28V, 6.5A, Low Iq, Synchronous Buck Converter With 2-Bit VID

NB681A
28V, 6.5A, Low Iq,

Synchronous Buck Converter with 2-Bit VID
DESCRIPTION FEATURES
The NB681A is a fully integrated, high-  Wide 4.5V to 28V Operating Input Range
frequency, synchronous, rectified, step-down,  VCCIO/PRIMCORE/EDRAM/EOPIO/V1.0A/
switch-mode converter with 2-bit VID, especially 1.8V/2.5V/3.3V Compatible for IMVP8
designed for IMVP8 applications—VCCIO,  Output Adjustable by 2-Bit VID
PRIMCORE, V1.0A, EDRAM, EOPIO, and  Low-Power Mode
other POLs (1.8V/2.5V/3.3V). It offers a very  25µA Low Quiescent Current
compact solution to achieve a 6.5A continuous  6.5A Continous Output Current
output current and a 7.5A peak output current  7.5A Peak Output Current
over a wide input supply range.
 Selectable Ultrasonic Mode
The NB681A operates at high efficiency over a  Adaptive COT for Fast Transient
wide output current load range based on MPS  DC Auto-Tune Loop
proprietary switching loss reduction technology  Stable with POSCAP and Ceramic
and internal low Ron power MOSFETs. Capacitors
Adaptive constant-on-time (COT) control mode  1% Reference Voltage
provides fast transient response and eases loop  Internal Soft Start
stabilization. The DC auto-tune loop provides  Output Discharge
good load and line regulation.  OCL, OVP, UVP, and Thermal Shutdown
 Latch-Off Reset via EN or Power Cycle
To avoid audible noise, the NB681A provides
low-power mode for power loss saving during  QFN-13 2mm x 3mm Package
the low-power state and ultrasonic mode. APPLICATIONS
Full protection features include OC limit, OVP,  Laptop Computers
UVP, and thermal shutdown.  Tablet PCs
The converter requires a minimal number of  Networking Systems
external components, and it is available in a  Servers
QFN-13 2mm x 3mm package.  Personal Video Recorders
 Flat Panel Televisions and Monitors
 Distributed Power Systems
All MPS parts are lead-free, halogen-free, and adhere to the RoHS directive. For
MPS green status, please visit the MPS website under Quality Assurance.
“MPS” and “The Future of Analog IC Technology” are registered trademarks of
Monolithic Power Systems, Inc.
TYPICAL APPLICATION
GND
LP# 150kΩ
VIN
220nF
4.5-24V VOUT
VIN LP# MODE BST
1.2μH 1.8V/6A
22μF EN SW
EN
GND VOUT
NB681A 66μF
C1 C1
C0 PGND
PG 3V3 AGND
AGND 100kΩ 3.3V

GND
1μF
AGND
NB681A Rev. 1.02 www.MonolithicPower.com 1

7/28/2017 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited.
© 2017 MPS. All Rights Reserved.
NB681A—28V, 6.5A HIGH CURRENT SYNCHRONOUS BUCK CONVERTER WITH 2-BIT VID
ORDERING INFORMATION
Part Number* Package Top Marking
NB681AGD QFN-13 (2mm x 3mm) See Below
* For Tape & Reel, add suffix –Z (e.g. NB681AGD–Z)
TOP MARKING
AQP: Product code of NB681AGD

Y: Year code
LLL: Lot number
PACKAGE REFERENCE
TOP VIEW
PG VOUT AGND 3V3
13 12 11 10
VIN 1 9 BST
8 SW
PGND 2 7 MODE
3 4 5 6
C1 C0 EN LP#

(4)
ABSOLUTE MAXIMUM RATINGS (1) Thermal Resistance θJA θJC
Supply voltage (VIN) .....................................28V QFN-13 (2mm x 3mm) ........... 70 ...... 15 ... C/W
VSW(DC) ............................................ -1V to 26V NOTES:
VSW (25 ns) .................................... -3.6V to 28V 1) Exceeding these ratings may damage the device.
2) The maximum allowable power dissipation is a function of the
VBST ..................................................VSW + 4.5V maximum junction temperature TJ(MAX), the junction-to-
IEN............................................................100µA ambient thermal resistance θJA, and the ambient temperature
TA. The maximum allowable continuous power dissipation at
All other pins ............................... -0.3V to +4.5V any ambient temperature is calculated by PD(MAX)=(TJ(MAX)-
(2)
Continuous power dissipation (TA = +25°C) TA)/θJA. Exceeding the maximum allowable power dissipation
will produce an excessive die temperature, causing the
QFN-13 (2mm x 3mm) ...............................1.8W regulator to go into thermal shutdown. Internal thermal
Junction temperature ............................... 150C shutdown circuitry protects the device from permanent
damage.
Lead temperature .................................... 260C 3) The device is not guaranteed to function outside of its
Storage temperature ................ -65C to +150C operating conditions.
4) Measured on JESD51-7, 4-layer PCB.
(3)
Recommended Operating Conditions
Supply voltage (VIN) ........................ 4.5V to 24V
Supply voltage (3V3) ................... 3.15V to 3.5V
Enable current (IEN)....................................50µA
Operating junction temp. (TJ). .. -40°C to +125°C

ELECTRICAL CHARACTERISTICS
VIN = 12V, 3V3 = 3.3V, TJ = 25C, LP# = 1, C1 = 1, C0 = 0, MODE = 0, unless otherwise noted.
Parameters Symbol Condition Min Typ Max Units
Supply Current
3V3 supply current in normal VEN = 3.3V, VLP# = 3.3V,
I3V3 150 μA
mode VOUT = 1V
3V3 supply current in LP# mode I3V3_LP# VEN = 3.3V, VLP# = 0 30 μA
3V3 shutdown current I3V3_SDN VEN = 0V 1 μA
MOSFET
High-side switch on resistance HSRDS-ON 36 mΩ
Low-side switch on resistance LSRDS-ON 13 mΩ
Switch leakage SW LKG VEN = 0V, VSW = 0V 0 1 μA
Current Limit
Low-side valley current limit ILIMIT_LS 7 7.6 8.5 A
Switching Frequency and Minimum Off Timer
(5)
Switching frequency FS Default 750 kHz
Constant on timer Ton VIN = 5V, VOUT = 1.0V 220 290 350 ns
(5)
Minimum on time TON_Min 50 ns
(5)
Minimum off time TOFF_Min 250 ns
Over-Voltage and Under-Voltage Protection
OVP threshold VOVP VFB 120% 130% 135% VREF
UVP-1 threshold VUVP VFB 70% 75% 80% VREF
(5)
UVP-1 hold off timer TOC VOUT = 60% VREF 64 μs
UVP-2 threshold VUVP VFB 45% 50% 55% VREF
Reference and Soft Start
(5)
LP# = 0 0 mV
LP# = 1, C1 = 0, C0 = 0 850 mV
VREF,
LP# = 1, C1 = 0, C0 = 1 875 mV
MODE=0
LP# = 1, C1 = 1, C0 = 0 940 950 960 mV
LP# = 1, C1 = 1, C0 = 1 975 mV
LP# = 0 700 mV
LP# = 1, C1 = 0, C0 = 0 850 mV
VREF,
Internal reference voltage LP# = 1, C1 = 0, C0 = 1 900 mV
MODE=Float
LP# = 1, C1 = 1, C0 = 0 950 mV
LP# = 1, C1 = 1, C0 = 1 1000 mV
(5)
LP# = 0 0 mV
LP# = 1, C1 = 0, C0 = 0 800 mV
VREF,
LP# =1, C1 = 0, C0 = 1 950 mV
MODE=100k
LP# = 1, C1 = 1, C0 = 0 990 1000 1010 mV
LP# = 1, C1 = 1, C0 = 1 1050 mV

ELECTRICAL CHARACTERISTICS (continued)

LP# = 0, C1 = 0, C0 = 0 1590 mV
LP# = 0, C1 = 0, C0 = 1 1990 mV
LP# = 0, C1 = 1, C0 = 0 2380 mV
VREF, LP# = 0, C1 = 1, C0 = 1 3300 mV
Internal reference voltage
MODE=150k LP# = 1, C1 = 0, C0 = 0 1200 mV
LP# = 1, C1 = 0, C0 = 1 1500 mV
LP# = 1, C1 = 1, C0 = 0 1800 mV
LP# = 1, C1 = 1, C0 = 1 2500 mV
Soft-start time TSS En to PG up 1.0 1.3 1.5 ms
MODE = float 5 10 mV/μs
VID change slew rate SRVID MODE = 100k 25 35 mV/μs
MODE = 0 10 20 mV/μs
(5)
VID change timer (EOPIO) TVID_EOPIO MODE = 100k 10 µs
(5) MODE = float 45 μs
LP# exit timer TLP#_exit
MODE = 0 or 100k 240 μs
MODE
MODE source current IMODE 9 10 11.6 μA
Enable and UVLO
EN UVLO rising threshold VEN_H_UVLO 1.1 1.2 1.3 V
EN hysteresis VEN_HYS 100 mV
EN high limit @ USM VEN_H_USM 1.7 V
(5)
EN low limit @ normal VEN_L_Normal 2.3 V
VEN = 3.3V 5
Enable input current IEN μA
VEN = 0V 0
VCC under-voltage lockout
VCCVth 2.8 3.0 3.13 V
threshold rising
VCC under-voltage lockout
VCCHYS 200 mV
threshold hysteresis
VIN under-voltage lockout
VINVTH 4.2 4.4 V
threshold rising
VIN under-voltage lockout
VINHYS 300 mV
threshold hysteresis
LP#, C1, and C0 Logic
Rising threshold VLH 0.39 0.6 0.79 V
Hysteresis VLHYS 100 mV
Input current ILIN V LP#,C1,C0 = 3.3V 1 μA

ELECTRICAL CHARACTERISTICS (continued)

Power Good
PG when Vout risng (good) PG_Rising(GOOD) VFB rising, percentage of VREF 95
PG when Vout falling (fault) PG_Falling(Fault) VFB falling, percentage of VREF 90
%
PG when Vout rising (fault) PG_Rising(Fault) VFB rising, percentage of VREF 115
PG when Vout falling (good) PG_Falling(GOOD) VFB falling, percentage of VREF 105
Power good low to high
PGTd 2 7 µs
delay
EN low to power good low
PGTd_EN low 1 µs
delay
PG sink current capability VPG Sink 4mA 0.4 V
Thermal Protection
(5)
Thermal shutdown TSD 145 °C
Thermal shutdown
(5) TSD_HYS 25 °C
hysteresis
NOTE:
5) Guaranteed by design.

PIN FUNCTIONS
PIN # Name Description
Supply voltage input. The NB681 operates from a +4.5V to +24V input rail. An input
1 VIN capacitor is needed to decouple the input rail. Use wide PCB traces and multiple vias to
make the connection with at least two layers for the input trace.
2 PGND Power ground. Use wide PCB traces and multiple vias to make the connection.
2-bit VID control input. Set C1 and C0 with MODE to get different voltage references for
3, 4 C1, C0
different rails. C1 and C0 are pulled high internally.
Enable. Drive EN high to turn on the buck regulator; drive EN low to turn off the buck
regulator. (There is an internal 800kΩ pull-down resistor on EN). EN determines USM. If EN
5 EN
is within 1.3V-1.7V, it is in USM. If EN > 2.3V, it is in normal mode. For normal operation, it
is recommended that EN rising finishes in < 1ms.
Low-power mode control signal. Pull LP# high in normal operation. Pull LP# low to enter
6 LP# low-power mode. U sually, LP# is controlled by the SLP#S0 of the system. LP# is pulled
high internally.
Selection for IMVP8 applications—VCCIO/PRIMCORE/EDRAM/EOPIO/V1.0A and other
7 MODE
POLs (1.8V/2.5V/3.3V) with external 1% resistors.
Switch output. Connect SW to the inductor and bootstrap capacitor. SW is connected to
VIN when the HS-FET is on; SW is connected to PGND when the LS-FET is on. Use wide
8 SW
and short PCB traces to make the connection. SW is noisy, so keep sensitive traces away
from SW.
Bootstrap. A >100nF capacitor connected between SW and BST is required to form a
9 BST
floating supply across the high-side switch driver.
External 3V3 VCC input for control and driver. Place a 1µF decoupling capacitor close to
10 3V3
3V3 and AGND.
Signal logic ground. Make a Kelvin connection to PGND near the VCC capacitor. AGND
11 AGND
can be applied as a remote sense ground with proper setting.
Output sense input. Connect VOUT to the remote output capacitor with good GND
12 VOUT decoupling. Keep the VOUT trace away from SW or other noisy nodes. It is recommended
to use a >20mil trace for the VOUT sense.
Power good output. PG is an open-drain signal. PG is high if the output voltage is higher
13 PG
than 95% of the nominal voltage or lower than 105% of the nominal voltage.

TYPICAL PERFORMANCE CHARACTERISTICS

VIN = 12V, VOUT = 1V, L = 1.0µH/10mΩ, RMDOE = 100kΩ, LP# = C1 = 1, C0 = 0, Rbst = 0, TJ = +25°C,
Cout = 22µF*3 unless otherwise noted.


VIN = 12V, VOUT = 1V, L = 1.0µH/10mΩ, RMODE= 100kΩ, LP# = C1 = 1, C0 = 0, Rbst = 0, TJ = +25°C,


VIN = 12V, VOUT = 1V, L = 1.0µH/10mΩ, RMODE = 100kΩ, LP# = C1 = 1, C0 = 0, Rbst = 0, TJ = +25°C,

FUNCTIONAL BLOCK DIAGRAM

AGND 3V3 MODE LP# EN VIN
VIN BSTREG BST

POR &
Soft Start VIN
Reference
VOUT
Vout
VOUT
On-Time
REF One Shot
Min Off Time SW

Control
Logic
VOUT
DC Error
+
Correction +
Output
Discharge PGND
C1 REF
Vref
Control
C0
SW OC Limit
MODE
130% Vref OVP
PG
90% Vref POK
Vout Fault
Logic
50% Vref UVP-2
75% Vref UVP-1
Figure 1: Functional Block Diagram

OPERATION
PWM Operation Continuous conduction mode (CCM) occurs
when the output current is high, and the inductor
The NB681A is a fully integrated, synchronous,
current is always above zero amps (see Figure 2).
rectified, step-down, switch-mode converter,
When VFB is below VREF, the HS-FET is turned on
especially designed for IMVP8 applications—
for a fixed interval. When the HS-FET is turned
VCCIO, PRIMCORE, EDRAM, EOPIO, V1.0A,
off, the LS-FET is turned on until the next period.
and other POLs (1.8V/2.5V/3.3V). Constant-on-
time (COT) control provides fast transient In CCM operation, the switching frequency is
response and eases loop stabilization. At the fairly constant (PWM mode).
beginning of each cycle, the high-side MOSFET
DCM Operation
(HS-FET) is turned on when the feedback
voltage (VFB) is below the reference voltage When the load decreases, the inductor current
(VREF), which indicates insufficient output voltage. will decrease as well. Once the inductor current
The on period is determined by the output reaches zero, the part transitions from CCM to
voltage and the input voltage to make the discontinuous conduction mode (DCM).
switching frequency fairly constant over the input DCM operation is shown in Figure 3. When VFB is
voltage range. below VREF, the HS-FET is turned on for a fixed
After the on period elapses, the HS-FET is turned interval, which is determined by the one-shot on
off or enters an off state. It is turned on again timer. See Equation (1). When the HS-FET is
when VFB drops below VREF. By repeating turned off, the LS-FET is turned on until the
operation this way, the converter regulates the inductor current reaches zero. In DCM operation,
output voltage. The integrated low-side MOSFET the VFB does not reach VREF when the inductor
(LS-FET) is turned on when the HS-FET is in its current approaches zero. The LS-FET driver
off state to minimize the conduction loss. A dead turns into tri-state (high Z) when the inductor
short occurs between the input and GND if both current reaches zero. A current modulator takes
the HS-FET and the LS-FET are turned on at the over the control of the LS-FET and limits the
same time (shoot-through). In order to avoid inductor current to less than -1mA. Hence, the
shoot-through, a dead time (DT) is generated output capacitors discharge slowly to GND
internally between the HS-FET off and the LS- through the LS-FET. As a result, the efficiency at
FET on period or the LS-FET off and the HS-FET light-load is improved greatly. The HS-FET is not
on period. turned on as frequently during a light-load
condition as it is during a heavy-load condition
Internal compensation is applied for COT control (skip mode).
for stable operation even when ceramic
capacitors are used as output capacitors. This At a light-load or no-load condition, the output
internal compensation improves the jitter drops very slowly, and the NB681A reduces the
performance without affecting the line or load switching frequency naturally, achieving high
regulation. efficiency at light load.
CCM Operation
Figure 3: DCM Operation
Figure 2: CCM Operation

Table 1: MODE Selection for Different Rails

As the output current increases from the light-
load condition, the time period within which the Resistor to GND
MODE VR Rail
(1% Accuracy)
current modulator regulates becomes shorter.
M1 VCCIO 0
The HS-FET is turned on more frequently; the
switching frequency increases accordingly. The M2 PRIMCORE Float or > 230K
output current reaches the critical level when the M3 EDRAM/V1.0A/EOPIO 100K
current modulator time is zero. The critical level M4 Others 150K
of the output current is determined with Equation Low-Power Mode
(1):
To minimize power loss at light-load, the NB681A
(VIN  VOUT )  VOUT
IOUT  (1) enters low-power mode once LP# is set to low.
2  L  FSW  VIN NB681A is allowed to decay to the LPM target
The device enters PWM mode once the output value with the assertion of LP#. When VR enters
current exceeds the critical level. After that, the LPM, it behaves in the following manner:
switching frequency stays fairly constant over the  PG remains high to all power good logic.
output current range.  VR stops switching (except PRIMCORE
DC Auto-Tune Loop mode).
NB681A applies a DC auto-tune loop to balance  The output decays into the load (discharge
the DC error between VFB and VREF by adjusting circuitry is off) and decays to 0V.
the comparator input REF to make VFB always Once LP# changes from 0V to 1V, the NB681A
follow VREF. This loop is quite slow, so it improves exits LPM by ramping up Vout (with a proper
the load and line regulation without affecting delay and slew rate) to make sure the output is
transient performance. The relationship between ready in 240µs, including the delay time (Tdelay).
VFB, VREF, and REF is shown in Figure 4. The operation timing and slew rate of LP# and
Vout is shown in Figure 5.
VFB DC VREF
Error
LP#
REF
Figure 4: DC Auto-Tune Loop Operation Vo Vout decays to the

Tdelay
LPM target
LPM exits SR
VCCIO/PRIMCORE/EDRAM/EOPIO/V1.0A Tdelay
MODE Selection
Figure 5: LPM Voltage Transition and Timing
NB681A combines mode selection to support
different rails in IMVP8 applications, including The LPM target value, slew rate, and PG state
VCCIO, PRIMCORE, EDRAM, EOPIO, and for different rails are listed in Table 2.
V1.0A. These rails have different (normal) VID
and different voltages in LPM, VID slew rate, and Table 2: Intel LPM Specification for Each Rail
other features. By selecting a different resistor
from MODE to GND, NB681A can be applied in EDRAM/
PRIMCORE VCCIO OTHER
different rails with proper features. Table 1 shows EOPIO
the resistor settings on MODE to enter different LPM
0.7 0 0 0
rails. Target(V)
LPM Enter Decay Decay Decay Decay
LPM Exit
45 240 240 240
Timer(μs)
PG during
High High High High
LPM

Control Bit Definitions (LP# and VID) Table 4 : EN/LP# Control

EN LP# Output PG
The control bit definitions, including LP# and
VIDx for different rails, are shown in Table 3. 0 0 0V, Off Low
Note that C1, C0, and LP# are NOT allowed to 0 1 0V, Off Low
change on-the-fly when the part is working in
Normal turn on
Others mode. and fall to LP#
Asserted when the output
reaches the nominal
Table 3 : Control Bit Logics 1 0 target value
voltage and remains high
after
during LP# = 0
LP# C1 C0 VOUT(V) PG + 1 ms
0 X X 0 Remains asserted after

1 1 High
SS
1 0 0 0.85
VCCIO 1 0 1 0.875 Soft Start (SS)
1 1 0 0.95 The NB681A employs a soft-start (SS)
mechanism to ensure smooth output during
1 1 1 0.975
power-up. When EN goes high, the internal
0 X X 0.7 reference voltage ramps up gradually; hence, the
1 0 0 0.85
output voltage ramps up smoothly as well. Once
VCCPRIM the reference voltage reaches the target value,
1 0 1 0.9 the soft start finishes, and the part enters steady-
_CORE
1 1 0 0.95 state operation.
1 1 1 1.00 If the output is pre-biased to a certain voltage
during start-up, the IC disables the switching of
0 X X 0
both the high-side and low-side switches until the
EDRAM/ 1 0 0 0.8 (MSM) voltage on the internal reference exceeds the
EOPIO/ 1 0 1 0.95 sensed output voltage at the internal FB node.
V1.0A 1 1 0 1 Power Good (PG)
1 1 1 1.05 The NB681A has power good (PG) output used
to indicate whether the output voltage of the buck
0 0 0 1.59
regulator is ready. PG is an open drain of a
0 0 1 1.99 MOSFET. It should be connected to 3V3 or
Others 0 1 0 2.38 another voltage source through a resistor (e.g.
(Fixed 100k). After the input voltage is applied, the
0 1 1 3.3
design only, MOSFET is turned on, so that PG is pulled to
not allowed 1 0 0 1.2 GND before SS is ready. After the FB voltage
for changing
on-the-fly) 1 0 1 1.5 reaches 95% of VREF, PG is pulled high in less
than 10µs. When the FB voltage drops to 90% of
1 1 0 1.8
VREF (or rises higher than 115% of VREF), PG is
1 1 1 2.5 pulled low.
Configuring EN Control Note that when LP# goes from 10, PG stays
EN is used to enable or disable the whole chip. high for all the power good logic.
Pull EN high to turn on the regulator; pull EN low Start-Up and Shutdown Sequence
to turn off the regulator. It is recommended to
have EN rise from 0V to over 2.3V in less than Figure 6 shows the start-up and shutdown
1ms. Note that there is an internal 800KΩ pull- sequence, including LP# and PG. During start-up,
down resistor on EN. PG goes high immediately when Vout reaches its
normal range. LP# mode is blanked until
EN works with the LP# signal to control the PG + 1ms, meaning the NB681A is not able to
output (see Table 4). enter LP# mode during the start-up period + 1 ms.

Vout decays to the target LPM setting when LP# Over-Current Protection (OCP)
pulls low and is able to ramp up to its normal NB681A has cycle-by-cycle over-current limiting
value in the Intel required timing. PG pulls low control. The current-limit circuit employs a
immediately after EN goes low. "valley" current-sensing algorithm. The part uses
the Rds(on) of the LS-FET as a current-sensing
VIN
element. If the magnitude of the current is above
the current-limit threshold, the PWM is not
0
allowed to initiate a new cycle even if FB is lower
3.3V
than REF. Figure 7 shows the detailed operation
EXT
VCC
of the valley current limit.
0
Valley_ILim
EN
0
FB
1ms REF
LP# LP# Masked Area

0
<240us
PWM
Vo
0 FB<Vref Ton trigger after IL
reach valley I_lim
Soft Start
Figure 7: Valley Current-Limit Operation
PG Keep high during
PG
0
LP#=0 period if no fault
occurs
Since the comparison is done during the LS-FET
on state, the OC trip level sets the valley level of
PG on immediately PG off once EN off the inductor current. The maximum load current
once Vo is settled
Figure 6: Power Sequence and EN/PG Logic Ultra- at the over-current threshold (Ioc) can be
Sonic Mode calculated using Equation (2):
Ultra-sonic mode (USM) is designed to keep the Iinductor
IOC  I _ limit  (2)
switching frequency above an audible frequency 2
area during light-load or no-load conditions. Once The OCL itself only limits the inductor current and
the part detects both the HS-FET and the LS- does not latch off. In an over-current condition,
FET are off (for about 32µs), it will force PWM to the current to the load exceeds the current to the
initiate Ton, so the switching frequency will be output capacitor; thus the output voltage tends to
out of audio range. To avoid Vout becoming too fall off. Eventually, it ends up crossing the under-
high, it shrinks Ton to control the Vout. If the FB voltage protection (UVP) threshold and latches
is still too high after shrinking Ton to its minimum off. Fault latching can be re-set by EN going low
value, the output discharge function is activated, or the power-cycling of VIN.
keeping Vout within a reasonable range. USM is
Over/Under-Voltage Protection (OVP/UVP)
selected by the voltage threshold on EN (see
Table 5). To enter USM, set EN with two NB681A monitors the output voltage to detect
resistors as a divider (e.g. two 100kΩ resistors over and under voltage. When the feedback
from 3.3V logic to get 1.65V). voltage becomes higher than 130% of the
Table 5: USM Selection feedback voltage, the OVP comparator output
goes high, and the circuit latches (as the HS-FET
Mode Voltage on EN driver turns off, and the LS-FET driver turns on),
acting as a -2A current source.
USM 1.3V < EN < 1.7V
Normal operation 2.3V < EN < 3.5V

To protect the part from damage, there is an Remote Sense

absolute 3.9V OVP on VOUT. Once Vout
When remote sense is required, AGND acts as
reaches this value, it latches off. The LS-FET
remote sen-, which is connected to the remote
behaves the same as at 130% OVP. This OVP is
ground of the output capacitors. VOUT acts as
active even in LP# mode.
remote sen+. The VCC capacitor connected
When the feedback voltage becomes lower than between 3V3 and AGND is still required and
75% of Vref, the UVP-1 comparator output goes should be placed very close to the IC. Figure 9
high, and the part latches if the FB voltage stays shows the SCH with a remote sense connection.
in this range for about 64µs (latching the HS-FET For additional remote sense details, refer to
off and LS-FET on). The LS-FET remains on until AN086 .
the inductor current hits zero. During this period,
the valley current limit helps control the inductor
current.
When the feedback voltage drops below 60% of
the Vref, the UVP-2 comparator output goes high,
and the part latches off directly after the
comparator and logic delay (latching the HS-FET
off and the LS-FET on). The LS-FET remains on
until the inductor current hits zero. Fault latching
can be reset by EN going low or the power
cycling of VIN or VCC.
UVLO Protection
The NB681A has two kinds of under-voltage
lockout protection: a 3V VCC UVLO and a 4.2V
Vin UVLO. The part starts up only when both the
VCC and Vin exceed their own UVLO. The part
shuts down when either the VCC voltage is lower
than the UVLO falling threshold voltage (2.8V,
typically), or the VIN is lower than the 3.9V Vin
falling threshold. Both UVLO protections are non-
latch off.
Thermal Shutdown (TSD)
Thermal shutdown is employed in the NB681A.
The junction temperature of the IC is monitored
internally. If the junction temperature exceeds the
threshold value (145ºC, typically), the converter
shuts off. This is a non-latch protection. There is
about 25ºC hysteresis. Once the junction
temperature drops to about 120ºC, it initiates a
SS.
Output Discharge
NB681A discharges the output when EN is low,
or the controller is turned off by the protection
functions UVP, OVP, UVLO, and thermal
shutdown. The part discharges the outputs using
an internal 3Ω MOSFET.

VOUT V 1 (7)
APPLICATION INFORMATION VOUT   (1  OUT )  (RESR  )
FSW  L VIN 8  FSW  COUT
Input Capacitor
The input current to the step-down converter is When using ceramic capacitors, the impedance
discontinuous, and therefore requires a capacitor at the switching frequency is dominated by the
to supply the AC current to the step-down capacitance. The output voltage ripple is caused
converter while maintaining the DC input voltage. mainly by the capacitance. For simplification, the
Ceramic capacitors are recommended for best output voltage ripple can be estimated with
performance and should be placed as close to Equation (8):
VIN as possible. Capacitors with X5R and X7R
VOUT V
ceramic dielectrics are recommended because VOUT   (1  OUT ) (8)
they are fairly stable with temperature 8  FSW  L  COUT
2
VIN
fluctuations.
The capacitors must have a ripple current rating When using POSCAP capacitors, the ESR
greater than the maximum input ripple current of dominates the impedance at the switching
the converter. The input ripple current can be frequency. The output ripple can be
estimated using Equation (3) and Equation (4): approximated with Equation (9):
VOUT V
VOUT V VOUT   (1  OUT )  RESR (9)
ICIN  IOUT   (1  OUT ) (3) FSW  L VIN
VIN VIN
The maximum output capacitor limitation should
The worst-case condition occurs at VIN = 2VOUT,
be considered in design application. For a small
where:
soft-start time period (if the output capacitor
IOUT
ICIN  (4) value is too high), the output voltage cannot
2 reach the design value during the soft-start time,
causing it to fail to regulate. The maximum output
For simplification, choose an input capacitor with
capacitor value (Co_max) can be limited
an RMS current rating greater than half of the
approximately using Equation (10):
maximum load current.
The input capacitor value determines the input CO _ MAX  (ILIM _ AVG  IOUT )  Tss / VOUT (10)
voltage ripple of the converter. If there is an input
voltage ripple requirement in the system, choose Where ILIM_AVG is the average start-up current
the input capacitor that meets the specification. during the soft-start period (it can be equivalent
to the current limit value), and Tss is the soft-start
The input voltage ripple can be estimated using time.
Equation (5) and Equation (6):
Inductor
IOUT V V (5)
VIN   OUT  (1  OUT ) The inductor is necessary to supply constant
FSW  CIN VIN VIN
current to the output load while being driven by
The worst-case condition occurs at VIN = 2VOUT, the switched input voltage. A larger value
where: inductor results in less ripple current, resulting in
1 I (6) a lower output ripple voltage. However, a larger
VIN   OUT
4 FSW  CIN value inductor will have a larger physical footprint,
a higher series resistance, and/or a lower
Output Capacitor saturation current. A good rule for determining
An output capacitor is required to maintain the the inductance value is to design the peak-to-
DC output voltage. Ceramic or POSCAP peak ripple current in the inductor to be in the
capacitors are recommended. The output voltage range of 30% to 50% of the maximum output
ripple can be estimated with Equation (7): current with the peak inductor current below the
maximum switch current limit. The inductance
value can be calculated using Equation (11):

VOUT V
L  (1  OUT ) (11)
FSW  IL VIN
Where ΔIL is the peak-to-peak inductor ripple
current.
The inductor should not saturate under the
maximum inductor peak current (including short
current), so it is suggested to choose Isat >7.5A.

PCB LAYOUT GUIDELINES

Efficient PCB layout is critical for the 4. Keep the BST voltage path as short as
performance of the IC. For best results, refer to possible with a > 25mil trace.
Figure 8 and follow the guidelines below. For 5. Keep the IN and GND pads connected with a
more information, refer to AN087. large copper plane to achieve better thermal
1. Place the high-current paths (PGND, IN, and performance. Add several vias (with 10mil
SW) very close to the device with short, direct, drill/18mil copper width) close to the IN and
and wide traces. A wide PGND trace under GND pads to help thermal dissipation.
the IC is the number one priority. 6. A 4-layer layout is recommended to achieve
2. Place the input capacitors as close to IN and better thermal performance.
GND as possible on the same layer as the IC. 7. Use a >20mil trace for the Vout sense for
3. Place the decoupling capacitor as close to output discharge.
VCC and GND as possible. Keep the
switching node (SW) short and away from the
feedback network.
AGND-PGND
KELVIN CONNECTION
LP# GND
0402
3V3
PG Vout AGND 3V3

13 12 11 10
0603
Vin MODE
VIN
Vin 1 9 BST
8 SW SW
PGND 2 7
MODE
3 4 5 6
C1 C0 EN LP#
L
6mm*6mm
PGND
VOUT
0805
VOUT
Figure 8: Recommended PCB Layout

Recommended Design Example Table 6.1: Design Example for Different Rails
Design examples are provided in Table 6.1 when VOUT (V)
RMode Cout L
ceramic capacitors are applied. (Ω) (F) (μH)
VCCIO 0 22μx3 0.68~1
There is a resistor from the external 3.3V power PRIMCORE Float 22μx3 0.68~1
supply to 3V3 acting as the ripple noise filter of
EDRAM/
the 3.3V power supply. It is recommended that EOPIO/ 100K 22μx3 0.68~1
the resistor have a value from 0Ω-5.1Ω, V1.0A
depending on the noise level. A 0402 size Others-
resistor will suffice if the 3.3V voltage rises with a 150K 22μx4 1.0~1.5
1.8V/2.5V
soft-start timer > 100µs. Otherwise, a larger size Others-3.3V 150K 22μx4
[6]
1.2~1.5
resistor (e.g., 0603/0805) is needed. [6]
Note : If Vin is lower than 7V, apply a 150µF POSCAP as
Cout, considering the transient.

TYPICAL APPLICATION—FOR DIFFERENT RAILS

VCCIO
SLP# GND
2.2Ω
VIN
220nF
4.5-24V VOUT
VIN LP# MODE BST
0.68μH 0.95V/6.5A
EN EN SW
22F
VOUT
3.3V NB681A 22μF*3
GND C1
20kΩ
C0 PGND
20kΩ PG 3V3 AGND
100kΩ 5.1Ω 3.3V

AGND GND
1μF
AGND
Figure 8.1: Typical Application Schematic for VCCIO, Default 0.95V (C1 and C0 can be Pulled
High/Floating or Low Directly without a Resistor if Vout is Fixed)
PRIMCORE
SLP#
2.2Ω
VIN
220nF
4.5-24V VOUT
VIN LP# MODE BST
0.68μH 1.0V/6.5A
EN EN SW
22μF
VOUT
NB681A 22μF*3
GND C1 C1
C0 C0 PGND
PG 3V3 AGND
100kΩ 5.1Ω 3.3V

GND
1μF
AGND
Figure 8.2: Typical Application Schematic for PRIMCORE, Vout Adjusted by VID

TYPICAL APPLICATION—FOR DIFFERENT RAILS

EDRAM & V1.0A
GND
SLP#
100k 2.2Ω
VIN
220nF
4.5-24V VOUT
VIN LP# MODE BST
0.68μH 1V/6.5A
EN EN SW
22μF
VOUT
3.3V NB681A 22μF*3
GND C1
20kΩ
C0 PGND
20kΩ PG 3V3 AGND
100kΩ 5.1Ω 3.3V

AGND GND
1μF
AGND
Figure 8.3: Typical Application Schematic for EDRAM and V1.0A, Default 1V, (C1 and C0 can be
Pulled High/Floating or Low Directly without a Resistor if Vout is Fixed)
EOPIO
GND
ZVM#
100k 2.2Ω
VIN
220nF
4.5-24V VOUT
VIN LP# MODE BST
0.68μH 1V-0.8V/6.5A
EN EN SW
22μF
VOUT
20kΩ NB681A 22μF*3
GND 3.3V C1
MSM#
C0 PGND
PG 3V3 AGND
20kΩ
100kΩ 5.1Ω 3.3V
GND
AGND
1μF
AGND
Figure 8.4: Typical Application Schematic for EOPIO

TYPICAL APPLICATION--FOR DIFFERENT RAILS

Others (1.8V)
GND
150kΩ 2.2Ω
VIN
4.5-24V 220nF
VOUT
VIN LP# MODE BST
1.2μH 1.8V/6.5A
22μF EN SW
EN
GND VOUT
NB681 22μF*4
C1
C0 PGND
PG 3V3 AGND
AGND 100kΩ 5.1Ω 3.3V

GND
1μF
AGND
Figure 8.5: Typical Application Schematic for Others Mode (1.8V)
Others (2.5V)
GND
150k 2.2Ω
VIN
220nF
4.5-24V VOUT
VIN LP# MODE BST
1.5μH 2.5V/6.5A
EN EN SW
22μF
VOUT
NB681A 22μF*4
GND C1
C0 PGND
PG 3V3 AGND
100kΩ 5.1Ω 3.3V

GND
1μF
AGND
Figure 8.6: Typical Application Schematic for Others Mode (2.5V)

TYPICAL APPLICATION—WITH REMOTE SENSE

For additional details on remote sense application, refer to AN086.
SLP#
2.2Ω
VIN
220nF
4.5-24V
VIN LP# MODE BST
0.68μH
EN EN SW VOUT
22μF
6.8Ω 1.0V/6.5A
VOUT 22μF*3 VOUT
GND NB681A
C1 C1
PGND
100Ω
C0 AGND
C0 GND 0Ω
PG 3V3 Remote SEN+
0Ω
100kΩ 5.1Ω 3.3V Remote SEN-
1μF 100Ω
Short Pad or 0-6.8ohm

VCC Cap always place GND
close to VCC and AGND
AGND AGND GND
Figure 9: Typical Application Schematic for NB681 Remote Sense Application

NOTE 1: Ultrasonic mode is not effective if applied in this SCH, make sure EN rising finishes in 1ms.
TYPICAL APPLICATION—WITH VOUT OUT OF VID TABLE

The two red resistors on VOUT act as feedback resistors to adjust the Vout to the proper value. It is
recommended to choose the closest VID value (which is lower than the target Vout) as Vref if there are
no other limitations. Figure 10 shows the typical SCH with the Vout setting at 1.1V.
GND
ZVM#
100k 2.2Ω
VIN
220nF
4.5-24V VOUT
VIN LP# MODE BST
0.68μH 1.1V/6.5A
EN EN SW
22μF
825Ω
GND VOUT
20kΩ NB681A 22μF*3
GND 3.3V C1 20kΩ
3.3V C0 PGND
20kΩ AGND
PG 3V3
GND
100kΩ 5.1Ω 3.3V
GND
1μF
AGND
Figure 10: Typical Application Schematic for NB681 with Vout from the VID Table
NOTE 2: Ultra-sonic mode is not effective if applied in this SCH, make sure EN rising finishes in 1ms.
NOTE 3: It is not recommended to set Vout over 50% of the target VREF.

PACKAGE INFORMATION
QFN-13 (2mm x 3mm)
PIN 1 ID
MARKING
PIN 1 ID
INDEX AREA
TOP VIEW BOTTOM VIEW
SIDE VIEW
NOTE:
1) ALL DIMENSIONS ARE IN MILLIMETERS.

2) EXPOSED PADDLE SIZE DOES NOT
INCLUDE MOLD FLASH.
3) LEAD COPLANARITY SHALL BE 0.10
MILLIMETERS MAX.
4) JEDEC REFERENCE IS MO-220.
5) DRAWING IS NOT TO SCALE.
RECOMMENDED LAND PATTERN
NOTICE: The information in this document is subject to change without notice. Users should warrant and guarantee that third
party Intellectual Property rights are not infringed upon when integrating MPS products into any application. MPS will not
assume any legal responsibility for any said applications.


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NB681A

28V, 6.5A, Low Iq,

AGND 100kΩ 3.3V

NB681A Rev. 1.02 www.MonolithicPower.com 1

* For Tape & Reel, add suffix –Z (e.g. NB681AGD–Z)

AQP: Product code of NB681AGD

NB681A Rev. 1.02 www.MonolithicPower.com 2

NB681A Rev. 1.02 www.MonolithicPower.com 3

NB681A Rev. 1.02 www.MonolithicPower.com 4

ELECTRICAL CHARACTERISTICS (continued)

NB681A Rev. 1.02 www.MonolithicPower.com 5

ELECTRICAL CHARACTERISTICS (continued)

NB681A Rev. 1.02 www.MonolithicPower.com 6

NB681A Rev. 1.02 www.MonolithicPower.com 7

TYPICAL PERFORMANCE CHARACTERISTICS

NB681A Rev. 1.02 www.MonolithicPower.com 8

TYPICAL PERFORMANCE CHARACTERISTICS

NB681A Rev. 1.02 www.MonolithicPower.com 9

TYPICAL PERFORMANCE CHARACTERISTICS

NB681A Rev. 1.02 www.MonolithicPower.com 10

FUNCTIONAL BLOCK DIAGRAM

VIN BSTREG BST

Min Off Time SW

130% Vref OVP

50% Vref UVP-2

75% Vref UVP-1

Figure 1: Functional Block Diagram

NB681A Rev. 1.02 www.MonolithicPower.com 11

Figure 3: DCM Operation

Figure 2: CCM Operation

NB681A Rev. 1.02 www.MonolithicPower.com 12

Table 1: MODE Selection for Different Rails

Figure 4: DC Auto-Tune Loop Operation Vo Vout decays to the

NB681A Rev. 1.02 www.MonolithicPower.com 13

Control Bit Definitions (LP# and VID) Table 4 : EN/LP# Control

0 X X 0 Remains asserted after

NB681A Rev. 1.02 www.MonolithicPower.com 14

LP# LP# Masked Area

NB681A Rev. 1.02 www.MonolithicPower.com 15

To protect the part from damage, there is an Remote Sense

NB681A Rev. 1.02 www.MonolithicPower.com 16

NB681A Rev. 1.02 www.MonolithicPower.com 17

NB681A Rev. 1.02 www.MonolithicPower.com 18

PCB LAYOUT GUIDELINES

PG Vout AGND 3V3

Figure 8: Recommended PCB Layout

NB681A Rev. 1.02 www.MonolithicPower.com 19

TYPICAL APPLICATION—FOR DIFFERENT RAILS

20kΩ PG 3V3 AGND

100kΩ 5.1Ω 3.3V

100kΩ 5.1Ω 3.3V

NB681A Rev. 1.02 www.MonolithicPower.com 20

TYPICAL APPLICATION—FOR DIFFERENT RAILS

20kΩ PG 3V3 AGND

100kΩ 5.1Ω 3.3V

Figure 8.4: Typical Application Schematic for EOPIO

NB681A Rev. 1.02 www.MonolithicPower.com 21