APW7142
APW7142
APW7142
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• Adjustable Output Voltage from 0.8V to VIN APW7142, designed with a current-mode control scheme,
- ±2% System Accuracy can convert wide input voltage of 4.3V to 14V to the output
voltage adjustable from 0.8V to VIN to provide excellent
• 70mΩ Integrated Power MOSFETs
output voltage regulation.
• High Efficiency up to 95%
For high efficiency over all load current range, the
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- Automatic Skip/PWM Mode Operation
APW7142 is equipped with an automatic Skip/PWM mode
• Current-Mode Operation
operation. At light load, the IC operates in the Skip mode,
- Easy Feedback Compensation
which keeps a constant minimum inductor peak current,
- Stable with Low ESR Output Capacitors to reduce switching losses. At heavy load, the IC works in
- Fast Load/Line Transient Response PWM mode, which inductor peak current is programmed
•
•
•
•
Power-On-Reset Monitoring
Fixed 500kHz Switching Frequency in PWM Mode
Built-In Digital Soft-Start and Soft-Stop
IC
Current-Limit Protection with Frequency Foldback
by the COMP voltage, to provide high efficiency and excel-
lent output voltage regulation.
The APW7142 is also equipped with power-on-reset,
soft-start, soft-stop, and whole protections (under-voltage,
over-voltage, over-temperature, and current-limit) into a
•
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123% Over-Voltage Protection
single package. In shutdown mode, the supply current
• Hiccup-Mode 50% Under-Voltage Protection
drops below 3µA.
• Over-Temperature Protection
This device, available in a 8-pin SOP-8 package, pro-
• <3µA Quiescent Current in Shutdown Mode
vides a very compact system solution with minimal exter-
• Small SOP-8 Package
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Applications 80
IP
70
Efficiency (%)
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
OM
G : Halogen and Lead Free Device
APW7142
APW7142 K : XXXXX XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
.C
MSL classification at lead-free peak reflow temperature. ANPEC defines “Green” to mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Pin Configuration
PGND
VIN
AGND
FB
1
2
3
4
APW7142
8
7
6
5
LX
LX
EN
COMP
IC
T-
SOP-8
Top View
o
TSDR Maximum Lead Soldering Temperature, 10 Seconds 260 C
Note 1: Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol Parameter Typical Value Unit
Junction-to-Ambient Thermal Resistance in Free Air (Note 2)
θJA
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80 C/W
SOP-8
Note 2: θJA is measured with the component mounted on a high effective thermal conductivity test board in free air.
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Converter Output Capacitor 20 ~ 1000 µF
COUT
Effective Series Resistance 0 ~ 60 mΩ
LOUT Converter Output Inductor 1 ~ 22 µH
Resistance of the Feedback Resistor connected from FB to GND 1 ~ 20 kΩ
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TA Ambient Temperature -40 ~ 85 C
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TJ Junction Temperature -40 ~ 125 C
Electrical Characteristics
Symbol Parameter
IC
Refer to the typical application circuits. These specifications apply over VIN=12V, VOUT=3.3V and TA= -40 ~ 85°C, unless otherwise
Test Conditions
APW7142
Unit
T-
Min. Typ. Max.
SUPPLY CURRENT
IVIN VIN Supply Current VFB = VREF +50mV, VEN=3V, LX=NC - 0.5 1.5 mA
IVIN_SD VIN Shutdown Supply Current VEN = 0V - - 3 µA
POWER-ON-RESET (POR) VOLTAGE THRESHOLD
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FOSC Oscillator Frequency TJ = -40 ~ 125oC, VIN = 4.75 ~ 14V 450 500 550 kHz
Foldback Frequency VOUT = 0V - 80 - kHz
Maximum Converter’s Duty - 99 - %
TON_MIN Minimum Pulse Width of LX - 150 - ns
CURRENT-MODE PWM CONVERTER
Gm Error Amplifier Transconductance VFB=VREF±50mV - 200 - µA/V
Error Amplifier DC Gain COMP = NC - 80 - dB
APW7142
Symbol Parameter Test Conditions Unit
Min. Typ. Max.
CURRENT-MODE PWM CONVERTER (CONT.)
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Current-Sense to COMP Voltage
- 0.048 - V/A
Transresistance
VIN = 5V, TJ=25°C - 90 110
High-side Switch Resistance mΩ
VIN = 12V, TJ=25°C - 70 90
VIN = 5V, TJ=25°C - 90 110
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Low-side Switch Resistance mΩ
VIN = 12V, TJ=25°C - 70 90
PROTECTIONS
ILIM High-Side Switch Current-Limit Peak Current 4.0 5.5 7.0 A
VTH_UV FB Under-Voltage Threshold VFB falling 45 50 55 %
VTH_OV FB Over-Voltage Threshold VFB rising 118 123 128 %
TOTP
TD
FB Under-Voltage Debounce
Over-Temperature Trip Point
Over-Temperature Hysteresis
Dead-Time
IC
VLX = -0.7V
-
-
-
-
1
150
40
20
-
-
-
-
µs
o
ns
C
C
T-
SOFT-START, SOFT-STOP, ENABLE AND INPUT CURRENTS
TSS Soft-Start / Soft-Stop Interval 1.5 2 2.5 ms
EN Logic Low Voltage VEN falling - - 0.5 V
EN Logic High Voltage VEN rising 2.1 - - V
High-Side Switch Leakage Current VEN = 0V, VLX = 0V - - 2 µA
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Efficiency (%)
70 3.34
60 3.32
VIN=5V, VOUT=3.3V, L1=2.2µF
50 3.3
40 3.28
VIN=12V, VOUT=5V, L1=6.8µF
3.26
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30
20 3.24
VIN=12V, VOUT=3.3V, L1=4.7µF
10 3.22
0 3.2
0.001 0.01 0.1 1 10 0 1 2 3
Output Current, IOUT(A) Output Current, IOUT(A)
7
Current Limit Level (Peak Current)
vs. Junction Temperature IC 3.4
3.38
Output Voltage vs. Supply Voltage
IOUT=500mA
Current Limit Level, ILIM(A)
6.5 3.36
T-
3.34
6 3.32
3.3
5.5 3.28
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3.26
5 3.24
3.22
4.5 3.2
-40 -20 0 20 40 60 80 100 120 140 4 6 8 10 12 14
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Junction Temperature, TJ ( C) Supply Voltage, VIN (V)
VIN Input Current vs. Supply Voltage Reference Voltage vs. Junction Temperature
2.0 0.816
VFB=0.85V
0.812
Reference Voltage, VREF (V)
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VIN Input Current, I VIN(mA)
1.5 0.808
0.804
1.0 0.800
0.796
0.5 0.792
0.788
0.0 0.784
0 2 4 6 8 10 12 14 -50 -25 0 25 50 75 100 125 150
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530
520
510
500
490
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480
470
460
450
-50 -25 0 25 50 75 100 125 150
o
Junction Temperature, TJ ( C)
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Operating Waveforms
(Refer to the application circuit 1 in the section “Typical Application Circuits”, VIN=12V, VOUT=3.3V, L1=4.7µH)
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IOUT=3A IOUT=3A
VIN
VIN
1 1
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VOUT
VOUT
2 2
IL1 IL1
3
Enable Shutdown
IOUT=3A
IOUT=3A
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VEN VEN
1 1
VOUT VOUT
2 2
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IL1 IL1
3 3
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IOUT =3~7A VOUT is shorted to GND by a short wire
VLx
1 VLX
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VOUT
VOUT
2 2
IL1 IL1
3
IL1 IL1
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2 2
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IOUT=0.2A VLX VLX
IOUT=3A
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1 1
IL1
IL1
2 2
VIN
VOUT
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1 1
VOUT VLX
2 2
IL1 3
IL1
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3
IOUT=-1A
Pin Description
PIN
FUNCTION
NO. NAME
Power Ground of the APW7142, which is the source of the N-channel power MOSFET.
1 PGND
Connect this pin to system ground with lowest impedance.
Power Input. VIN supplies the power (4.3V to 14V) to the control circuitry, gate drivers
and step-down converter switches. Connecting a ceramic bypass capacitor and a
OM
2 VIN
suitably large capacitor between VIN and both of AGND and PGND eliminates switching
noise and voltage ripple on the input to the IC.
3 AGND Ground of MOSFET Gate Drivers and Control Circuitry.
Output feedback Input. The APW7142 senses the feedback voltage via FB and
4 FB regulates the voltage at 0.8V. Connecting FB with a resistor-divider from the converter’s
output sets the output voltage from 0.8V to VIN.
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Output of the error amplifier. Connect a series RC network from the COMP to the GND to
5 COMP compensate the regulation control loop. In some cases, an additional capacitor from the
COMP to the GND is required.
Enable Input. EN is a digital input that turns the regulator on or off. Drive EN high to turn
6 EN
on the regulator, drive it low to turn it off. Connect this pin to the VIN if it is not used.
Power Switching Output. LX is the junction of the high-side and low-side power
7, 8
Block Diagram
LX
IC
MOSFETs to supply power to the output LC filter.
VIN
T-
Current Sense
Amplifier VIN
Power-On- Current
Reset Limit
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Zero-Crossing
POR Comparator
UG
OVP
123%VREF Soft-Start /
Soft-Stop Gate
and Driver
50%VREF UVP Fault Logic
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Soft-Start /
Soft-Stop Inhibit
Gate LX
FB Control VIN
Gm
VREF Error LG
Amplifier Current Gate
Compartor Driver
CH
COMP PGND
Slope
Compensation
Oscillator AGND
EN Enable Over
500kHz
1.5V Temperature FB
Protection
VIN
2 C1
VIN
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L1
Enable
6 8 VOUT
EN LX
Shutdown U1 LX 7
APW7142
PGND 1 C2
5 COMP R1
±
1%
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R3 4
FB
±5%
C3 AGND R2
±
30% 3 ±1% C4
±30%, Optional
VIN(V)
12
12
12
VOUT(V)
3.3
5
5
L1(µH)
6.8
6.8
4.7
C2(µF)
22
44
22
IC
a. Cost-effective Feedback Compensation (C4 is not connected)
C2 ESR(mΩ)
5
3
5
R1(kΩ)
63.0
63.0
46.9
R2(kΩ)
12
12
15
R3(kΩ)
10.0
20.0
10.0
C3(pF)
1500
1500
1500
T-
12 3.3 4.7 44 3 46.9 15 22.0 1500
VIN
C1 C5 12V
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2
2.2µF 470µF
VIN
L1
Enable 4.7µH /3A VOUT
6 8 3.3V/3A
EN LX
Shutdown U1 LX 7
APW7142 C2
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PGND 1 470µF
R1
5 COMP (ESR=30mΩ)
46.9K
R3 ±1%
FB 4
62K
±5%
R2
AGND
C3 15K
3
680pF
±30%
IC ±1% C4
47pF
±30%
T-
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Function Description
VIN Power-On-Reset (POR)
The APW7142 keeps monitoring the voltage on VIN pin to The under-voltage threshold is 50% of the nominal out-
prevent wrong logic operations which may occur when put voltage. The under-voltage comparator has a built-in
VIN voltage is not high enough for the internal control 2µs noise filter to prevent the chips from wrong UVP shut-
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circuitry to operate. The VIN POR has a rising threshold of down being caused by noise. The under-voltage protec-
4.1V (typical) with 0.5V of hysteresis. tion works in a hiccup mode without latched shutdown.
During startup, the VIN voltage must exceed the enable The IC will initiate a new soft-start process at the end of
voltage threshold. Then, the IC starts a start-up process the preceding delay.
and ramps up the output voltage to the voltage target.
Over-Voltage Protection (OVP)
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Digital Soft-Start The over-voltage function monitors the output voltage by
The APW7142 has a built-in digital soft-start to control the FB pin. When the FB voltage increases over 123% of the
rise rate of the output voltage and limit the input current reference voltage due to the high-side MOSFET failure or
surge during start-up. During soft-start, an internal volt- for other reasons, the over-voltage protection comparator
IC
age ramp (VRAMP), connected to one of the positive inputs
of the error amplifier, rises up from 0V to 0.95V to replace
the reference voltage (0.8V) until the voltage ramp reaches
the reference voltage.
During soft-start without output over-voltage, the APW7142
will force the low-side MOSFET gate driver high. This ac-
tion actively pulls down the output voltage and eventually
attempts to blow the internal bonding wires. As soon as
the output voltage is within regulation, the OVP compara-
tor is disengaged. The chip will restore its normal
T-
converter’s sinking capability is disabled until the output operation. This OVP scheme only clamps the voltage
voltage reaches the voltage target. overshoot, and does not invert the output voltage when
otherwise activated with a continuously high output from
Digital Soft-Stop
low-side MOSFET driver - a common problem for OVP
At the moment of shutdown controlled by EN signal, un- schemes with a latch.
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down rises from 0.95V to 0V to replace the reference power MOSFETs, allowing the devices to cool. The ther-
voltage. Therefore, the output voltage falls down slowly at mal sensor allows the converters to start a start-up pro-
the light load. After the soft-stop interval elapses, the soft- cess and to regulate the output voltage again after the
stop process ends and the the IC turns on the low-side junction temperature cools by 40oC. The OTP is designed
power MOSFET. with a 40 oC hysteresis to lower the average TJ during
CH
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aging during overload or short-circuit conditions.
Frequency Foldback
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quency allows the inductor current to safely discharge,
thereby preventing current runaway. The oscillator’s fre-
quency will gradually increase to its designed rate when
the feedback voltage on the FB again approaches 0.8V.
IC
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Application Information
Setting Output Voltage T=1/FOSC
R1 VLX
VOUT = 0.8 × (1 + ) (V) DT I
R2
IOUT
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Suggested R2 is in the range from 1k to 20kΩ. For por-
IL
table applications, a 10k resistor is suggested for R2. To
prevent stray pickup, please locate resistors R1 and R2 IOUT
close to APW7142. IQ1
Input Capacitor Selection I
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ICOUT
Use small ceramic capacitors for high frequency
VOUT
decoupling and bulk capacitors to supply the surge cur-
rent needed each time the P-channel power MOSFET (Q1)
turns on. Place the small ceramic capacitors physically VOUT
close to the VIN and between the VIN and the GND.
The important parameters for the bulk input capacitor are
the voltage rating and the RMS current rating. For reliable
operation, select the bulk capacitor with voltage and cur-
rent ratings above the maximum input voltage and larg-
IC Figure 1 Converter Waveforms
lum capacitors can be used, but caution must be exer- VESR = ∆I. ⋅ ESR ........... (3)
cised with regard to the capacitor surge current rating.
The peak-to-peak voltage of the ideal output capacitor is
VIN calculated as the following equations:
VIN
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IQ1 CIN ∆I
∆VCOUT = (V) ........... (4)
8 ⋅ FOSC ⋅ COUT
Q1
IL IOUT For the applications using bulk capacitors, the ∆VCOUT is
VOUT much smaller than the VESR and can be ignored. Therefore,
LX L
ESR the AC peak-to-peak output voltage (∆VOUT ) is shown as
Q2 ICOUT
below:
COUT
∆VOUT = ∆ I ⋅ ESR (V) ........... (5)
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portant to ensure proper operation of the regulator. In
The load transient requirements are the function of the general, interconnecting impedance should be minimized
slew rate (di/dt) and the magnitude of the transient load by using short and wide printed circuit traces. Signal and
current. These requirements are generally met with a mix power grounds are to be kept separating and finally com-
of capacitors and careful layout. High frequency capaci- bined using the ground plane construction or single point
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tors initially supply the transient and slow the current load grounding. Figure 2 illustrates the layout, with bold lines
rate seen by the bulk capacitors. The bulk filter capacitor indicating high current paths. Components along the bold
values are generally determined by the ESR (Effective lines should be placed close together. The following is a
Series Resistance) and voltage rating requirements rather checklist for your layout:
than actual capacitance requirements. 1. Firstly, to initial the layout by placing the power
High frequency decoupling capacitors should be placed
as close to the power pins of the load as physically
IC
possible. Be careful not to add inductance in the circuit
board wiring that could cancel the usefulness of these
low inductance components. An aluminum electrolytic
components. Orient the power circuitry to achieve a
clean power flow path. If possible, make all the con-
nections on one side of the PCB with wide and copper
filled areas.
T-
+
capacitor’s ESR value is related to the case size with lower VIN
2
ESR available in larger case sizes. However, the Equiva- -
VIN C1 L1
lent Series Inductance (ESL) of these capacitors increases
8
LX
with case size and can reduce the usefulness of the ca- 6 LX 7 +
EN
pacitor to the high slew-rate transient loading.
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U1 C2 Load
VOUT
Compensation APW7142
Inductor Value Calculation Network
-
1
5 COMP PGND
The operating frequency and inductor selection are inter-
4 R1
related in that higher operating frequencies permit the R3 FB
C3 Divider
ripple current. However, this is at the expense of efficiency C4
3
(Optional)
due to an increase in MOSFET gate charge losses. The
equation (2) shows that the inductance value has a direct
effect on ripple current. 2. In Figure 2, the loops with the same color bold lines
Accepting larger values of ripple current allows the use of conduct high slew rate current. These interconnect-
CH
low inductances, but results in higher output voltage ripple ing impedances should be minimized by using wide
and greater core losses. A reasonable starting point for and short printed circuit traces.
setting ripple current is ∆I ≤ 0.4x IOUT(MAX) . Remember, the 3. Keep the sensitive small signal nodes (FB, COMP)
maximum ripple current occurs at the maximum input away from switching nodes (LX or others) on the PCB.
voltage. The minimum inductance of the inductor is cal- Therefore place the feedback divider and the feedback
culated by using the following equation: compensation network close to the IC to avoid switch-
VOUT ·(VIN - VOUT) ing noise. Connect the ground of feedback divider di-
≤ 1.2 rectly to the AGND pin of the IC using a dedicated
500000 ·L ·VIN
ground trace.
VOUT ·(VIN - VOUT )
L≥ (H) ........... (6)
600000 ·VIN
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high slew rate current.
C2
C1
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L1 VOUT
VIN 1 8 V
LX
SOP-8
2 7
3 6
Ground 4 5
APW7142
Ground
Package Information
SOP-8
D
SEE VIEW A
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E1
E °
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h X 45
e b c
IC
A2
0.25
A
GAUGE PLANE
SEATING PLANE
A1
T-
L
VIEW A
S SOP-8
Y
M MILLIMETERS INCHES
B
O
L MIN. MAX. MIN. MAX.
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A 1.75 0.069
A1 0.10 0.25 0.004 0.010
A2 1.25 0.049
b 0.31 0.51 0.012 0.020
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OD0 P0 P2 P1 A
E1
F
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W
B0
K0 A0
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OD1 B A
B
SECTION A-A
T
SECTION B-B
IC d
H
A
T-
T1
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Application A H T1 C d D W E1 F
12.4+2.00 13.0+0.50
330.0±2.00 50 MIN. 1.5 MIN. 20.2 MIN. 12.0±0.30 1.75±0.10 5.5±0.05
-0.00 -0.20
IP
SOP-8 P0 P1 P2 D0 D1 T A0 B0 K0
1.5+0.10 0.6+0.00
4.0±0.10 8.0±0.10 2.0±0.05 1.5 MIN. 6.40±0.20 5.20±0.20 2.10±0.20
-0.00 -0.40
(mm)
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Classification Profile IC
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Average ramp-up rate
3 °C/second max. 3 °C/second max.
(Tsmax to TP)
Liquidous temperature (TL) 183 °C 217 °C
Time at liquidous (tL) 60-150 seconds 60-150 seconds
Peak package body Temperature
See Classification Temp in table 1 See Classification Temp in table 2
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(Tp)*
Time (tP)** within 5°C of the specified
20** seconds 30** seconds
classification temperature (Tc)
Average ramp-down rate (Tp to Tsmax) 6 °C/second max. 6 °C/second max.
Package
IC
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum.
** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum.
Table 1. SnPb Eutectic Process – Classification Temperatures (Tc)
Volume mm
3
Volume mm
3
≥350
T-
Thickness <350
<2.5 mm 235 °C 220 °C
≥2.5 mm 220 °C 220 °C
Table 2. Pb-free Process – Classification Temperatures (Tc)
3 3 3
Package Volume mm Volume mm Volume mm
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Customer Service
OM
Fax : 886-3-5642050
Taipei Branch :
2F, No. 11, Lane 218, Sec 2 Jhongsing Rd.,
Sindian City, Taipei County 23146, Taiwan
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Tel : 886-2-2910-3838
Fax : 886-2-2917-3838
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