INTEGRATED CIRCUITS

DATA SHEET

74AHC1G32; 74AHCT1G32
2-input OR gate
Product specification 2002 Jun 05
Supersedes data of 2002 Mar 26
Philips Semiconductors Product specification

2-input OR gate 74AHC1G32; 74AHCT1G32

FEATURES DESCRIPTION
• Symmetrical output impedance The 74AHC1G/AHCT1G32 is a high-speed Si-gate CMOS
• High noise immunity device.
• ESD protection: The 74AHC1G/AHCT1G32 provides the 2-input
OR function.
– HBM EIA/JESD22-A114-A exceeds 2000 V
– MM EIA/JESD22-A115-A exceeds 200 V
– CDM EIA/JESD22-C101 exceeds 1000 V.
• Low power dissipation
• Balanced propagation delays
• Multiple very small 5-pin packages
• Output capability: standard
• Specified from −40 to +125 °C.

QUICK REFERENCE DATA

GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns.

TYPICAL
SYMBOL PARAMETER CONDITIONS UNIT
AHC1G AHCT1G
tPHL/tPLH propagation delay A and B to Y CL = 15 pF; VCC = 5 V 3.2 3.3 ns
CI input capacitance 1.5 1.5 pF
CPD power dissipation capacitance CL = 50 pF; f = 1 MHz; 16 17 pF
notes 1 and 2

Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. VI = GND to VCC.

2002 Jun 05 2
Philips Semiconductors Product specification

2-input OR gate 74AHC1G32; 74AHCT1G32

FUNCTION TABLE
See note 1.
INPUTS OUTPUT
A B Y
L L L
L H H
H L H
H H H

Note
1. H = HIGH voltage level;
L = LOW voltage level.

ORDERING INFORMATION

TEMPERATURE PACKAGE
TYPE NUMBER
RANGE PINS PACKAGE MATERIAL CODE MARKING
74AHC1G32GW −40 to +125 °C 5 SC-88A plastic SOT353 AG
74AHCT1G32GW −40 to +125 °C 5 SC-88A plastic SOT353 CG
74AHC1G32GV −40 to +125 °C 5 SC-74A plastic SOT753 A32
74AHCT1G32GV −40 to +125 °C 5 SC-74A plastic SOT753 C32

PINNING

PIN SYMBOL DESCRIPTION

1 B data input B
2 A data input A
3 GND ground (0 V)
4 Y data output Y
5 VCC supply voltage

handbook, halfpage
B 1 5 VCC
handbook, halfpage 1 B
A 2 32 Y 4
2 A
GND 3 4 Y
MNA164
MNA163

Fig.1 Pin configuration. Fig.2 Logic symbol.

2002 Jun 05 3
Philips Semiconductors Product specification

2-input OR gate 74AHC1G32; 74AHCT1G32

handbook, halfpage
1 B
handbook, halfpage ≥1 4
2 Y

MNA165
A
MNA166

Fig.3 IEC logic symbol. Fig.4 Logic diagram.

RECOMMENDED OPERATING CONDITIONS

74AHC1G 74AHCT1G
SYMBOL PARAMETER CONDITIONS UNIT
MIN. TYP. MAX. MIN. TYP. MAX.
VCC supply voltage 2.0 5.0 5.5 4.5 5.0 5.5 V
VI input voltage 0 − 5.5 0 − 5.5 V
VO output voltage 0 − VCC 0 − VCC V
Tamb operating ambient see DC and AC −40 +25 +125 −40 +25 +125 °C
temperature characteristics per device
tr, tf input rise and fall VCC = 3.3 ±0.3 V − − 100 − − − ns/V
times VCC = 5 ±0.5 V − − 20 − − 20 ns/V

LIMITING VALUES
In accordance with the Absolute Maximum Rating System (IEC 60134); voltages are referenced to GND (ground = 0 V).
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VCC supply voltage −0.5 +7.0 V
VI input voltage −0.5 +7.0 V
IIK input diode current VI < −0.5 V − −20 mA
IOK output diode current VO < −0.5 V or VO > VCC + 0.5 V; note 1 − ±20 mA
IO output source or sink current −0.5 V < VO < VCC + 0.5 V − ±25 mA
ICC VCC or GND current − ±75 mA
Tstg storage temperature −65 +150 °C
PD power dissipation per package for temperature range from −40 to +125 °C − 250 mW

Note
1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.

2002 Jun 05 4
Philips Semiconductors Product specification

2-input OR gate 74AHC1G32; 74AHCT1G32

DC CHARACTERISTICS
Family 74AHC1G
Over recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS Tamb (°C)
SYMBOL PARAMETER VCC 25 −40 to +85 −40 to +125 UNIT
OTHER
(V) MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VIH HIGH-level input 2.0 1.5 − − 1.5 − 1.5 − V
voltage 3.0 2.1 − − 2.1 − 2.1 − V
5.5 3.85 − − 3.85 − 3.85 − V
VIL LOW-level input 2.0 − − 0.5 − 0.5 − 0.5 V
voltage 3.0 − − 0.9 − 0.9 − 0.9 V
5.5 − − 1.65 − 1.65 − 1.65 V
VOH HIGH-level output VI = VIH or VIL; 2.0 1.9 2.0 − 1.9 − 1.9 − V
voltage IO = −50 µA
VI = VIH or VIL; 3.0 2.9 3.0 − 2.9 − 2.9 − V
IO = −50 µA
VI = VIH or VIL; 4.5 4.4 4.5 − 4.4 − 4.4 − V
IO = −50 µA
VI = VIH or VIL; 3.0 2.58 − − 2.48 − 2.40 − V
IO = −4.0 mA
VI = VIH or VIL; 4.5 3.94 − − 3.8 − 3.70 − V
IO = −8.0 mA
VOL LOW-level output VI = VIH or VIL; 2.0 − 0 0.1 − 0.1 − 0.1 V
voltage IO = 50 µA
VI = VIH or VIL; 3.0 − 0 0.1 − 0.1 − 0.1 V
IO = 50 µA
VI = VIH or VIL; 4.5 − 0 0.1 − 0.1 − 0.1 V
IO = 50 µA
VI = VIH or VIL; 3.0 − − 0.36 − 0.44 − 0.55 V
IO = 4.0 mA
VI = VIH or VIL; 4.5 − − 0.36 − 0.44 − 0.55 V
IO = 8.0 mA
ILI input leakage VI = VCC or GND 5.5 − − 0.1 − 1.0 − 2.0 µA
current
ICC quiescent supply VI = VCC or GND; 5.5 − − 1.0 − 10 − 40 µA
current IO = 0
CI input capacitance − 1.5 10 − 10 − 10 pF

2002 Jun 05 5
Philips Semiconductors Product specification

2-input OR gate 74AHC1G32; 74AHCT1G32

Family 74AHCT1G
Over recommended operating conditions; voltages are referenced to GND (ground = 0 V).
TEST CONDITIONS Tamb (°C)
SYMBOL PARAMETER 25 −40 to +85 −40 to +125 UNIT
OTHER VCC (V)
MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VIH HIGH-level input 4.5 to 5.5 2.0 − − 2.0 − 2.0 − V
voltage
VIL LOW-level input 4.5 to 5.5 − − 0.8 − 0.8 − 0.8 V
voltage
VOH HIGH-level output VI = VIH or VIL; 4.5 4.4 4.5 − 4.4 − 4.4 − V
voltage IO = −50 µA
VI = VIH or VIL; 4.5 3.94 − − 3.8 − 3.70 − V
IO = −8.0 mA
VOL LOW-level output VI = VIH or VIL; 4.5 − 0 0.1 − 0.1 − 0.1 V
voltage IO = 50 µA
VI = VIH or VIL; 4.5 − − 0.36 − 0.44 − 0.55 V
IO = 8.0 mA
ILI input leakage VI = VIH or VIL 5.5 − − 0.1 − 1.0 − 2.0 µA
current
ICC quiescent supply VI = VCC or GND; 5.5 − − 1.0 − 10 − 40 µA
current IO = 0
∆ICC additional VI = 3.4 V; 5.5 − − 1.35 − 1.5 − 1.5 mA
quiescent supply other inputs at
current per input VCC or GND;
pin IO = 0
CI input capacitance − 1.5 10 − 10 − 10 pF

2002 Jun 05 6
Philips Semiconductors Product specification

2-input OR gate 74AHC1G32; 74AHCT1G32

AC CHARACTERISTICS
Type 74AHC1G32
GND = 0 V; tr = tf ≤ 3.0 ns.

TEST CONDITIONS Tamb (°C)

SYMBOL PARAMETER CL 25 −40 to +85 −40 to +125 UNIT
WAVEFORMS
(pF) MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VCC = 3.0 to 3.6 V; note 1
tPHL/tPLH propagation delay see Figs 5 and 6 15 − 4.4 7.9 1.0 9.5 1.0 10.0 ns
A and B to Y 50 − 6.3 11.4 1.0 13.0 1.0 14.5 ns
VCC = 4.5 to 5.5 V; note 2
tPHL/tPLH propagation delay see Figs 5 and 6 15 − 3.2 5.5 1.0 6.5 1.0 7.0 ns
A and B to Y 50 − 4.6 7.5 1.0 8.5 1.0 9.5 ns

Notes
1. All typical values are measured at VCC = 3.3 V.
2. All typical values are measured at VCC = 5.0 V.

Type 74AHCT1G32
GND = 0 V; tr = tf ≤ 3.0 ns.

TEST CONDITIONS Tamb (°C)

SYMBOL PARAMETER CL 25 −40 to +85 −40 to +125 UNIT
WAVEFORMS
(pF) MIN. TYP. MAX. MIN. MAX. MIN. MAX.
VCC = 4.5 to 5.5 V; note 1
tPHL/tPLH propagation delay see Figs 5 and 6 15 − 3.3 6.9 1.0 8.0 1.0 9.0 ns
A and B to Y 50 − 4.8 7.9 1.0 9.0 1.0 10 ns

Note
1. All typical values are measured at VCC = 5.0 V.

2002 Jun 05 7
Philips Semiconductors Product specification

2-input OR gate 74AHC1G32; 74AHCT1G32

AC WAVEFORMS

handbook, halfpage
A, B input VM

tPHL tPLH

Y output VM

MNA167

VI INPUT VM
FAMILY VM INPUT
REQUIREMENTS OUTPUT
AHC1G GND to VCC 50% VCC 50% VCC
AHCT1G GND to 3.0 V 1.5 V 50% VCC

Fig.5 The input (A and B) to output (Y) propagation delays.

handbook, halfpage VCC

VI VO
PULSE
D.U.T.
GENERATOR

RT CL

MNA101

Definitions for test circuit:

CL = Load capacitance including jig and probe capacitance. (See Chapter “AC characteristics” for values).
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.

Fig.6 Load circuitry for switching times.

2002 Jun 05 8
Philips Semiconductors Product specification

2-input OR gate 74AHC1G32; 74AHCT1G32

PACKAGE OUTLINES
Plastic surface mounted package; 5 leads SOT353

D B E A X

y HE v M A

5 4

A1
1 2 3 c

e1 bp w M B Lp

e
detail X

0 1 2 mm

scale

DIMENSIONS (mm are the original dimensions)

A1
UNIT A bp c D E (2) e e1 HE Lp Q v w y
max
1.1 0.30 0.25 2.2 1.35 2.2 0.45 0.25
mm 0.1 1.3 0.65 0.2 0.2 0.1
0.8 0.20 0.10 1.8 1.15 2.0 0.15 0.15

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC EIAJ PROJECTION

SOT353 SC-88A 97-02-28

2002 Jun 05 9
Philips Semiconductors Product specification

2-input OR gate 74AHC1G32; 74AHCT1G32

Plastic surface mounted package; 5 leads SOT753

D B E A
X

y HE v M A

5 4

A1
c

1 2 3 Lp

detail X
e bp w M B

0 1 2 mm

scale

DIMENSIONS (mm are the original dimensions)

UNIT A A1 bp c D E e HE Lp Q v w y

1.1 0.100 0.40 0.26 3.1 1.7 3.0 0.6 0.33

mm 0.95 0.2 0.2 0.1
0.9 0.013 0.25 0.10 2.7 1.3 2.5 0.2 0.23

OUTLINE REFERENCES EUROPEAN

ISSUE DATE
VERSION IEC JEDEC JEITA PROJECTION

SOT753 SC-74A 02-04-16

2002 Jun 05 10
Philips Semiconductors Product specification

2-input OR gate 74AHC1G32; 74AHCT1G32

SOLDERING If wave soldering is used the following conditions must be

observed for optimal results:
Introduction to soldering surface mount packages
• Use a double-wave soldering method comprising a
This text gives a very brief insight to a complex technology. turbulent wave with high upward pressure followed by a
A more in-depth account of soldering ICs can be found in smooth laminar wave.
our “Data Handbook IC26; Integrated Circuit Packages”
• For packages with leads on two sides and a pitch (e):
(document order number 9398 652 90011).
– larger than or equal to 1.27 mm, the footprint
There is no soldering method that is ideal for all surface longitudinal axis is preferred to be parallel to the
mount IC packages. Wave soldering can still be used for
transport direction of the printed-circuit board;
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is – smaller than 1.27 mm, the footprint longitudinal axis
recommended. must be parallel to the transport direction of the
printed-circuit board.
Reflow soldering The footprint must incorporate solder thieves at the
downstream end.
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied • For packages with leads on four sides, the footprint must
to the printed-circuit board by screen printing, stencilling or be placed at a 45° angle to the transport direction of the
pressure-syringe dispensing before package placement. printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor During placement and before soldering, the package must
type oven. Throughput times (preheating, soldering and be fixed with a droplet of adhesive. The adhesive can be
cooling) vary between 100 and 200 seconds depending applied by screen printing, pin transfer or syringe
on heating method. dispensing. The package can be soldered after the
adhesive is cured.
Typical reflow peak temperatures range from
215 to 250 °C. The top-surface temperature of the Typical dwell time is 4 seconds at 250 °C.
packages should preferable be kept below 220 °C for A mildly-activated flux will eliminate the need for removal
thick/large packages, and below 235 °C for small/thin of corrosive residues in most applications.
packages.
Manual soldering
Wave soldering Fix the component by first soldering two
Conventional single wave soldering is not recommended diagonally-opposite end leads. Use a low voltage (24 V or
for surface mount devices (SMDs) or printed-circuit boards less) soldering iron applied to the flat part of the lead.
with a high component density, as solder bridging and Contact time must be limited to 10 seconds at up to
non-wetting can present major problems. 300 °C.

To overcome these problems the double-wave soldering When using a dedicated tool, all other leads can be
method was specifically developed. soldered in one operation within 2 to 5 seconds between
270 and 320 °C.

2002 Jun 05 11
Philips Semiconductors Product specification

2-input OR gate 74AHC1G32; 74AHCT1G32

Suitability of surface mount IC packages for wave and reflow soldering methods

SOLDERING METHOD
PACKAGE(1)
WAVE REFLOW(2)
BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA not suitable suitable
HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, not suitable(3) suitable
HVSON, SMS
PLCC(4), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(4)(5) suitable
SSOP, TSSOP, VSO not recommended(6) suitable
Notes
1. For more detailed information on the BGA packages refer to the “(LF)BGA Application Note” (AN01026); order a copy
from your Philips Semiconductors sales office.
2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with respect to time) and body size of the package, there is a risk that internal or external package
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods”.
3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder
cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side,
the solder might be deposited on the heatsink surface.
4. If wave soldering is considered, then the package must be placed at a 45° angle to the solder wave direction.
The package footprint must incorporate solder thieves downstream and at the side corners.
5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not
suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.

2002 Jun 05 12
Philips Semiconductors Product specification

2-input OR gate 74AHC1G32; 74AHCT1G32

DATA SHEET STATUS

PRODUCT
DATA SHEET STATUS(1) DEFINITIONS
STATUS(2)
Objective data Development This data sheet contains data from the objective specification for product
development. Philips Semiconductors reserves the right to change the
specification in any manner without notice.
Preliminary data Qualification This data sheet contains data from the preliminary specification.
Supplementary data will be published at a later date. Philips
Semiconductors reserves the right to change the specification without
notice, in order to improve the design and supply the best possible
product.
Product data Production This data sheet contains data from the product specification. Philips
Semiconductors reserves the right to make changes at any time in order
to improve the design, manufacturing and supply. Changes will be
communicated according to the Customer Product/Process Change
Notification (CPCN) procedure SNW-SQ-650A.
Notes
1. Please consult the most recently issued data sheet before initiating or completing a design.
2. The product status of the device(s) described in this data sheet may have changed since this data sheet was
published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.

DEFINITIONS DISCLAIMERS
Short-form specification  The data in a short-form Life support applications  These products are not
specification is extracted from a full data sheet with the designed for use in life support appliances, devices, or
same type number and title. For detailed information see systems where malfunction of these products can
the relevant data sheet or data handbook. reasonably be expected to result in personal injury. Philips
Semiconductors customers using or selling these products
Limiting values definition  Limiting values given are in
for use in such applications do so at their own risk and
accordance with the Absolute Maximum Rating System
agree to fully indemnify Philips Semiconductors for any
(IEC 60134). Stress above one or more of the limiting
damages resulting from such application.
values may cause permanent damage to the device.
These are stress ratings only and operation of the device Right to make changes  Philips Semiconductors
at these or at any other conditions above those given in the reserves the right to make changes, without notice, in the
Characteristics sections of the specification is not implied. products, including circuits, standard cells, and/or
Exposure to limiting values for extended periods may software, described or contained herein in order to
affect device reliability. improve design and/or performance. Philips
Semiconductors assumes no responsibility or liability for
Application information  Applications that are
the use of any of these products, conveys no licence or title
described herein for any of these products are for
under any patent, copyright, or mask work right to these
illustrative purposes only. Philips Semiconductors make
products, and makes no representations or warranties that
no representation or warranty that such applications will be
these products are free from patent, copyright, or mask
suitable for the specified use without further testing or
work right infringement, unless otherwise specified.
modification.

2002 Jun 05 13
Philips Semiconductors Product specification

2-input OR gate 74AHC1G32; 74AHCT1G32

NOTES

2002 Jun 05 14
Philips Semiconductors Product specification

2-input OR gate 74AHC1G32; 74AHCT1G32

NOTES

2002 Jun 05 15
Philips Semiconductors – a worldwide company

Contact information

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© Koninklijke Philips Electronics N.V. 2002 SCA74

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Printed in The Netherlands 613508/05/pp16 Date of release: 2002 Jun 05 Document order number: 9397 750 09709