DXT Plug-In Unit Descriptions: DN0420278 Issue 1-3
DXT Plug-In Unit Descriptions: DN0420278 Issue 1-3
DXT Plug-In Unit Descriptions: DN0420278 Issue 1-3
SW128B
DN0420278
Issue 1-3
SW128B
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Table of Contents
This document has 36 pages
2 SW128B overview..........................................................................7
3 Capacity of SW128B...................................................................... 9
4 Structure of SW128B................................................................... 10
4.1 Mechanical structure.................................................................... 10
4.2 Logical structure...........................................................................10
4.2.1 Incoming serial buses...................................................................11
4.2.2 Outgoing serial buses...................................................................11
4.2.3 Branching interface.......................................................................11
4.2.4 Control bus interface.................................................................... 12
4.2.5 PCM IF FPGA.............................................................................. 12
4.2.6 Incoming data bus IF FPGA.........................................................15
4.2.7 SW1A ASIC 0 and SW1A ASIC 1................................................ 15
4.2.8 Configuration interface of the FPGAs.......................................... 16
4.2.9 Clocks.......................................................................................... 16
4.2.10 Power........................................................................................... 16
4.3 Interfaces of SW128B.................................................................. 16
4.4 Start-up and reset........................................................................ 20
5 Operation of SW128B.................................................................. 21
7 SW128B C108487....................................................................... 24
List of Figures
Figure 1 Operating environment of the SW128B in the GSW1KB (maximum
equipping).............................................................................................8
Figure 2 Block diagram of the SW128B............................................................ 11
Figure 3 The external interfaces of the SW128B..............................................17
Figure 4 A symmetrical current-controlled interface......................................... 18
Figure 5 The principle of the Control bus interface...........................................19
Figure 6 The front panel of the SW128B.......................................................... 21
Figure 7 Connectors, micro switch and settings of the SW128B......................24
List of Tables
Table 1 4M/8M mode selection....................................................................... 12
Table 2 Description of interface signals...........................................................17
Table 3 PCM mode settings on SW128B (S2)................................................ 24
Table 4 Switches and their function in micro switch package S3.................... 25
Table 5 Setting the ICC codes on SW128B (S3).............................................25
Table 6 PCM mode settings on SW128B (S2) in BSC3i................................. 26
Table 7 Pin descriptions.................................................................................. 29
Table 8 Connector J5 B(22) type female.........................................................30
Table 9 Connector J4 AB(25) type female...................................................... 31
Table 10 Connector J3 B(19) type female.........................................................32
Table 11 Connector J2 B(22) type female.........................................................33
Table 12 Connector J1 AB(25) type female...................................................... 35
1 Summary of changes
Changes between document issues are cumulative. Therefore, the latest document
issue contains all changes made to previous issues.
2 SW128B overview
Main functions of SW128B
The Switching network for 128 PCMs (SW128B plug-in unit) is the core of the Group
Switch (GSW1KB). The GSW1KB is a congestion-free, full-availability single-step
switching network based on time-space architecture. It consists of a maximum of eight
SW128B plug-in units with a combined capacity of 1024 PCM lines. A maximum-sized
GSW1KB switching network can be equipped in a single SW10C-A or SW10C cartridge.
The GSW1KB switches 8 kbit/s channels but supports also switching of channels that
consist of more broadband 8 kbits/s sequential channels.
The SW128B plug-in unit supports not only the current 4 Mbit/s serial bus connections
but also 8Mbit/s serial bus connections thus decreasing the number of PCM cables
needed in the network.
Operating environment
The operation of the GSW1KB is controlled by the switch processor unit SWCOP-A or
SWCOP-S. The SWCOP-A or SWCOP-S is connected to Host CPU unit using
CompactPCI or DMC bus. The maximum length of the control bus is 10 meters.
The SW128B receives the basic timing signals (16M, 8k) distributed by the SWCOP-A or
SWCOP-S, supervises them and initiates an alarm to the SWCOP-A or SWCOP-S in the
event of failure, and turns on the red LED indicator on the front panel.
The SWCOP-A or SWCOP-S can start the sending of the through-connection test to the
input direction channel for one SW128B at a time, and branch the output direction serial
bus to receive the data. For the comparison test, the SWCOP-A or SWCOP-S branches
the input and output direction serial bus from the SW128B.
The figure below presents the GSW1KB interfaces with the other functional blocks in a
DX 200 network element or exchange.
Incoming
databus
2
CLITG
32x8Mbit/s serial interface OR
SW128B 32x4Mbit/s,16x8MBit/s serial interfaces OR
64x4Mbit/sserialinterface
3
dn0498178
3 Capacity of SW128B
The SW128B has 64 serial bus interfaces with total capacity of 128 bidirectional 2.048
Mbit/s internal PCM lines, that is, twice the capacity of the SW64B.
The capacity of one internal 2M PCM line is 256 time-division multiplexed 8 kbit/s
channels, yielding a maximum capacity of 65536 channels for one SW128B.
Internal serial bus interfaces
The capacity of the internal serial bus interfaces can selected from the following
alternatives:
4 Structure of SW128B
INCOMING OUTGOING
4M/8MSERIAL BUSES 4M/8MSERIAL BUSES
64bit
0 SCBUS PCMRC PCMTC 0
64bit 4Mbit/s
SERIAL SERIAL
4Mbit/s 8Mbit/s
BUSES BUSES
8Mbit/s TxSERIAL BUSIF
INPUT OUTPUT
INTERFACE RxSERIAL BUSIF INTERFACE
63 63
PCMIF
FPGA
DIN1DIN0 DA AD DOUT
8bit/32MHz
Configuration
IFofthe 15bit/32MHz
FPGAs
18bit/32MHz
64bit/32MHz
DN0498181
• Incoming data path block (4M serial bus interface, 8M serial bus interface,
Multiplexer, test data generator, PCMRC IF)
• Outgoing data path block (4M serial bus interface, 8M serial bus interface,
Multiplexer)
• Control bus interface block.
Incoming data path block: 4M serial bus interface
Up to 64 incoming 4M serial buses (R0...R63) can be connected to the SW128B plug-in
unit. The 4M internal serial interface is a 4.096 Mbit/s serial bus with two 2.048 Mbit/s
PCM circuits multiplexed together by bit-interleaving.
The Rx 4Mbit/s IF block multiplexes the data of its incoming 4M serial buses into eight
32.768 Mbit/s signals with eight 4M serial buses multiplexed into one 32.768 Mbit/s
signal by byte interleaving.
Incoming data path block: 8M serial bus interface
Up to 32 incoming 8M serial buses (R0...R15, R32…R63) can be connected to the
SW128B plug-in unit. The 8M internal serial bus interface is an 8.192 Mbit/s serial bus
with four 2.048 Mbit/s PCM circuits multiplexed together by byte-interleaving.
The Rx 8Mbit/s IF block multiplexes the data of its incoming 8M serial buses into eight
32.768 Mbit/s signals with four 8M serial buses multiplexed into one 32.768 Mbit/s signal
by byte interleaving.
Incoming data path block: Multiplexer
The Multiplexer block connects data from incoming serial buses to the data out port.
Connections are made according the tables below.
4M 4M R0...R64 → PCM0...PCM127
4M 8M R0...R16 → PCM0...PCM63;
R32...R63 → PCM64...PCM127
8M 4M R0...R31 → PCM0...PCM63;
R32...R47 → PCM64...PCM127
8M 8M R0...R16 → PCM0...PCM63;
R32...R47 → PCM64...PCM127
TheTx 4Mbit/s IF block demultiplexes data of its incoming eight 32M serial buses into 64
internal 4M serial buses.
Outgoing data path block: 8M serial bus interface
Up to 32 outgoing 8M serial buses (T0...T15, T32…T63) can be connected to the
SW128B plug-in unit. The internal 8M serial buses interface is an 8.192 Mbit/s serial bus
with four 2.048 Mbit/s PCM circuits multiplexed together by byte-interleaving.
The Tx 8Mbit/s IF block demultiplexes data of its incoming eight 32M serial buses into 32
internal 8M serial buses.
Outgoing data path block: Multiplexer
Incoming data bits from SW1A ASICs are selected according the content of the
Multiplexer control memory. The logic of the Control Bus Interface block updates the
content of the Multiplexer control memory when a connection is established. The size of
the required dual-port memory is 4096 times 8 bits.
Outgoing data path block: PCMTC IF
The branching logic is used in comparison and connection tests. The branching logic
allows for branching one outgoing 2Mbit/s PCM line data to the branching interface. The
branching logic works in the following way: the data of one 2Mbit/s PCM line is written in
the dualport memory one frame at a time, and the data is branched from the memory
only after the entire frame has been written in it. Therefore, enough memory for two
frames is needed; one memory block is used to read the data of the previous frame while
the second memory block is used to write data to the next frame. The size of the
required dual-port memory is 2 x 32 x 8 bits.
For the comparison and connection tests, the SWCOP-A or SWCOP-S branches one
outgoing internal 2Mbit/s PCM line to the SWCOP-A or SWCOP-S. The branching is
done by an I/O operation of the SWCOP-A or SWCOP-S: the output PCM line is chosen
by one operation. Seven bits are used to indicate the internal 2Mbit/s PCM line and after
that the branching is activated by write operation into the Test Data Control register.
When the test is completed, the branching must be released with a separate I/O
operation.
Branching interface is divided into blocks of 512 internal 2 Mbit/s PCM lines, and only
one outgoing internal 2Mbit/s PCM line can be branched at a time in that block.
Control bus interface block
The control logic block handles address decoding and starts the task required by each
operation. The control logic also handles parity check of incoming data.
The control bus interface is a symmetrical voltage-controlled bi-directional parallel bus
interface. It includes the multiplexed address and data bus (CAD0...CAD7), the parity bit
(CPAR), the address latch enable signal (CALE), the write signal (_CWR) and the read
signal (_CRD).
The SWCOP-A or SWCOP-S reads from and writes into the control memory and
registers of the SW128B plug-in unit via the parallel control bus. The SW128B registers
are located in the I/O space of the SWCOP-A or SWCOP-S.
When writing into the control memory, the SWCOP-A or SWCOP-S first writes the output
data of the connection into the address registers, in two parts, and then the input data of
the connection into the data registers, in three parts. The logic of the SW128B updates
the control memory location in question after the last operation. The width of the
connected channel is defined in the N x 8kbit/s Channel register.
When the connection has been established, the SWCOP-A or SWCOP-S can check the
contents of the control memory at any time. This check reading is conducted by first
writing the address of the memory location to be checked into the SW128B registers,
and then by reading the contents of the memory location from the SW128B registers.
The write operations performed by the SWCOP-A or SWCOP-S on the control bus are
supervised with a parity check. If the SW128B detects a parity error in the data, the
writing into the control memory or registers is disabled. If a parity error occurs in the
address, the decoding of the write/read operation in the control memory or registers is
completely disabled. The parity error alarm can be read from the status register. The
alarm is cancelled after a successful status register read operation.
The SWCOP-A or SWCOP-S can test parity alarm logic with an I/O operation by which
the parity is set "wrong", causing a parity alarm from all control bus operations.
4.2.9 Clocks
The SW128B plug-in unit receives the basic timing signals (16M and 8K) from the
SWCOP-A or SWCOP-S. The interface is a symmetrical current-controlled interface.
The SW128B unit also needs the clock signals 32,768 MHz, 65,536 MHz and 98,064
MHz, which are generated by using phase-locked loops. 32,768 MHz is generated from
incoming basic timing signal 16,384 MHz with MC88915 PLL and distributed to the unit
with MPC940L clock distribution buffer. 65,536 MHz and 98,064 MHz signals are
generated and distributed from 32,768 MHz with MPC972 PLL.
The SW128B supervises the basic timing signals by counting the number of pulses in the
32M signal during one cycle of the 8K signal. An alarm is activated, if the number of
pulses is incorrect or if one synchronisation signal is missing.
4.2.10 Power
Incoming voltage of -48V is drawn through backplane connectors. The following
operating voltages needed by the SW128B are converted in the power block:
Signal Description
Signal Description
Timing interface
The SWCOP-S or SWCOP-A unit distributes the 16.384 MHz and 8 kHz clock signals to
the SW128B units. The timing interface is a symmetrical current-controlled interface (see
the figure below) and it is connected to the back connector of the plug-in unit.
R R R R
IN A B OUT
DN0174087
The control bus interface does not have termination resistors on SW128B, because the
termination resistors are in the cartridge at end of the control bus.
The MAX9201E type comparator is used in the control bus interface as a line receiver.
The 26LV31 type differential line driver is used in the control bus interface as a line
transmitter. There are 390 Ohm serial resistors in the differential outputs of the control
bus line-transmitter.
The principle of the Control bus interface is presented in the figure below.
A
CALE,CWR,CRD CALE,CWR,CRD
B
RD_EN
390ohm
EN
CAD7...0_OUT,CPAR_OUT
390ohm
A
CAD7...0,CPAR
CAD7...0_IN,CPAR_IN B
DN0498209
4 and 8Mbit/s serial bus interface
64 internal serial buses are connected to the back plane.
The MAX9201E type comparator is used in the serial bus interface as a line receiver.
There is a 2.2 kOhm pull-up in the A-line of the differential input of serial line-receiver,
and there are 68 Ohm pull-down termination resistors in the differential inputs of serial
line-receiver.
The 26LV31 type differential line driver is used in the serial bus interface as a line
transmitter. There are 390 Ohm serial resistors in the differential outputs of the serial
line-transmitter.
Unit address UA bits
Unit Address (UA) bits are used to indicate the slot number to the SW128B plug-in units.
The UA bits are hardwired in the cartridge.
Branching interface
The branching interfaces (PCMRC, PCMTC) are symmetrical voltage-controlled 2Mbit/s
interfaces.
The 26LV31 type differential line driver is used in the serial bus interface as a line
transmitter.
The branching interface does not have termination resistors on the SW128B, because
the termination resistors are in the cartridge at end of the bus.
Alarm interface
The power alarm signal (PWAL) is an open-collector type signal. It is activated, if the
supply voltages drop below specified level. It is possible to test power alarm interface by
activating the _PWTST signal.
Clock alarm signal (CCLAL) is an open-collector type signal. It is activated, if a clock
error or parity error is detected. It is possible to test power alarm interface by writing into
the Status register.
JTAG test interface
There is one TAP chain on the SW128B. The JTAG interface is buffered in the SW128B
unit, and signal lines are terminated both before and after buffering. There are AC
terminations in the connector side of the buffers and AC or series terminations in the unit
side. The termination in the unit side is important for TMS and TCK signals. TDI/TDO
signals are buffered by the chain and do not need termination. The TMS and TCK
signals go through every pin without branches. There is a 10 kOhm pull-up in each TDI-
input.
The TAP goes to FPGAs and SW1A ASICs. The JTAG interface is connected to the
PWB with 2 x 4 and 2 x 6 pin headers.
5 Operation of SW128B
The front panel of the SW128B is a M98 mechanics compatible front panel. There are
two LED indicators in the front panel; see the figure below.
OPR
DN0498212
LED indicators
The front panel of the SW128B plug-in unit contains two LED indicators, a green one and
a red one. The green LED is controlled by software green and it indicates the active
matrix half; the red LED indicates an alarm which is activated, if the alarm (CCLAL)
signal of the SW128B is active.
Backplane connectors
The SW128B is connected to backplane with five 5-row EMC shielded female Hard
Metric connectors, that is, with pressfit connectors J5, J4, J3, J2 and J1:
Connectors J1 and J2 are used to interface unit to the incoming data bus; connector J2
is used to interface unit to the control bus, and connectors J3, J4 and J5 are used to
interface internal serial buses to other units. The -48V operating voltage is connected
through connector J4.
For the connector maps, see Connector maps of SW128B.
+1.8V 1A 1.8W
7 SW128B C108487
Figure 7 Connectors, micro switch and settings of the SW128B
J5
J4
S1 S2 S3
J3
8 7 6 5
ON
J2
OFF
1 2 3 4
J1
DN0498224
The SW128B has three micro switch packages containing four switches each. The
switches are used for setting PCM mode and Interchangeability code.
PCM mode settings (S2)
The PCM mode set up is made with micro switches as follows:
3-6 Reserved
4-5 Reserved
The first interchangeability code A corresponds to all switches OFF. After that, the
settings start to roll for each interchangeability code change as shown in the table below.
D ON ON OFF OFF
F ON OFF ON OFF
G OFF ON ON OFF
H ON ON ON OFF
K ON OFF OFF ON
L OFF ON OFF ON
M ON ON OFF ON
N OFF OFF ON ON
P ON OFF ON ON
R OFF ON ON ON
Pin Decription
Pin Decription
Connector J5
Table 8 Connector J5 B(22) type female.
Pin F E D C B A
1 GND T 00 B T 00 A GND R 00 B R 00 A
2 GND T 01 B T 01 A GND R 01 B R 01 A
3 GND T 02 B T 02 A GND R 02 B R 02 A
4 GND T 03 B T 03 A GND R 03 B R 03 A
5 GND T 04 B T 04 A GND R 04 B R 04 A
6 GND T 05 B T 05 A GND R 05 B R 05 A
7 GND T 06 B T 06 A GND R 06 B R 06 A
8 GND T 07 B T 07 A GND R 07 B R 07 A
9 GND T 08 B T 08 A GND R 08 B R 08 A
10 GND T 09 B T 09 A GND R 09 B R 09 A
11 GND T 10 B T 10 A GND R 10 B R 10 A
12 GND T 11 B T 11 A GND R 11 B R 11 A
13 GND T 12 B T 12 A GND R 12 B R 12 A
Pin F E D C B A
14 GND T 13 B T 13 A GND R 13 B R 13 A
15 GND T 14 B T 14 A GND R 14 B R 14 A
16 GND T 15 B T 15 A GND R 15 B R 15 A
17 GND T 16 B T 16 A GND R 16 B R 16 A
18 GND T 17 B T 17 A GND R 17 B R 17 A
19 GND T 18 B T 18 A GND R 18 B R 18 A
20 GND T 19 B T 19 A GND R 19 B R 19 A
21 GND T 20 B T 20 A GND R 20 B R 20 A
22 GND T 21 B T 21 A GND R 21 B R 21 A
Pin F E D C B A
1 GND T 22 B T 22 A GND R 22 B R 22 A
2 GND T 23 B T 23 A GND R 23 B R 23 A
3 GND T 24 B T 24 A GND R 24 B R 24 A
4 GND T 25 B T 25 A GND R 25 B R 25 A
5 GND T 26 B T 26 A GND R 26 B R 26 A
6 GND T 27 B T 27 A GND R 27 B R 27 A
7 GND T 28 B T 28 A GND R 28 B R 28 A
8 GND T 29 B T 29 A GND R 29 B R 29 A
9 GND T 30 B T 30 A GND R 30 B R 30 A
10 GND T 31 B T 31 A GND R 31 B R 31 A
Pin F E D C B A
11 GND
14
15 GND T 32 B T 32 A GND R 32 B R 32 A
16 GND T 33 B T 33 A GND R 33 B R 33 A
17 GND T 34 B T 34 A GND R 34 B R 34 A
18 GND T 35 B T 35 A GND R 35 B R 35 A
19 GND T 36 B T 36 A GND R 36 B R 36 A
20 GND T 37 B T 37 A GND R 37 B R 37 A
21 GND T 38 B T 38 A GND R 38 B R 38 A
22 GND T 39 B T 39 A GND R 39 B R 39 A
23 GND T 40 B T 40 A GND R 40 B R 40 A
24 GND T 41 B T 41 A GND R 41 B R 41 A
25 GND T 42 B T 42 A GND R 42 B R 42 A
Pin F E D C B A
1 GND T 43 B T 43 A GND R 43 B R 43 A
2 GND T 44 B T 44 A GND R 44 A R 44 A
3 GND T 45 B T 45 A GND R 45 A R 45 A
4 GND T 46 B T 46 A GND R 46 B R 46 A
Pin F E D C B A
5 GND T 47 B T 47 A GND R 47 B R 47 A
6 GND T 48 B T 48 A GND R 48 B R 48 A
7 GND T 49 B T 49 A GND R 49 B R 49 A
8 GND T 50 B T 50 A GND R 50 B R 50 A
9 GND T 51 B T 51 A GND R 51 B R 51 A
10 GND T 52 B T 52 A GND R 52 B R 52 A
11 GND T 53 B T 53 A GND R 53 B R 53 A
12 GND T 54 B T 54 A GND R 54 B R 54 A
13 GND T 55 B T 55 A GND R 55 B R 55 A
14 GND T 56 B T 56 A GND R 56 B R 56 A
15 GND T 57 B T 57 A GND R 57 B R 57 A
16 GND T 58 B T 58 A GND R 58 B R 58 A
17 GND T 59 B T 59 A GND R 59 B R 59 A
18 GND T 60 B T 60 A GND R 60 B R 60 A
19 GND T 61 B T 61 A GND R 61 B R 61 A
Pin F E D C B A
1 GND T 62 B T 62 A GND R 62 B R 62 A
2 GND T 63 B T 63 A GND R 63 B R 63 A
Pin F E D C B A
11 GND GND
12 GND GND
Pin F E D C B A
Pin F E D C B A