Nokia

DXT Plug-in Unit Descriptions

ET4E, ET4E-C, ET4A

DN0423851
Issue 1-0
 ET4E, ET4E-C, ET4A

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2 © 2016 Nokia DN0423851 Issue: 1-0

ET4E, ET4E-C, ET4A

Table of Contents
This document has 34 pages

1 Summary of changes .................................................................... 6

1.1 Issue 1-0........................................................................................ 6

2 ET4E, ET4E-C, ET4A overview..................................................... 7

3 Capacity and performance of ET4E, ET4E-C, ET4A..................... 9

4 Structure of ET4E, ET4E-C, ET4A...............................................10

4.1 Mechanical structure of ET4 plug-in units.................................... 10
4.2 Logical structure of ET4 plug-in units...........................................10
4.3 Operating principles......................................................................11
4.3.1 Microprocessor (CPU) and memories.......................................... 11
4.3.2 Bus architecture........................................................................... 15
4.3.3 Programmable logic..................................................................... 16
4.3.4 Clocking scheme..........................................................................16
4.3.5 Reset structure.............................................................................17
4.3.6 Interrupt structure.........................................................................18
4.4 Interfaces..................................................................................... 18
4.4.1 Line interface................................................................................18
4.4.2 Framer..........................................................................................18
4.4.3 Backplane interface......................................................................19

5 Operation of ET4E, ET4E-C, ET4A..............................................20

6 Power consumption of ET4E, ET4E-C, ET4A..............................22

7 ET4E C108784, ET4A C108786.................................................. 23

8 ET4E-C C108785.........................................................................25

9 Connector maps of ET4E, ET4E-C, ET4A................................... 28

9.1 Front panel connectors................................................................ 28
9.2 Backplane connector....................................................................29
9.3 Interface between mother board and daughter board..................32

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List of Figures
Figure 1 The operating environment of the ET4E and ET4E-C..........................8
Figure 2 The operating environment of the ET4A...............................................8
Figure 3 The block diagrams of the ET4E and ET4E-C................................... 10
Figure 4 The block diagrams of the ET4A........................................................ 11
Figure 5 Front panels and LED indicators of the ET4 plug-in units.................. 20
Figure 6 Connectors, LED indicator and jumper group B2............................... 23
Figure 7 Connectors, LED indicator and jumper groups B2 and B3...B6......... 25
Figure 8 Front panel connectors.......................................................................28

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List of Tables
Table 1 MPC 8280 Hardware cofiguration...................................................... 12
Table 2 The basic parameters for the Boot Flash........................................... 15
Table 3 Interchangeability code (ICC) settings (B2)........................................23
Table 4 Interchangeability code (ICC) settings (B2)........................................25
Table 5 The selection of the cable sheath.......................................................26
Table 6 Terminal assignment list of the ET4E-C variant SMB connectors...... 28
Table 7 Terminal assignment list of the ET4E and ET4A variants' RJ45
connectors.......................................................................................... 28
Table 8 Terminal assignment list of the euroconnector between ET4 plug-in
units and the backplane......................................................................29
Table 9 Meanings of the backplane connector signals....................................31
Table 10 Interface betwwen the mother board and the daughter board............33
Table 11 Meanings of the signals between mother board and daughter board....
33

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Summary of changes ET4E, ET4E-C, ET4A

1 Summary of changes
Changes between document issues are cumulative. Therefore, the latest document
issue contains all changes made to previous issues.

1.1 Issue 1-0

This is the first issue of ET4E, ET4E-C, ET4A.

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ET4E, ET4E-C, ET4A ET4E, ET4E-C, ET4A overview

2 ET4E, ET4E-C, ET4A overview

This document describes the ET4E, ET4E-C, ET4A exchange termination plug-in units.
For reasons of simplicity and clarity, ET4 is used for all these plug-in units when no
distinction between plug-in units is needed.
Purpose of ET4 units
Three different variants are defined for the ET4 plug-in units:

• the ET4E with RJ45 connector (symmetrical E1 interfaces)

• the ET4E-C with SMB connector (coaxial E1 interfaces)
• the ET4A with RJ45 connector (symmetrical T1 interfaces)

The ET4 is the exchange terminal unit. It has four external PCM-interfaces (either E1,
T1), interfaces to switching network and to the HDLC/LAPD channel, on-board power
supply, and clock system for generating the 8 kHz synchronising signal to the
synchronisation unit. The ET4 can be installed in the current ET4C and ET5C and in the
new ET4C-C type cartridges.
The ET4E and ET4E-C plug-in units comply with the E1 standards and connect four
2.048 Mbit/s E1 lines to a DX 200 based network element. The ET4A complies with the
T1 standards and connects four 1.544 Mbit/s T1 circuits to a DX 200 based network
element.
The ET4 provides the following:

• four PCM interfaces

• an 8Mbit/s interface between the ET4 and the Group switch (GSW1KB)
• one synchronization output towards the exchange clock system available in the ET4.

Although echo cancelling is not implemented at present, the ET4s already have
hardware support for installing the echo cancelling daughter board in the future.
Operating environment of ET4 units
The ET4 plug-in units are connected to eight external 2.048 Mbit/s (E1) or 1.544 Mbit/s
(T1) lines. The units are connected to the switching network with two duplicated 4.096
Mbit/s internal PCM circuits (two 1.544 Mbit/s PCM circuits are first converted to 2.048
Mbit/s and then multiplexed to one cable). The units are connected to the controlling
computer with an LAPD link which is connected to time-slot 0 of the even PCM circuit.
Operating voltages required by the units are formed with an on board integrated power
unit from an external -48 V voltage.
The following figures display the operating environments of the ET4 plug-in units.

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Figure 1 The operating environment of the ET4E and ET4E-C

4x2.048M/ET4 GSW1KB 4x2.048M/ET4

ET4E/ 1x8M 1x8M ET4E/
G.703 G.703
ET4E-C LAPD LAPD ET4E-C
PSTN BSS/BSC

ET4E/ ET4E/
ET4E-C ET4E-C

ET- ET-
Signalling Signalling
controlling controlling
computer computer
computer computer

DN0478014

Figure 2 The operating environment of the ET4A

4x1.544M/ET4 4x1.544M/ET4
1x8M GSW1KB 1x8M
T1.403 ET4A ET4A T1.403
PSTN LAPD LAPD BSS/BSC

ET4A ET4A

ET- ET-
Signalling Signalling
controlling controlling
computer computer
computer computer

DN0478159

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ET4E, ET4E-C, ET4A Capacity and performance of ET4E, ET4E-C, ET4A

3 Capacity and performance of ET4E, ET4E-C,

ET4A
The capacity of the ET4E, ET4E-C, and ET4A is four 2.048 Mbit/s E1/T1 lines.
The ET4 has

• Four E1/T1 ports on the front panel

• PM4354 COMET-QUAD framer
• MPC850 PowerQUICC processor at 50MHz
• 8MByte SDRAM main memory at 50MHz
• 512kByte Boot Flash
• Serial I2C EEPROM for Board Information Block
• Backplane interface
– 8.192MBit/s serial interface
– 64kBit/s HDLC/LAPD interface

• Hardware support for installing the echo cancelling daughter board in the future
• Single alarm LED indicator on the front panel
• FPGA for timing adaptation, clock supervision and glue logic.

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4 Structure of ET4E, ET4E-C, ET4A

4.1 Mechanical structure of ET4 plug-in units

ET4 plug-in units
The ET4 plug-in units consist of a single printed wiring board (PWB), the size of which is
100 mm x 222 mm, and an echo cancelling daughter board. Line interface connectors
are located at the front panel of the plug-in unit. E1/T1 cables are connected with four
RJ48C connectors (the ET4E, ET4A), and E1 coaxial cables are connected with four
SMB connectors (the ET4E-C). There is one bicolorered LED (red/orange) indicator on
the front panel.
The ET4 plug-in units are connected to the backplane of the cartridge with a 3 x 32-pin
Euroconnector.

4.2 Logical structure of ET4 plug-in units

The following block diagrams of the ET4 plug-in units illustrate the logical structure
(including possible loop interfaces).

Figure 3 The block diagrams of the ET4E and ET4E-C

Data-,address- CPU LAPD

ET_IF andcontrolbus SW_IF

E1 1.Speechchannels
PCM- +TSO
circuits 2.Clocksystem
3.Sideselection
Speech channels 4.Separate
LAPD-PCM-
cable
Operatingvoltagesto
Plug-inUnit

-48V
DC/DC-converter

DN0478302

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Figure 4 The block diagrams of the ET4A

Data-,address- CPU LAPD

ET_IF andcontrolbus SW_IF

T1/JT1
PCM-circuits 1.Speechchannels
(RBS-signalling) +TSO
2.Clocksystem
3.Sideselection
Speech channels
4.(TS25)
Operatingvoltagesto
Plug-inUnit

-48V
DC/DC-converter

DN0478314

4.3 Operating principles

4.3.1 Microprocessor (CPU) and memories
The ET4 includes one Motorola PowerQUICC device MPC850. The device is a versatile,
single-chip intergrated microprocessor and CPM that is ideally suited for controller
applications in network and communication products. The MPC850 provides the ET4
with the following:

• Embedded 32bit MPC8xx core with 2kByte data and 1kByte instruction cache and
memory management unit (MMU)
• External 32bit data bus
• External 26bit address bus (256MByte addressable)
• System integration unit (SIU) with software watchdog, clock synthesizer,
decrementer and reset controller
• Memory controller for eight banks, glueless interface for SDRAM, SRAM and Flash
devices
• Four 16-bit general-purpose timers
• Interrupt controller with up to 20 external and 15 internal interrupts
• Communication processor module (CPM) with 32bit scalar RISC communication
processor and 8kByte of dual-port RAM
• Serial Communication controller (SCC) that is configured for HDLC mode
• Serial management controller (SMC) that is configured for UART mode
• I2C bus interface
• Time slot assigner (TSA) which allows the SCC to operate in multiplexed TDM
operation mode
• Single 3.3V supply voltage.
Hardware configuration
To ensure proper operation some the MPC850 features must be configured during
power-on reset and during the hardware reset.

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While _PORESET (power-on reset) is asserted, the reset configuration of the SPLL is
sampled on the MODCK[1-2] pins. The SPLL immediately begins to use the
multiplication factor value and external clock source for the SPLL determined by the
sampled MODCK[1-2] pin and attempts to achieve lock.
When a hardware reset event occurs and when the signal _RSTCONF is pulled low at
the same time, the MPC850 determines its initial mode of operation by sampling the
values present on the data bus D[0-31]. The signals D[0-31] are pulled down internally,
therefore only configuration pins that need a logic HIGH must be driven externally. The
table below shows the necessary hardware configuration of the MPC850 during reset.

Table 1 MPC 8280 Hardware cofiguration.

MPC 8280 pin Value Description

MODCK[1-2] 10 Core frequency is 50MHz oscillator input

EXTCLK

D0 0 Internal arbitration for bus interface

D1 1 Interrupt exceptions are vectored to physical

address 0x000n.nnnn

D3 0 Memory controller is acivated after reset so that

it matches all addresses and starts booting from
_CS0

D[4-5] 01 Boot Flash size is 8bit

D[7-8] 00 Internal memory region is 0xFFF0.0000

D[9-10] 11 Debug pin configuration

D[11-12] 11 Debug port pin configuration

D[13-14] 00 External bus is running at core frequency

(50MHz)

Memory controller
The MPC580 processor contains a memory controller for up to eight memory banks that
are shared between a general-purpose chip-select machine (GPCM) and a pair of
sophisticated user-programmable machines (UPMA and UPMB).
The GPCM provides interfacing for simpler and lower-performance memory resources
and memory-mapped devices. The GPCM does not support bursting. The GPCM
provides a _CS signal for each memory region, _WE signals for write cycles for each
byte written to memory, and _OE signal for read cycles. Timing for these signals can be
configured very flexibly via the memory controller register set.
The UPM provides both more features and, because it supports bursting, higher
performance. Therefore it is typically used to interface with higher-performance memory
such as SDRAM. The UPM supports address multiplexing of the external bus, periodic
timers, and generation of programmable control signals for row address and column
address strobes to allow for a glueless interface to DRAM devices. The periodic timers

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allow refresh cycles to be initiated while the address multiplexing provides row and
column addresses. The UPM is a microsequencer that requires microinstructions or
RAM words to generate signal timings for different memory cycles. The contents of the
internal-memory RAM array specifies the logical value driven on the external memory
controller pins for a given clock cycle. Timing resolution for the signals is one quarter of
the external bus clock CLKOUT, that is used as SDRAM clock. The UPM provides a _CS
signal for memory bank activation, four dedicated byte select signals _BST[0:3] and six
general-purpose signals _GPL[1:5] and _GPL0.
Serial management controller
The two serial management controllers (SMC) of MPC850 are fullduplex ports that can
be configured independently to support one of three protocols:

• UART mode (in use on the ET4)

• Transparent mode
• General circuit interface

The following main features are supported by the SMC in UART mode:

• Flexible message-oriented data structure

• Programmable data length (514 bits)
• Programmable 1 or 2 stop bits
• Even/odd/no parity generation and checking
• Frame error, break, and IDLE detection
• Transmit preamble and break sequences
• Received break character length indication
• Continuous receive and transmit modes
• Clocking by internal baud rate generator or clock pin.
Serial communication controller
The MPC850 used on the ET4 has one serial communication controller (SCC2), which
can be configured to implement different protocols for bridging functions, routers, and
gateways, and to interface with a wide variety of standard WANs, LANs, and proprietary
networks. The SCC has many physical interface options such as interfacing to a TDM
bus, an ISDN bus, or a standard modem interface.
The choice of protocol is independent from the choice of interface. When the SCC is
programmed to a certain protocol or mode, it implements functionality that corresponds
to parts of the protocols' link layer. The following protocols / modes are supported by the
SCC:

• UART mode
• HDLC mode (in use on the ET4)
• Transparent mode
• Ethernet mode

On the ET4, a 64kbit/s HDLC/LAPD link is provided via the backplane. The link is used
for software downloading, for supervision and control of the T4 board. The link resides
either in timeslot 0 of the 8.192MBit/s TDM line or in timeslot N of the seperate control
TDM line, where N is defined by the slot number. The slot number is provided via the
backplane signals TS[0:5] and can be in the range of 0..63. Selection of the TDM line is
done via multiplexer plus extraction of timeslot via Time Slot Assigner (TSA).

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The serial communication controller SCC2 is responsible for handling the HDLC/LAPD
link. SCC2 must be configured for the HDLC mode.
Time Slot Assigner
The selected TDM line is connected to the serial interface (SI) of the MPC850 which is
configured in the TDM mode. The following TDM pins are provided by the MPC850 TSA:

• L1RXDA Connected to receive data of the TDM line

• L1TXDA Connected to transmit data of the TDM line

In addition, some pins are needed for clocking and synchronisation of the TSA. The
signals are “generated” within programmable logic:

• L1RSYNCA, L1RCLKA Receive synchronisation (frame pulse) and clock

• L1TSYNCA, L1TCLKA Transmit synchronisation (frame pulse) and clock

The TSA simply routes pre-programmed portions of the received data frame from the
TDM pins to the target SCC2, while the target SCC2 processes the received data
according tothe configured protocol. The routing information for the TDM line is
contained in the 512Byte SI RAM inside the MPC850. The SI RAM has 128 32bit entries
- 64 entries each for transmit and receive routing, when TSA is configured for static
mode. For the ET4 application only, one timeslot (8Bit) out of 128 timeslots is routed to
the target SCC2. Therefore, the ten SI-RAM entries are sufficient when they are
programmed as in the example below (where TS5 is selected):

• RAM entry 1 covers TS0...TS4 - 5Bytes

• RAM entry 2 covers TS5 - 1Byte
• RAM entry 3 covers TS6...TS15 - 10Bytes
• RAM entry 4 covers TS16...TS31 - 16Bytes
• ....
• RAM entry 10 covers TS112...TS127 - 16Bytes
I²C interface and board information block
The MPC850 processor includes a I²C controller for access to serial devices like
EEPROMs. The main features of the I2C controller are:

• Independent programmable baud rate generator

• Two signal interface via SDA and SCL
• Master and slave operation
• Support of 7bit addressing

Connected to the I²C interface of the MPC850 is one 24C04 EEPROM device (4kBit) that
is used to store the following information:

• Variant information
• Version information
• Unit identification information
General-purpose I/O functions
The MPC850 provides 49 general-purpose I/O pins (GPIO). On the ET4, the GPIO pins
are used for the following main functions:

• TSA pins
• UART interface

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• I2C bus interface

• FPGA configuration
• Reset generation
• Alarm LED activation.

4.3.2 Bus architecture

The MPC850 external bus is a synchronous, burstable bus that can support multiple
master and slave devices. Accesses to 32, 16 and 8-bit slaves are controlled by the
memory controller. On the ET4 only, slave devices are connected to the bus interface.
Note that the bit numbering of the MPC850 follow the PowerPC architecture definition,
which means that bit0 is the most significant bit and is the least significant bit.
The bus interface features are:

• 26bit address / 32bit data bus

• Access to 32, 16 and 8bit devices
• Glueless interface to slave devices
• Synchronous architecture
Memory controller machine configuration
Two different memory controller machinesd are used to access the different devices that
are attached to the external bus. The GPCM is used to access the BootFlash and the
PM4354 Framer. The control signal timing must be configured by different GPCM
registers. The UPMA is used to access the SDRAM while UPMB is used to access the
SRAM and the UART.
Boot flash memory
At least 512 kByte of Boot flash memory are supported on the ET4. A socket will be
provided for the Flash to allow easy update during debugging phase and the use of a
PROMICE emulator. The basic parameters for the Boot Flash are given below.

Table 2 The basic parameters for the Boot Flash

Used Device AMD AM29LV040B

Organisation 512k x 8bit

Power Supply 3.3V

Used Memory Machine GPCM

Used Chip Select _CS0

The control signals _CS0, _OE and _WE are driven by the general-purpose chip select
machine GPCM. The _CS0 signal is the boot chip select output and its operation differs
from the other external chip select outputs on the system reset. Boot chip select
operation allows address decoding for a boot device before system initialization occurs.
When the MPC850 internal core begins accessing memory after system reset, _CS0 is
asserted for the complete address range. The boot chip select provides a programmable
port size during system reset by using the BPS field of the hard reset configuration word.

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SDRAM memory
8 MByte of SDRAM memory is available on the ET4.
The control signals for the SDRAM are generated by the UPMA. The _CS on the
SDRAM is connected to _CS1 on the MPC850. The DQM signals of the used SDRAM
device select byte lanes and are connected to the appropriate byte strobe _BS0:3
signals on the MPC850. SDRAM address A10 is connected to _GPL0 on the MPC850
because it is required that A10 acts as an address line and a control line. _RAS, _CAS
and _WE are generated by MPC850 signals _GPL2, _GPL3 and _GPL4 respectively.
The SDRAM clock is driven by the MPC850s CLKOUT signal. The used SDRAM has
2048 rows and 256 columns, and therefore 11-row address lines and 8-column address
lines must be used. The _BS1:0 lines are connected to MPC850 address lines A9:10
and are used as high order address bit.
Framer interface
The control signals _CS2, _OE and _WE for access to the registers of the PM4354
Framer are driven by the general-purpose chip select machine GPCM.
Serial terminal interface
A Texas Instrument's TL16C550C controller is used to provide a serial terminal interface
for debugging purposes. The control signals _CS4, _OE and _WE are driven by the
UPMB.

4.3.3 Programmable logic

Some special functions of the ET4 are implemented in the programmable logic. The ET4
contains one Xilinx SpartanII XC2S15 FPGA. The FPGA is a SRAM-based Gate Array
that is In-System configurable in slave serial mode via MPC850 processor pins. The
FPGA image must be included in the Boot Flash device. The FPGA will loose its
configuration in case of powerdown.
The main functions implemented in the FPGA are:

• Timing adaption for interface to/from GSW1KB

• Clock supervision
• Clock distribution to PM4354
• Frame sync adaption for PM4354 and MPC850
• TCL clock generation and RSYNC divider
• Multiplexer MX3-MX6 for TDM line routing
• Alarm generation
• Debouncing of changeover signal
• Timeslot reordering (for the T1 variant ET4A)
• Additional test functions

4.3.4 Clocking scheme

The ET4 has the following independent clock domains: processor core, SDRAM, serial
terminals, H-MVIP interface, synchronization (TCL) signal, clock supervision.
Processor core

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The MPC850 processor is running at a core frequency of 50.0MHz. This clock is

provided to the EXTCLK pin of the processor by an Epson SG710-type oscillator. The
frequency stability of the oscillator is 50ppm. The oscillator needs 3.3V supply voltage.
SDRAM
CLKOUTs clock signal is used to clock the SDRAM interface.
Serial terminals
Rreference clock for the serial terminal interface controller TL16C550C is generated by
an internal baud rate generator.
Additionally, an Epson SG8002 type oscillator with 1.8432MHz is provided for
debugging. The frequency stability of the oscillator is 100ppm. The oscillator needs a
3.3V supply voltage.
H-MVIP interface
The system provides an 8kHz and 8.192MHz clock via the backplane interface. These
two clock signals are the timing reference for the 8.192MBit/s data TDM line and the
seperate 8.192MBit/s control TDM line. All further clocks for PM4354 backplane interface
and MPC850 TSA are derived from these two clocks.
Synchronization (TCL and RSYNC) signal
Synchronization Signal (RSYNC) which is either

• 1.544MHz for the ET4A or

• 2.048MHz for the ET4E / ET4E-C.

The source of RSYNC is software-programmable and is one of the four ports (default is
port 1). RSYNC is provided to the backplane pin RTCP and connected to the FPGA to
generate the 8kHz TCL signal that is also provided to the backplane connector.
The TCL backplane driver is always enabled. In case of LOS, the framer automatically
disables the RSYNC output and helds RSYNC high during the LOS condition.In case of
equipment loopback, AIS reception, frame alignment loss and CRC multiframe alignment
loss condition and an interrupt is issued to the MPC850 and the software has to disable
TCL generation (TCL is held high) inside the FPGA by setting the signal DisableTCL.
Clock supervision
The clock supervision (implemented in the FPGA) generates a clock alarm if one of the
following disruptions are observed in the 8 kHz or 8.192 MHz clock: too much / too few
pulses in frame, clock missing or clock stucked at “0” or “1”.

4.3.5 Reset structure

Different sources and levels are defined for the reset structure:

1. The voltage monitor supervises the on-board power supply. During power-on, the
monitor asserts _PORESET signal. The typical reset pulse width is 200ms.
_PORESET is connected to the MPC850.
2. When _PORESET is asserted, the MPC850 samples the MODCK bits and
configures the internal PLL. The MPC850 enters the power-on reset state and stays
there until both of the following events occur: – Internal PLL enters lock state and
system clock is active – _PORESET is deasserted

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Structure of ET4E, ET4E-C, ET4A ET4E, ET4E-C, ET4A

3. With the negation of _PORESET or PLL lock, the MPC850 enters the state of
internal initiated _HRESET, and drives _HRESET for 512 clock cycles (10us). Once
the 512 cycles are elapsed, the MPC850s hardware configuration is sampled from
the data signals and the core stops internally asserting _HRESET. During _HRESET
the UART and the BootFlash are also reset.
4. With the negation of _HRESET the MPC850 starts reading basic firmware code from
the BootFlash memory. After basic register initialization, the FPGA are configured via
MPC850 GPIO pins.
5. _FPGA_RESET, _FRAMER_RESET and _DCARD_RESET are driven by the
MPC850 and therefore are automatically held active during the complete power-on,
_HRESET and FPGA configuration procedure. After the FPGA configuration is
finished the software has to release these reset signals.

4.3.6 Interrupt structure

An interrupt controller with up to 20 external and 15 internal interrupts is included in the
MPC850 processor. The following external signals are connected to the interrupt
controller:

• _INT1 PM4354 interrupt output

• _INT3 TL15C550 UART interrupt
• _INT4 Backplane signal ALTST
• _INT5 Clock supervision interrupt (active when clock error is detected)

All interrupts are maskable by software. _INT1 has the highest priority and _INT4 hasthe
lowest priority.

4.4 Interfaces
4.4.1 Line interface
E1 Interface
The E1 line interface consists of interface protection with magnetics, and line interface
with LIU and framer (integrated in the PM4354). For the E1 interface, there is no
overvoltage protection on the secondary side of the isolation transformer.
T1 Interface
The T1 line interface consists of interface protection with magnetics, and line interface
with LIU and framer (integrated in the PM4354). For the T1 interface, overvoltage
protection is available on the secondary side of the isolation transformer.

4.4.2 Framer
The ET4 includes one PMC-Sierra PM4354 COMET-QUAD device . The device contains
a four-channel combined E1/T1 frame with line interface unit in a single chip.
The following features of PM4354 are essential for the ET4:

• Four integrated E1/T1 framers

• E1/T1 line interface unit

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• Software selectable between E1 and T1 operation

• Encoding and decoding of the B8ZS, HDB3 and AMI line codes
• Receive equalization, clock recovery and line performance monitor
• Transmit and receiver jitter attenuation
• Selectable de-jittered E1 or T1 recovered line clock for system clock synchronisation
• Programmable pulse shape to adapt LIU to line length (E1: short haul, T1: long haul)
• Transparent forwarding of national SA bits
• Through timing mode from backplane interface or loop mode
• E1 CRC-4 multiframe, doubleframe and unframed mode
• T1 SF, ESF and unframed mode
• 8.192Mbit/s H-MVIP backplane interface for all E1 and T1 links. Device operates in
H-MVIP clock slave mode with elastic store
• 8.192Mbit/s H-MVIP interface for channel associated signaling (CAS) extraction from
T1 ESF or SF including robbed bit signalling (RBS) support
• 8bit multiprocessor interface for configuration, control and status monitoring and
performance statistics
• Possibility to generate interrupt when line status changes
• Line, payload and diagnostic loopback modes
• Single 2.048 MHz clock for E1 and T1 mode

4.4.3 Backplane interface

The ET4 has a 8.192MBit/s backplane interface that carries all E1 and T1 timeslots.

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Operation of ET4E, ET4E-C, ET4A ET4E, ET4E-C, ET4A

5 Operation of ET4E, ET4E-C, ET4A

Front panel of ET4 plug-in units
Figure 5 Front panels and LED indicators of the ET4 plug-in units

DN0478326

On the left, the front panel of the ET4E-C; on the right, the
front panel of the ET4E and ET4A.

LED indicator
The front panel of the ET4 plug-in units has one bi-coloured (red and orange) alarm LED
indicator. It is provided together with the lightpipe. The following functions are defined:

1. If there are no alarms or errors, the LED is off.

2. If there is a clock alarm, the LED is on (red colour)
3. If the following special situations occur in incoming or outgoing PCMs, the LEDis on
(orange colour):
• loss of incoming signal or frame
• AIS in incoming or outgoing direction
• BER in incoming direction > 10E-3
• equipment or line loop is activated.

g Note: ALTST signal does not turn the red LED on.

Front panel connectors

On the ET4E-C variant, there are four pairs of 50Ohm SMB connectors (J1 to J8) on the
front panel. For detailed information, see Connector maps of ET4E, ET4E-C, ET4A.
On the ET4A and ET4E variants, there are four shielded RJ45 connectors (J1 to J4) on
the front panel. For detailed information, see Connector maps of ET4E, ET4E-C, ET4A.
Bakcplane connector

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The ET4 plug-in units are connected to the backplane with a non-shielded standard male
3 x 32-pin, right angle Euroconnector (P5). For connector map, see Connector maps of
ET4E, ET4E-C, ET4A.

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Power consumption of ET4E, ET4E-C, ET4A ET4E, ET4E-C, ET4A

6 Power consumption of ET4E, ET4E-C, ET4A

The typical power consumption for the ET4 plug-in units is presented the table below.

Operational voltage Typical power consumption

-5V 0.04W

+2.5V 0.2W

+3.3V 2.6W

+5V 0.5W

-48V 4.1W

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7 ET4E C108784, ET4A C108786

Figure 6 Connectors, LED indicator and jumper group B2

B2

P1

P2

P5

P3

P4

LD

DN0478341
2 4 6 8

B2

1 3 5 7
Interchangeability code
The setting of the interchangeability code is presented in the table below (B2).

Table 3 Interchangeability code (ICC) settings (B2).

ICC code Setting
7-8 5-6 3-4 1-2

A ON ON ON ON

B ON ON ON OFF

C ON ON OFF ON

D ON ON OFF OFF

E ON OFF ON ON

F ON OFF ON OFF

G ON OFF OFF ON

H ON OFF OFF OFF

J OFF ON ON ON

K OFF ON ON OFF

L OFF ON OFF ON

M OFF ON OFF OFF

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Table 3 Interchangeability code (ICC) settings (B2). (Cont.)

ICC code Setting
N OFF OFF ON ON

P OFF OFF ON OFF

R OFF OFF OFF ON

S OFF OFF OFF OFF

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8 ET4E-C C108785
Figure 7 Connectors, LED indicator and jumper groups B2 and B3...B6

B2

J1
B3
J2

J3
B4
J4
P5
J5
B5
J6

J7
B6
J8

LD

DN0478353
2 4 6 8 5 3 1

B2 B3...B6

1 3 5 7 6 4 2
Interchangeability code
The setting of the interchangeability code (ICC) with B2 is presented in the table below.

Table 4 Interchangeability code (ICC) settings (B2).

ICC code Setting
7-8 5-6 3-4 1-2

A ON ON ON ON

B ON ON ON OFF

C ON ON OFF ON

D ON ON OFF OFF

E ON OFF ON ON

F ON OFF ON OFF

G ON OFF OFF ON

H ON OFF OFF OFF

J OFF ON ON ON

K OFF ON ON OFF

L OFF ON OFF ON

M OFF ON OFF OFF

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ET4E-C C108785 ET4E, ET4E-C, ET4A

Table 4 Interchangeability code (ICC) settings (B2). (Cont.)

ICC code Setting
N OFF OFF ON ON

P OFF OFF ON OFF

R OFF OFF OFF ON

s OFF OFF OFF OFF

The selection of the cable sheath is presented in the table below (B3...B6).

Table 5 The selection of the cable sheath.

Selection criteria Jumper Note
Output direction cable sheath of B3: 4 - 6 Factory setting
circuit 0 not connected

Output direction cable sheath of B3: 2 - 4

circuit 0 galvanically connected to
GND

Input direction cable sheath of B3: 3 - 5 Factory setting

circuit 0 not connected

Input direction cable sheath of B3: 1 - 3

circuit 0 galvanically connected to
GND

Output direction cable sheath of B4: 4 - 6 Factory setting

circuit 1 not connected

Output direction cable sheath of B4: 2 - 4

circuit 1 galvanically connected to
GND

Input direction cable sheath of B4: 3 - 5 Factory setting

circuit 1 not connected

Input direction cable sheath of B4: 1 - 3

circuit 1 galvanically connected to
GND

Output direction cable sheath of B5: 4 - 6 Factory setting

circuit 2 not connected

Output direction cable sheath of B5: 2 - 4

circuit 2 galvanically connected to
GND

Input direction cable sheath of B5: 3 - 5 Factory setting

circuit 2 not connected

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Table 5 The selection of the cable sheath. (Cont.)

Selection criteria Jumper Note
Input direction cable sheath of B5: 1 - 3
circuit 2 galvanically connected to
GND

Output direction cable sheath of B6: 4 - 6 Factory setting

circuit 3 not connected

Output direction cable sheath of B6: 2 - 4

circuit 3 galvanically connected to
GND

Input direction cable sheath of B6: 3 - 5 Factory setting

circuit 3 not connected

Input direction cable sheath of B6: 1 - 3

circuit 3 galvanically connected to
GND

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Connector maps of ET4E, ET4E-C, ET4A ET4E, ET4E-C, ET4A

9 Connector maps of ET4E, ET4E-C, ET4A

9.1 Front panel connectors

The ET4E-C variant has four pairs of 50Ohm SMB connectors and the ET4A and ET4E
variants have four shielded RJ45 connectors on the front panel (see the figure below).

Figure 8 Front panel connectors

2 1
1

8
4 3

DN0478338

Terminal assignment list of the ET4E-C variant SMB connectors is presented in the table
below.

Table 6 Terminal assignment list of the ET4E-C variant SMB connectors.

Pin Function (N = port number 0...3)

1 RxTip_N

2 RxRing_N

3 TxTip_N

4 TxRing_N

Terminal assignment list of the ET4E and ET4A variants' RJ45 connectors is presented
in the table below.

Table 7 Terminal assignment list of the ET4E and ET4A variants' RJ45 connectors.

Pin Function (N = port number 0...3)

1 RxRing_N

2 RXTip_N

3 NC

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Table 7 Terminal assignment list of the ET4E and ET4A variants' RJ45 connectors.
(Cont.)

Pin Function (N = port number 0...3)

4 TXRing_N

5 TxTip_N

6 NC

7 NC

8 NC

9.2 Backplane connector

The backplane connector signals are presented in the table below. Note that low active
signals are marked as follows: _TAL (an example).

Table 8 Terminal assignment list of the euroconnector between ET4 plug-in units
and the backplane.

Pin C B A

1 -UB -UB -UB

2 CR0B CR0A CT0A

3 CT0B

4 D0V

5 B0V B0V B0V

6 CR1B CR1A CT1A

7 CT1B

8 D0V

9 NTIM_1 NTIM_0 0VG

10 RSVD5 OVG RSVD1

11 RSVD6 OVG RSVD2

12 _TAL D0V

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Connector maps of ET4E, ET4E-C, ET4A ET4E, ET4E-C, ET4A

Table 8 Terminal assignment list of the euroconnector between ET4 plug-in units
and the backplane. (Cont.)

Pin C B A

13 ALTST

14 RSVD7 RSVD3

15 RSVD8 RSVD4

16 D0V

17 +5VA CSB CSA

18 _SPRP TCL0A

19 TS0 TCL0B

20 TS1 D0V

21 TS2

22 TS3

23 TS4

24 TS5 D0V

25 -5VA 8M0B 8M0A

26 RCTP0

27 8K0B 8K0A

28 D0V

29 T0B T0A

30 T1B T1A

31 R0B R0A

32 D0V R1B R1A

The table below presents the meanings of the backplane connectors.

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Table 9 Meanings of the backplane connector signals.

Pin Meaning

-UB, B0V Accumulator voltage

OVG Overvoltage ground

D0V Digital ground. Overvoltage ground and digital ground are separate on the
PWB, and they are connected together in the cartridge.

8M0A, 8M0B, 8K0A, Basic timing signals. Line receiver has been of type 75107, but MAX92201
8K0B may also be used. Equipped with series resistors of 1 kOhm to prevent clock
error when the plug-in unit is uninstalled.

R0A, R0B, R1A, R1B 8Mbit/s TDM circuits of the switching network. Line receiver has been of type
75107, but but MAX92201 may also be used.

T0A, T0B, T1A, T1B 8Mbit/s TDM circuits of the switching network. Line transmitter has been of
type 75110, but MAX3032 may also be used.

TCL0A, TCL0B Synchronizing signal of the synchronization unit.

CSA, CSB Inputs to changeover signal invoice. Comparator LM311 has been used for
reception, but MAX9201 may also be used. Sourced by 75119 line driver.

_TAL Basic timing alarm signal. Connected parallel in the cartridge and taken to
specific cabling place. Open-collector is used to prevent overloading if a fuse
blows.

ALTST Alarm test signal. Connected parallel in the cartridge and taken to specific
cabling place.

+5VA +5V output from ET4. Connected to +5V through a resistor of 100 Ohm and
diode. Connected in parallel in the cartridge.

-5VA -5V output from ET4. Connected to -5V through a resistor of 100 Ohm and
diode. Connected in parallel in the cartridge.

NTIM_0, NTIM_1 Timing mode.

NTIM_0 = “1”: PCM signals are connected to the switching network have
nominal timing.

NTIM_0 = “0”: transmitted PCM signals are advanced by 31 ns and sampling

of received PCM signals is delayed by 31 ns.

NTIM_1 = “1”: PCM signals conneted to the swtching network have nominal
timing.

NTIM_1 = “0”: transmitted PCM signals are advanced by 62 ns and sampling

of received PCM signals is delayed by 62ns.

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Connector maps of ET4E, ET4E-C, ET4A ET4E, ET4E-C, ET4A

Table 9 Meanings of the backplane connector signals. (Cont.)

Pin Meaning

Note that it is allowed to set only NTIM_0 or NTIM_1 to “0”, not both of them
at the same time.

NTIM signals are parallel connected cartridge wide and taken to the jumper
field in the cartridge back plane.

NTIM is equipped on the ET with a 4.7 kOhm pull-up resistor. In series with
the pull-up resistor there is a diode to prevent the decrease in the signal level
caused by a blown fuse. In addition, a resistor of 1 kOhm is connected in
series with CMOS input.

RCTP Test point receive clock. Selection of receive clock is made by software.
Equipped with series resistor of 150 Ohm.

TCTP Test point for transmit clock. Reserved for future use.

_SPRP Separate PCM circuit selection. Selected by jumper in the cartridge

backplane.

CR0A, CR0B, CR1A, Separate input control PCM circuits (8Mbit/s TDM circuits). Line receiver has
CR1B been of type 75107, but MAX9201 may also be used.

Connected parallel in the cartridge (R to R) and taken to specific cabling

place.

CT0A, CT0B, CT1A, Separate output control PCM circuits (8Mbit/s TDM circuits). Line transmitter
CT1B has been of type 75110, but MAX3032 may also be used

Connected parallel in the cartridge (T to T) and taken to specific cabling

place.

RSVD1...RSVD8 Reserved for future use

TS0...TS5 Reserved for future use

9.3 Interface between mother board and daughter

board

g Note: Although echo cancelling is not implemented at present, the ET4s already have
hardware support for installing the echo cancelling daughter board in the future. The the
connector is not assembled, but the tables below present the terminal assignments and
the meanings of the signals reserved for the interface between the ET4 mother board
and the daughter board.

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Table 10 Interface betwwen the mother board and the daughter board.

Pin Signal (to daughter board) Signal (from daughter board) Pin

1 D0V D0V 2

3 NIEC_TYPE0 NIEC_TYPE1 4

5 NIEC_TYPE2 NIEC_TYPE3 6

7 _BoardResetIn _BoardResetOut 8

9 TBD _AlarmOut 10

11 D0V D0V 12

13 Spare0 Spare1 14

15 Spare2 Spare3 16

17 D0V D0V 18

19 TBD TBD 20

21 TBD TBD 22

23 TBD TBD 24

25 ASCP_IN ASCP_OUT 26

27 D0V D0V 28

29 RBS_IN RBS_OUT 30

31 D0V D0V 32

33 RCV_IN RCV_OUT 34

35 D0V D0V 36

37 SND_IN SND_OUT 38

Table 11 Meanings of the signals between mother board and daughter board.

Signal Meaning

SND_ IN PCM circuit from the line to the daughter board

SND_ OUT PCM circuit from the daughter board to the

switching network

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Connector maps of ET4E, ET4E-C, ET4A ET4E, ET4E-C, ET4A

Table 11 Meanings of the signals between mother board and daughter board.
(Cont.)

Signal Meaning

RCV_ IN PCM circuit from the switching network to the

daughter board

RCV_ OUT PCM circuit from the daughter board to the line

_BoardResetIn Reset signal to the daughter board

_BoardResetOut Reset signal from the daughter board

ASCP_IN The data sent by UART to the daughter board

ASCP_OUT The data received by UART from the daughter

board

_AlarmOut Alarm from the daughter board

NIEC_TYPE_0…NIEC_TYPE Daughter board type.

_03

Spare0…Spare3 Spare pins connected to FPGA's I/O

RBS_IN Robbed Bit Signalling to the daughter board

RBS_OUT Robbed Bit Signalling from the daughter board

TBD To be decided later

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