Week 3 - Four Instruction CPU

Applied Mechanics and Materials Vols.
198-199 (2012) pp 1115-1120

Online available since 2012/Sep/26 at www.scientific.net
© (2012) Trans Tech Publications, Switzerland
doi:10.4028/www.scientific.net/AMM.198-199.1115
Four Instructions CPU
Hui Liua, Jianfei Ouyangb , Yuan Liuc

1
GanZhou, China
a
zdhdq@sohu.com, boyjf0606@126.com, cliuyuan_8888@126.com
Keywords: CPU; instruction set; computer; microprocessor; hardware systems; logic chips;
Abstract. This paper introduces using digital electronic technology of knowledge and logic devices
designed a four instruction set of the microprocessor, this processor enable the operation of eight-bit
binary number. Complete hardware and instruction set of microprocessor design, the
microprocessor can add two unsigned eight-bit binary number, subtraction, multiplication and
division functions.
Introduction
Perhaps many of my friends are CPU principle interested, we can gather from the Internet using
the transistor switch is closed binary operation or data storage "or something like that.The central
processing unit (CPU) is the core and control core of a computer operator.With the development of
the process, the degree of integration of the semiconductor chip, the design of the system is
increasingly complex, the increasing scale of the growing demand for high performance, power
consumption is also growing.
The CPU, internal memory and input / output device is the three core components of the
computer. Its main function is to explain the data in the computer instruction and dealing with
computer software.Arithmetic unit, controller and register and the data link between them, control
and status bus constitutes a CPU.Described the principle of operation of the CPU instruction can be
divided into three stages:fetch, decode, execute.Fetches instructions from memory into the
instruction register and instruction decoder, and execute the command.
The Design Of Four Instructions CPU

Microprocessor hardware consists of the following eight basic components: the operator,
controller, instruction register splitter, clock generator, the program counter, accumulator, address
register, the data selector. We require that the microprocessor can access memory 32byte, which
1byte = 8bits. So the CPU there are five address lines A [4:0], and eight data lines D [7:0], the
system structure shown in Figure 1.
Figure 1. Microprocessor hardware constitute the block diagram
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1116 Applied Mechanics, Mechatronics Automation & System Simulation
The work process of the microprocessor
A. Instruction fetch stage

The first phase, retrieved from memory or cache instruction (for the value or range of values).
Memory location specified by the program counter (Program Counter), the program counter saved
for to recognize the value of the current program location. In other words, the program counter
records the traces of the CPU in the current program.Fetch instructions, the program counter to
increase the memory unit according to the instruction length. Extraction of the directive must be to
find, often from relatively slow memory and therefore lead into the CPU to wait for instructions.
This problem is mainly addressed in modern processors, cache and pipelined architecture.
B. Instruction decoding stage
CPU memory abstraction to the instruction to determine its execution behavior. In the decode
stage, the instruction is disassembled into meaningful pieces. According to the CPU instruction set
architecture (ISA) to define the value is interpreted as a command.Part of the instruction value for
the operation code (opcode), and its instructions to which computing. Other values usually supply
the instruction necessary information, such as an addition (Addition) computing computing goals.
The goal of this operation may provide a constant value (ie, the value of addressing immediate
value), or a space: register or memory address, addressing mode decision.The old design, the part of
the CPU instruction decoder is a hardware device that can not be changed. However, in many
abstract and complex CPU and Instruction Set Architecture, a microprogram is often used to help
convert the instructions for various forms of signal. These micro-program has finished the CPU can
often be rewritten convenient to change the decoding instruction.
C. Instruction execution stage
After extraction and decoding stages, and then entered the implementation stage. The stages,
connected to the various operations required CPU components. For example, requiring an addition
operation, the arithmetic logic unit (ALU Arithmetic Logic Unit). Will be connected to a set of input
and output. The input to the sum of the values, the output will contain the sum of the results. The
ALU contains the circuitry, easy-to-output completion of a simple ordinary arithmetic and logical
operations (such as addition and bitwise). If the addition operation of the CPU processing is too large
results in the flag register, arithmetic overflow (Arithmetic the Overflow) flag may be set.
Instruction execution is completed, then moved to the next instruction of the instruction fetch
stage and began a new round of circulation. The entire work process shown in Figure 2.
Figure 2. Microprocessor course of their work
The System's Hardware Design

D. PC Program counter (PC)
The program counter of the schematic diagram shown in Figure 3, which CD4066 provides the
system clock frequency is 2HZ, so help us to observe the experimental phenomena.The counter part
using the 74HC393; latch part of the 74HC373 latch; 74HC125 tri-state as a PC with the address bus
connection part.
Applied Mechanics and Materials Vols. 198-199 1117
Figure 3. The program counter PC hardware schematic
E. ROM Unit
CPU storage unit schematic diagram shown in Figure 4, when we have made the PC value, the
decoder will point corresponding to the ROM area.
Figure 4. ROM area hardware schematic
F. Instruction decoder
Obtained from the instruction register eight instructions are separated into three parts, namely the
three destination operand address, the three source operand address and two actuator selection code.
The destination operand address and the source operand address selector switch through two
CD4066 data sharing release to the address on the bus. Actuator to select the code all the way to 2/4
decoder decoding selected to enable the corresponding instruction is executed.
G. Instruction Actuator
Instruction execution is the driver of the clock pulse, according to the function of the different
instructions, so that the data transmission of a control logic. Required to generate data path control
signal in two ways: hard-wired logic and program control. Here, we use hard-wired logic. Simple
CPU control logic consists of three components:
• Counter: used to generate the clock of the drivers required.
• Divider: Control the clock cycle, easy to debug and adjust the speed of the instruction to run.
• Decoder: to generate the control signals of the various state
A general principle of the control unit shown in Figure 5
Figure 5. Common control unit schematic

H. ALU structure and how it works

Arithmetic logic unit is the execution unit of the central processing unit (CPU) is a core
component of all central processing unit, arithmetic logic unit consisting of "And Gate" and "Or Gate,
the main function is binary arithmetic such as addition, subtract, multiply.Binary majority of modern
CPU architecture to complement the form.
Since this involved with ALU the ADD instruction, so the four accumulator is The ALU.4
accumulator consists of three parts, respectively, the full adder, accumulator A and accumulator B in
Figure 6.
Figure 6. Full adder schematic
I. Memory design
The storage structure of the computer, there are two commonly used were the Harvard storage
structure and von According to Mann storage structure. Harvard storage nodes and Feng According
to Mann storage structure the biggest difference is the data storage and program memory is unified
addressing the Harvard architecture, data storage and program memory are independent of each other
in addressing, in von Neumann unified addressing. Harvard architecture has the advantage of high
efficiency in the implementation, but the von Neumann architecture is much simpler, based on the
above reasons, we take the von Neumann storage structure. Therefore, the calculation of the four
instructions of the program, data, operation of the register set of memory operations.
• Program memory ROM: the stored program instructions.
• Data memory RAM: Read the temporary data storage computing intermediate variables.
• Special input and output registers: the data input and output.
Coding and the timing of the instruction set
J. The system completed the MOV, ADD, SUB, MUL instruction.
TABLE I. INSTRUCTION ENCODING TABLES

Instruc Encoding
tion Code DST SRC
MOV 00 010 001
ADD 01 010 001
SUB 10 010 001
MUL 11 010 001
Applied Mechanics and Materials Vols. 198-199 1119
K. Public execution block

The public code segment consists of two parts: the instruction fetch stage and decoding stage
fetch stage of the flow chart as follows:
1) Latch PC current value to the PC register.
2) The PC current value on the address bus.
3) Fetch the current value of the part of the latch PC.
4) Current value, according to PC to take the IR on the data bus.
5) Decoder latch IR current value.
6) According to the IR decoding.
After a public execution block, the CPU can begin to execute our written to the procedures
required by paragraph content of the code segment.
L. MOV function performs encoding

Execution over a public code snippet, we Implementation of the MOV instruction, its
implementation process are as follows:
1) Reading the source operand address.
2) Latched source address.
3) According to the source address to take the data to the data bus.
4) Latch data.
5) Read the target operand address.
6) Latch the target address.
7) SData read the DBUS and open the storage unit corresponding to the DAddr.
8) Write, to write SData DAddr corresponding unit.
M. Temporal Logic
Temporal logic in this topic is actually a control logic circuit, through the control bus to get real.
Control logic as shown in Figure 7. Temporal logic consists of two parts, the first part of the public
temporal logic, by Figure 9, the first four machine cycles to complete, which already contains the
first two phases of the implementation of a directive: address-stage and decoding stage, taking the
address of stage inside the timing of the first two machine cycles; the timing of the two machine
cycles inside the next decoding stage. The remaining belong to the actuator instructions executed by
the timing.
Figure 7. MOV instruction to control the timing
Summary
The issues we have completed the software and hardware design of the CPU.At the same
time,we complete our debugging in the experimental box,. Debugging results show that our design
of the CPU can be achieved add, subtract, multiply and divide.
References
[1] Advanced Micro Devices. Coming soon: The AMD fusion family of APUs Hou, Q., Zhou, K.,
Guo, B.: Debugging GPU stream programs through automatic dataflow recording and
visualization. ACM Transactions on Graphics 153(5), 153:1–153:11 (2009)
[2] Stuart, J.A., Owens, J.D.: Message passing on data-parallel architectures. In:Proceedings of the
23rd IEEE International Parallel and Distributed ProcessingSymposium (May 2009)
[3] gramming guide (February 2010),http://developer.nvidia.com/cu da.
[4] http://developer.download.nvidia.com/compu te/cu da/2 1/cudagdb/CUDA GDB
UserManual.pdf
[5] Yaakob, W.F., et al.: System-on-a-Chip Approach for Industrial Robotic Controller Design. In:
ICSE 2000 Proceedings (November 2000)
[6] Keating, M., Bricaud, P.: Reuse Methodology Manual for System-on-a-Chip Designs.3300 AH.
Kluwer Academic Publishing Group, Dodrecht, Netherlands (2005).
[7] Findenig, R., Priewasser, R., Eibensteiner, F., Pfaff, M.: Einsatz von EmbeddedLinux auf dem
Leon3 am Beispiel eines Hexapod-Roboters. Tagungsband Austrochip2006, TU-Wien and FH-
Technikum-Wien (October 2006).
[8] Free Software Foundation, Inc.: GNU General Public License (December
2006),http://www.gnu.org/copyleft/gpl.html.
[9] embedded Configurable operating system (December 2006),http://ecos.sourceware.org/.
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Applied Mechanics, Mechatronics Automation & System Simulation
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Four Instructions CPU

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Applied Mechanics and Materials Vols.

198-199 (2012) pp 1115-1120

Four Instructions CPU

Hui Liua, Jianfei Ouyangb , Yuan Liuc

The Design Of Four Instructions CPU

Figure 1. Microprocessor hardware constitute the block diagram

The work process of the microprocessor

A. Instruction fetch stage

Figure 2. Microprocessor course of their work

The System's Hardware Design

Figure 3. The program counter PC hardware schematic

Figure 4. ROM area hardware schematic

Figure 5. Common control unit schematic

H. ALU structure and how it works

Figure 6. Full adder schematic

Coding and the timing of the instruction set

J. The system completed the MOV, ADD, SUB, MUL instruction.

TABLE I. INSTRUCTION ENCODING TABLES

K. Public execution block

L. MOV function performs encoding

Figure 7. MOV instruction to control the timing

Four Instructions CPU

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