Unit3

1. Hazards
o Definition
o Types
o Explanation

Definition
Example
Diagram
Solutions
2. MIPS datapath and control
o Datapath elements
o Control signals
o Diagram: datapath with the control unit
Pipeline Hazards
There are situations in pipelining when the next instruction cannot execute in the following
clock cycle. These events are called hazards, and there are three different types.
I. Structural Hazard
2. Data Hazard
3. Control Hazard

Structural Hazard:
When a planned instruction cannot execute in the proper dock cycle because the
hardware does not support the combination of Instructions that are set to execute.
E.g., suppose single - 1101 separate - instruction and data memory in pipeline below with
one read port
Then a structural hazard between first and fourth lw instructions, the same clock cycle the
first instruction is accessing data from memory while the fourth instruction is fetching an
instruction from that same memory. Without two memories, our pipeline could have a
structural hazard.

15
 Program
execution 2 4 6 8 10 12 14
order Tme;====~;---;::=i;===i;==~=~-,----,----,---

-
(ln instructions) lnllrudion Reg ALU Date R
1w $1, 100($0) __
,._tch
_ _ _ _ _~ - - - - - - - - - -
lnstrucilon Data
R
Pipelined
fetch Reg ALU
1w $2, 200($0)
lntwction Data
fetch Reg ALU
1w $3, 300($0) 8CC8II
Instruction
2ns fetch Reg ALU
1w $4, 400($0) .,_____. ...,.____..... ._____..,___...... +-------+
2M 2M 2M 2M 2M

Data Hazards:
When a planned inslTuction cannot execute in the proper dock cycle because data
that is needed to execute the instruction is not yet available.
In a computer pipeline, data hazards arise from the dependence of one instruction on an
earlier one that is still in the pipeline. For example, suppose we have an add instruction followed
immediately by a subtract instruction that uses the sum (SsO):
add SsO, StO, St I
sub St2, SsO, St3
Without intervention, a data hazard could severely stall the pipeline. The add instruction
doesn't write its result until the fifth stage, meaning that we would have to waste three clock cycles
in the pipeline.

I. Forwarding: or bypassing:
A method of resolving a data hazard by retrieving the missing data element from internal
buffers rather than waiting for it to arrive from programmer visible registers or memory.
Program
execution 200 400 600 800 1000
order Time
(In Instructions)
add ' $10, $11

\
sub $12, $13

Fig.: Graphical representatlon of forwarding

The connection shows the forwarding path from the output of the EX stage of add lo the
input of the EX stage for sub, replacing the value from registerSsO read in the second stage of sub.

16
Load-use data hazard:
A specific fonn of data hazard in which the data being loaded by a load instruction has not
yet become available when it is needed by another instruction.
Program
execution 200 400 600 800 1000 1200 1400
order Tlme ---"T"""--"""T"---.----...------.----.------..--
On Instructions)
1w c; 1 20($11)

sub S12, $13

Fig: R-format instruction following a load tries to use the data

Pipeline stall: A stall initiated in order to resolve a hazard. Also called bubble.
Control Hazard:
When the proper Instruction cannot execute In the proper pipeline clock cycle because
the instruction that was fetched Is not the one that ls needed; that is, the now of instruction
addresses is not what the pipeline expected. Also called branch hazard.

$olYliPP I Stoll the pipeline

The below example assumes the conditional branch is taken, and the instruction at the
destination of the branch is the OR instruction. There is a one-stage pipeline stall, or bubble, after
the branch.

Program
execution 2T"00_ _400-.--__6_,oo
Time ___ ___800.--__
1ooo..--__1200.....-_ _1_,400
_ __

-
order
(in Instructions)
lnalNdlon
add $4, $5, $6 Reg ALU Reg

200 ps .___•-
_ __.
Reg ALU ..,.,...
0.111
Reg

, L
k..J l bl
or S7 SB. S9
400ps § IReol
ALU ..,.,...
Dau,
I I
Reg

So!utjop 2 Predict branch outcome

Computers do indeed use prediction to handle branches. One simple approach is to predict
always that branches will be untaken. When you're right, the pipeline proceeds at full speed. Only
when branches are taken does the pipeline stall.

Branch prediction:
A method of resolving a branch hazard that assumes a given outcome for the branch and
proceeds from that assumption rather than waiting to ascertain the actual outcome.
I. Static : predict always that branches will be untaken
2. Dynamic: prediction of branches is keeping a history for each branch as taken or
untaken, and then using the recent past behavior to predict the future.

18

Implementing control means sening the nine control lines to these values in each stage for
each instruction. The simplest way to do this is to extend the pipeline registers to include control
information. Since the control lines start with the EX stage, we can create the control information
during instruction decode. The above figure shows that these control signals are then used in the
appropriate pipeline stage as the instruction moves down the pipeline and shows the full datapath
with the extended pipeline registers and with the control lines connected to the proper stage.
*****************************************************************************
Building a Oatapath:
Datapath
Datapath is a collection of functional units organized in a manner to execute each class of
instruction.
Datapath element:
A unit used to operate on or hold data within a processor. In the MIPS implementation, the
datapath elements include the instruction and data memories, the register file, the ALU, and adders.

Datapath: Instruction Store/Fetch & PC Increment

Three elements used to store and fetch instructions and increment the PC.

-cs::;
-B- V
lnstl\ldion MEMIPCI
address

lnstrvctk>n
lnstrucoon
memo,y

a. Instruction memory b. Program counter c. Adder

Fig: Elements: Instruction Store/Fetch & PC Increment
The state elements are the instruction memory and the program counter. The instruction
memory need only provide read access because the datapath docs not write instructions. Since the
instruction memory only reads, we treat it as combinational logic: the output at any time renects
the contents of the location specified by the address input, and no read control signal is needed.
(We will need to write the instruction memory when we load the program; this is not hard to add.)
The program counter is a 32-bit register that is wrinen at the end of every clock cycle and thus
does not need a write control signal. The adder is an ALU wired to always add its two 32-bit inputs
and place the sum on its output.

Read
address

Instruction

Instruction
memory

Fig: A ponion of the datapath used for fetching instructions and incrementing
the program counter
Creating a Single Datapath:

PC Read
addo-ess
Read
register I Read 11.t«nV.
I
Read data 1
register 2
lllltruction
Wnte Registers Read Read
Instruction regisler data 2 data
memory
Wnte
data
Wnte Data
data memory

16 Merr

Fig: The simple datapath for the core MIPS architecture combines the
elements required by different instruction classes
This datapath can execute the basic instructions (load-store word, ALU operations, and
branches) in a single clock cycle.
The operations of arithmclic-logical (or R-typc) instructions and the memory instructions
datapath arc quite similar. The key differences arc the following:
• The arithmetic-logical instructions use the ALU, with the inputs coming from the two
registers. The memory instructions can also use the A LU to do the address calculation,
although the second input is the sign-extended 16-bit off set field from the instruction.
• The value stored into a destination register comes from the ALU (for an R-type instruction)
or the memory ( for a load) .
••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••••

.
Control Implementation scheme:
Control unit takes input from

. o the instruction opcode bits

Control unit generates
o ALU control input
o write enable (possibly, read enable also) signals for each storage clement

. o selector controls for each multiplexor

Plan to control ALU: main control sends a 2-bit ALUOp control field to the ALU control.
Based on ALUOp and funct field of instruction 1he ALU control generates the 4-bit ALU
control field. 8
 2
• ALU control
field
Fune-
tion
4
ALUOp To 0000 and
Main ALU
Control ControJ,-"'l"t't:ti--"':-+ ALU 0001 or
control 0010 add
input 0110 sub
0111 sit
6

Instruction

I
funct field

• ALU must perform

o add for load/stores (ALUOp 00)
o sub for branches (ALUOp OI)
o one of and, or, add, sub, sit for R-type instructions, depending on the instruction's
6-bit funct field (ALUOp I0)
Setting ALU Control Bits:

=t
-
---r
LW 00 load word -,- XXJO()()( add 0010

-
-t-
SW 00 store word XXJO()()( add 0010
Branch equal 01 branch equal -l- XXJO()()( subtract 0110
R-type 10
-t- 100000 add 0010
R-type 10
add
subtract t 100010 subtract
-t
+
0110
R-type 10 AND • 100100 AND + 0000
R-type 10 OR 100101 OR 0001
, R-type 10 set on less than
1
T 101010 1
set on less than 1 0111
The opcode, listed in the first column, determines the setting of the ALUOp bits. All the
encodings are shown in binary. Notice that when the ALUOp code is 00 or 01, the desired ALU
action does not depend on the function code field; in this case, we say that we -don't carel about
the value of the function code, and the funct field is shown as XXXXXX. When the ALUOp value
is 10, then the function code is used to set the ALU control input.

9
 Funct field

0 0
mmmmm
X X X X X
.,

X
+
X 1 X X X X X X 0110
+ +-
1 X X X 0 0 0 0 0010
+-
1 X X X 0 0 1 0 0110
1 X X X 0 1 0 0 0000--i

1 X X X 0 1 0 1 0001
1 X X X 1 0 1 0 0111
Table: The truth table for the 4 ALU control bits (called Operation)
The inputs are the ALUOp and function code field. Only the entries for which the ALU
control is asserted arc shown. Some don't-care entries have been added. For example, the ALUOp
docs not use the encoding 11, so the truth table can contain entries IX and XI, rather than IO and
01. Nole that when the function Ii cld is used, the Ii rsl 2 bits (F5 and F4) of these instructions are
always I0, so they arc don 't-carc terms and arc replaced with XX in the truth table.
Designing the Main Control Unit:
Field 0 rs n rd shamt funct
811 pos,tJOns 31:26 25:21 20:16 15:11 10:6 5:0
type instruct ion

Field
B,t pos,tJons
35 o, 43
31:26
I rs
25:21
I rt
20:16
L address
15:0
b. load or store Instruction

Field
L4 rs rt address
..
B,t positions 31:26 25:21 20:16 15:0

Fig: The three instruction classes (R-type, load and store, and branch)

Opcode: The field that denotes the operation and fonnal of an instruction.
o Observations about MIPS instruction formal
o opcode is always in bits 31-26
o two registers to be read are always rs (bits 25-21) and rt (bits 20-16)
o base register for load/s1orcs is always rs (bits 25-21)
o 16-bit offset for branch equal and load/store is always bits 15-0 destination register
for loads is in bits 20-16 (rt) while for R-1ype instructions ii is in bits 15-11 (rd) (will
require 11111/11p/exor to select)

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Seven Control Signals:
Signal
name Effect when cleaaurtecl Effect when •uartad
RegDst The register desbnabon number for the The register destinat,on number for the Wnte~
Wnte reg,ster comes from the rt field register comes from the rd field (bits 15'.11).
(bits 2016)
RegWnte None The register on the Wnte reg,ster input Is
wntten with the value on the Wnte data input
ALUSrc The second ALU operand comes from the The second ALU operand IS the sign-
second register file output (Read data 2). extended, lower 16 bits of the instruction.
PCSrc The PC is replaced by the output of the The PC is replaced by the output of the adder
adder that computes the value of PC • 4. that computes the branch target

I
MemRead None. Data memory contents designated by the
address input are put on the Read data output
MemWnte None Data memory contents designated by the
address input are replaced by the value on
the Wnle data input

1MemtoReg The value fed to the register Wnte data

input comes from the ALU
The value fed to the register Wnte data 111put
comes from the data memory
When the I-bit control to a two way multiplexor is asserted, the multiplexor selects the
input corresponding to I. Otherwise, if the control is deasserted, the multiplexor selects the Oinput.

--
AL

~--~I -12$-211
Read
PC
---!20-16)

(31-0)
lnslnlelion
memory

Fig:The simple datapath with the control unit 11