Exercise 2

Ain Shams University ECE 316: Digital Circuit Design
Faculty of Engineering Spring 2024
Exercise 2
Static CMOS Combinational Logic

1. [2012] For a CMOS inverter, Wn = 0.1 µm, Ln = Lp = 0.065 µm, µn = 600 cm2/Vs, µp = 300
cm2/Vs, Cox = 0.42 fF/µm2, Vtn = -Vtp = 0.2 V and VDD = 1.2 V.
a. Choose Wp such that tpLH = 0.5 tpHL.
b. What is the value of VM / VDD for the inverter in (a)?
c. Design a CMOS gate implementing the logic function 𝑌 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝐴𝐵 + 𝐶𝐷)𝐸 such that it has
the same worst-case ON resistances as the inverter in (a) and (b).
d. For the gate designed in (c), which input pattern(s) would give the worst and best
equivalent pull-up or pull-down resistance? What are the values of these resistances in
terms of pull-up or pull-down resistance of the CMOS inverter in (a) and (b)?
Hint: Just give one input pattern for each case.
2. [2014]
a. Implement the logic function 𝑂𝑢𝑡 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴𝐵𝐶 + 𝐴̅𝐵 + 𝐵𝐶̅ + 𝐴𝐶 with a static CMOS gate
using the minimum number of transistors possible.
b. Someone claims he has implemented a
static CMOS gate with the circuit shown.
In order to find the problem with this
gate, fill out the “truth table” for the gate,
but with voltages instead of ones and
zeroes. (i.e., Vdd, Gnd, Vth, etc. at 𝑂𝑢𝑡 for
all possible combinations of the inputs A,
B, and C).
c. By adding just one more transistor to the
circuit shown above, fix the circuit so that
it will indeed implement a static gate. What is the logic function of this gate?
3. [2014] The figure shows a logic gate designed using a family called Push-Pull Pass
Transistor Logic (PPL).
a. Determine the logic function of Y and Y .
b. What is the function of this gate?
c. What is the role of transistors Mp and Mn?
d. In your opinion, what are the advantages and disadvantages of PPL gates?
Mp
Mn
Page 1 of 3
4. [2014] A pass-transistor network is shown. Assume
that inputs A and B are ideal voltage sources.
VDD=2.5V. VTN=-VTP=0.6V. The gate capacitances
are constant and equal to 4fF, and all drain/source
capacitances are equal to 2 fF (all these capacitances
can be considered as capacitances to ground). The
load capacitor connected to the output is CL=10fF.
The equivalent resistance of an NMOS transistor
with W/L=1 is 15kΩ, while the equivalent resistance of a PMOS with W/L=1 equals 50 kΩ.
The NMOS transistors have W/L=2 and the PMOS transistors have W/L=4.
a. For all possible combinations of A and B find the output voltage level.
b. What is the logic function Y=f(A,B)?
c. Find the propagation delay when B=0, and A switches instantaneously from VDD to 0.
5. [2015] For the circuit shown in the figure:

a. Write a Boolean expression for the logic
function F in terms of inputs A, B, C, and
D.
b. Implement the circuit in the figure using
static CMOS circuits for the individual
logic gates. Be sure to label all inputs,
outputs, and other circuit nodes.
c. Design a static CMOS circuit that implements F which consists of a single multiple-
input CMOS logic gate and a static CMOS inverter.
d. Size your circuit in c such that the worst-case resistance of the gates is equal to a
reference inverter of ratio N:P = 1:2.
6. [2015]
a. Simplify the following equation to have only A, B, C, D
and E as inputs (i.e., with no inverted inputs). 𝑌 =
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴𝐵𝐶𝐸 + 𝐴𝐵𝐶̅ 𝐸 + 𝐴𝐶𝐷𝐸 + 𝐴̅𝐶𝐷𝐸
b. Implement the equation 𝑌 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅𝐴(𝐵𝐶 + 𝐷𝐸) using
complementary CMOS.
c. For the logic gate shown, size the devices so that the
output resistance (R) is the same as that of an inverter with
an NMOS W/L = 1 and PMOS W/L = 2. Use this gate for
the rest of the problem.
d. Which input pattern(s) would give the worst and best
equivalent pull-up or pull-down resistance? (Give all
possible patterns)
e. What are the values of the equivalent resistance in terms of R for the patterns ABCDE
= 00000, 01110, 11100, and 11111?
f. If P(A=1) = P(B=1) = P(C=1) = P(D=1) = P(E=1) = 0.5, determine the power dissipation
in the logic gate. Assume VDD=1.2 V, CL=15 fF and fclk=600 MHz. Hint: P(L and M)
= P(L).P(M) and P(L or M) = P(L)+P(M)-P(L).P(M)
g. What are the parasitic delay of the gate and the logical effort of the 5 inputs?
Page 2 of 3
7. [2015] Given the Boolean expression 𝑌 = 𝐴̅𝐵𝐶 + 𝐴𝐵̅ 𝐶 + 𝐴𝐵𝐶̅ + 𝐴̅𝐵̅ 𝐶̅ and knowing that
the inputs and their complements are available:
a. Draw the schematic of a static CMOS circuit that implements Y.
b. Draw the schematic of a PTL circuit that implements Y.
c. Compare between the two in terms of speed, area, power, and noise margin.
8. [2015] The figure shows a logic gate designed using a special PTL logic family.
a. Determine the logic function of Y.
b. What is the function of this gate?
c. What is the role of transistors Mp?
d. In your opinion, what are the advantages
and disadvantages of this gate?
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Ain Shams University ECE 316: Digital Circuit Design

Faculty of Engineering Spring 2024

Static CMOS Combinational Logic

5. [2015] For the circuit shown in the figure:

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