Shreeyash College of Engineering and Technology (Polytechnic), Chh. Sambhajinagar Micro-Project
Shreeyash College of Engineering and Technology (Polytechnic), Chh. Sambhajinagar Micro-Project
Shreeyash College of Engineering and Technology (Polytechnic), Chh. Sambhajinagar Micro-Project
MICRO-PROJECT REPORT
Seal of Institute
ACKNOWLEDGEMENT
We wish to express our profound gratitude to our guide Prof. M. B. Chavan who
guided us endlessly in framing and completion of Micro-Project. He / She guided
us on all the main points in that Micro-Project. We are indebted to his / her
constant encouragement, cooperation and help. It was his / her enthusiastic
support that helped us in overcoming of various obstacles in the Micro-Project.
We are also thankful to our Principal, HOD, Faculty Members and
classmates for extending their support and motivation in the completion of this
Micro-Project.
1) Rathod Bajirao Bandu EN. NO.2210920291
2) Chavan Dhiraj Sanjay EN. NO.2210920252
3) Jadhav Ranjit Sunil EN. NO.2210920268
4) Rathod Dinesh Mansing EN. NO.2210920293
5) Chavan Rahul Rohidas EN. NO.23511510452
Annexure-1
Micro-Project Proposal
(Format or Micro-Project Proposal about1-2pages)
2. Circuit Design Proficiency: Learners will enhance their ability to design and analyze
simple digital circuits by creating a half adder circuit using logic gates.
4. Critical Thinking and Analysis: Participants will engage in critical analysis of the
functionality and efficiency of the half adder circuit, evaluating its performance in terms
of speed, power consumption, and reliability.
5. Proposed Methodology
2. Component Selection: Identify and gather the necessary components, including logic
gates (such as AND, OR gates), breadboard, wires, and power supply.
3. Circuit Design: Design the half adder circuit on the breadboard based on the logic
gate configurations required for adding two binary digits.
5. Testing and Verification: Verify the functionality of the half adder circuit by
inputting various combinations of binary digits and observing the outputs.
7. Documentation: Document the methodology, circuit diagram, test results, and any
observations made during the project for future reference and learning.
Annexure-
4.0 Action Plan
Name of
Sr. Planned Planned Responsible
Details of activity
No. Week Start Finish Team Members
date date
1 1 &2 Discussion & Finalization Bajirao Rathod
of Topic
2 3 Preparation of the Abstract Dhiraj Chavan
3 4 Literature Review Dinesh Rathod
4 5 Submission of Microproject Rahul chavan
Proposal ( Annexure-I)
5 6 Collection of information about
Topic
6 7 Collection of relevant content / Dinesh Rathod
materials for the execution
of Microproject.
7 8 Discussion and submission Rahul chavan
of outline of the
Microproject.
8 9 Analysis / execution of Dinesh Rathod
Collected data / information and
preparation of Prototypes /
drawings / photos / charts /
graphs / tables / circuits /
Models
/ programs etc.
9 10 Completion of Contents Bajirao Rathod
of Project Report
10 11 Completion of Weekly Dhiraj chavan
progress Report
11 12 Completion of Project Report ( Rahul Chavan
Annexure-II)
12 13 Viva voce / Delivery Bajirao Rathod
of Presentation
5.0 Resources Required (major resources such asraw material, some machining
facility, software etc.)
Micro-Project Report
Format for Micro-Project Report (Minimum 4 pages)
Title of Micro-Project:-
1. Online Tutorials and Guides: Websites like Electronics Tutorials (www.electronics-tutorials.ws) andAll
About Circuits (www.allaboutcircuits.com) offer detailed tutorials and guides on digital logic circuits,
including half adders, suitable for beginners.
2. Academic Papers and Journals: Research articles in journals like IEEE Transactions on Computersand
IEEE Transactions on Circuits and Systems may delve into advanced topics related to half adders, providing
insights into cutting-edge research and applications.
5.0 Actual Methodology Followed (Write step wise work done, data collected and its analysis
(if any).The contribution of individual member may also be noted.)
An adder is a digital logic circuit in electronics that is extensively used for the addition of
numbers. In many computers and other types of processors, adders are even used to calculate
addresses and related activities and calculate table indices in the ALU and even utilized in other
parts of the processors. These can be built for many numerical representations like excess-3 or
binary coded decimal. Adders are basically classified into two types: Half Adder and Full Adder
Half Adder
The half adder circuit has two inputs: A and B, which add two input digits and generates a carry and a sum.
So, coming to the scenario of half adder, it adds two binary digits where the input bits are termed as augend and
addend and the result will be two outputs one is the sum and the other is carry. To perform the sum operation,
OR is applied to both the inputs, and AND gate is applied to both inputs to produce carry
The carry output is 0 unless both inputs are 1. The S output represents the least significant bit of the sum.
The simplified Boolean functions for the two outputs can be obtained directly from the truth table. The
simplified sum of products expressions are
S = x y + xy
C = xy
Full Adder
This adder is difficult to implement when compared to half-adder
The difference between a half-adder and a full-adder is that the full-adder has three inputs and two outputs,
whereas half adder has only two inputs and two outputs. The first two inputs are A and B and the third
input is an input carry as C-IN. When a full-adder logic is designed, you string eight of them together to
create a byte-wide adder and cascade the carry bit from one adder to the next.
A full adder is a fundamental building block in digital electronics used to perform binary addition of three
input bits: two operands (A and B) and a carry-in (Cin) from the previous stage. It produces twooutputs: the
sum (S) and the carry-out (Cout) for the next stage. The truth table for a full adder enumerates all possible
combinations of inputs and their corresponding outputs, aiding in its design and analysis.
The circuitry of a full adder typically consists of two half adders and an additional OR gate. The firsthalf
adder computes the sum of A and B inputs, while the second half adder calculates the sum of thefirst half
adder's output and the carry-in input. The OR gate combines the carry-out outputs from both half adders to
produce the final carry-out (Cout) of the full adder.
Full adders are crucial components in arithmetic units of digital systems, enabling the addition of multi-bit
numbers. They are utilized in applications such as microprocessors, arithmetic logic units (ALUs), and data
processing circuits. Understanding and implementing full adders are essential skills for students and
professionals in fields like electrical engineering, computer science, and digital design.
6.0 Actual Resources Used
sr.
Name of Resource/material Specifications Qty Remarks
No.
1 Google - 01 -
Youtube - 01 -
2
Refference Book - 01 -
3
2. Truth Table Verification: Verification of the half adder's functionality through a truth table.
The truth table illustrates all possible combinations of input values (A and B) and the
corresponding outputs (S and Cout), ensuring that the circuit operates correctly according to
its logic.
8.0 Skill Developed/Learning outcome of this Micro-Project
1. Understanding of Digital Logic: Participants gain a deeper understanding of digital logic principles,
including binary addition, Boolean algebra, and logic gate operations.
2. Circuit Design Proficiency: Learners enhance their ability to design and implement basic digital circuits
by constructing a half adder circuit using logic gates.
3. Problem-Solving Skills: Engaging in troubleshooting activities during the construction and testing phases
helps develop problem-solving skills necessary for identifying and resolving issues in digital circuits.
(A) Process and Product Assessment (Convert Below total marks out of 6Marks)
1 Relevance to the course
2 Literature
Review/information
collection
3 Completion of the Target
as Per project proposal
4 Analysis of Data and
representation
5
Quality of
Prototype/Model
6 Report Preparation
(B) Individual Presentation/Viva(Convert Below total marks out of 4Marks)
7 Presentation
8
Viva
(A) (B)
Process and Product Individual Presentation/ Total Marks
Assessment (6 Viva (4 marks) 10
marks)