Adf 4377

Data Sheet
ADF4377
Microwave Wideband Synthesizer with Integrated VCO
FEATURES GENERAL DESCRIPTION

► Output frequency range: 800 MHz to 12.8 GHz The ADF4377 is a high performance, ultralow jitter, dual output
► Jitter = 18 fsRMS (integration bandwidth: 100 Hz to 100 MHz) integer-N phased locked loop (PLL) with an integrated voltage con-
► Jitter = 27 fsRMS (ADC SNR method) trolled oscillator (VCO) ideally suited for data converter and mixed
signal front end (MxFE) clock applications. The high performance
► Wideband noise floor: −160 dBc/Hz at 12 GHz
PLL has a figure of merit of −239 dBc/Hz, ultralow 1/f noise, and
► PLL specifications a high phase frequency detector (PFD) frequency that can achieve
► −239 dBc/Hz: normalized in-band phase noise floor ultralow in-band noise and integrated jitter. The fundamental VCO
► −147 dBc/Hz: normalized in-band 1/f noise and output divider of the ADF4377 generate frequencies from 800
MHz to 12.8 GHz. The ADF4377 integrates all necessary power
► Phase detector frequency up to 500 MHz supply bypass capacitors, saving board space on compact boards.
► Reference input frequency up to 1000 MHz For multiple data converter and MxFE clock applications, the
ADF4377 simplifies clock alignment and calibration routines re-
► Typical spurious fPFD: −95 dBc at fOUT = 12 GHz quired with other clock solutions by implementing the automatic
► Reference input to output delay specifications reference to output synchronization feature, the matched reference
► Device-to-device standard deviation: 3 ps
to output delays across process, voltage, and temperature feature,
and the less than ±0.1 ps, jitter free reference to output delay
► Temperature coefficient: 0.03 ps/°C adjustment capability feature.
► Adjustment step size: < ±0.1 ps These features allow for predictable and precise multichip clock and
system reference (SYSREF) alignment. JESD204B and JESD204C
► Multichip output phase alignment Subclass 1 solutions are supported by pairing the ADF4377 with
► 3.3 V and 5 V power supplies an integrated circuit (IC) that distributes pairs of reference and
► 7 mm × 7 mm 48-lead LGA SYSREF signals.
APPLICATIONS
► High performance data converter and MxFE clocking
► Wireless infrastructure (MC-GSM, 5G)
► Test and measurement
FUNCTIONAL BLOCK DIAGRAM
Figure 1.
Rev. 0
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Data Sheet ADF4377
TABLE OF CONTENTS
Features................................................................ 1 Reference Source Considerations................... 32

Applications........................................................... 1 Output Phase Noise Characteristics................ 33
General Description...............................................1 Power-Up and Initialization Sequence............. 34
Functional Block Diagram......................................1 Power Supply and Bypassing...........................34
Specifications........................................................ 3 Design and Programming Example 1:
Serial Interface Timing Characteristics...............7 Single ADF4377............................................. 35
Absolute Maximum Ratings...................................9 Aligning Multiple ADF4377 Output Phases...... 39
Transistor Count.................................................9 Design Example 2: JESD204B/C Multichip
Thermal Resistance........................................... 9 Clock and SYSREF Alignment....................... 40
Electrostatic Discharge (ESD) Ratings...............9 ADC Clock and Jitter Considerations............... 43
ESD Caution.......................................................9 Measuring Differential Spurs With A Single-
Pin Configuration and Function Descriptions...... 10 Ended Test Instrument................................... 46
Typical Performance Characteristics................... 12 Application Circuits...........................................46
Theory of Operation.............................................21 Register Map....................................................... 48
Introduction.......................................................21 Register Details................................................ 49
Output Frequency.............................................22 Outline Dimensions............................................. 79
Circuit Description............................................ 22 Ordering Guide.................................................79
Applications Information...................................... 32 Evaluation Boards............................................ 79
Loop Filter Design............................................ 32
REVISION HISTORY
10/2022—Revision 0: Initial Version
analog.com Rev. 0 | 2 of 79

Data Sheet ADF4377
SPECIFICATIONS
3.3 V Supply Group 1 pins voltage (V3.3V_1) = 3.3 V Supply Group 2 pins voltage (V3.3V_2) = 3.15 V to 3.45 V, VV5_VCO = VV5_CP = VV5_CAL =
4.75 V to 5.25 V, all voltages are with respect to GND, TA = −40°C to +105°C, operating temperature range, unless otherwise noted.
Table 1.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments
REFERENCE INPUTS (REFP, REFN)
Input Frequency fREF 10 1000 MHz
Input Signal Level VREF 0.5 2.6 V p-p Refer to Figure 61
Minimum Input Slew Rate 100 V/μs
Input Duty Cycle 50 %
Self-Bias Voltage 1.85 V
Input Resistance 3 kΩ Differential
Input Capacitance 1 pF Differential
Input Current −2 μA
Reference Peak Detector
Input Frequency 10 1000 MHz
Minimum Input Signal Detected (REF_OK Bit = 1) 200 mV p-p fREF = 100 MHz, single-ended sine wave
Maximum Input Signal Not Detected (REF_OK Bit = 160 mV p-p fREF = 100 MHz, single-ended sine wave
0)
REFERENCE DIVIDER 1 63 All integers included
REFERENCE DOUBLER
Input Frequency 10 250 MHz EN_RDBLR = 1
PHASE/FREQUENCY DETECTOR (PFD)
Input Frequency fPFD 3 500 MHz
CHARGE PUMP (CP)
Output Current Range ICP 0.79 to mA Set by CP_I bit fields
11.1
Output Current Source/Sink Accuracy ±2 % All CP_I bit field settings, VCP = VV5_CP/2
Output Current Source/Sink Matching ±2 % All CP_I bit field settings, VCP = VV5_CP/2
Output Current vs. Output Volt Sensitivity 0.2 %/V VCP1
Output Current vs. Temperature 280 ppm/°C VCP = VV5_CP/2
Output High-Z Leakage Current −0.01 μA Minimum ICP, VCP1
−0.3 μA Maximum ICP, VCP1
VCO
Frequency Range fVCO 6.4 12.8 GHz
Tuning Sensitivity KVCO 0.75 to %Hz/V KVCO2, 3
1.25
VCO Calibration Frequency fDIV_RCLK 125 MHz Must set DCLK_MODE = 1, when fDIV_RCLK >
80 MHz
FEEDBACK DIVIDER (N) AND CLOCK OUTPUT
DIVIDER (O)
N 2 4095 All integers included
O 1 8 1, 2, 4, 8
CLOCK OUTPUTS (CLK1P and CLK1N, CLK2P and Differential termination = 100 Ω for all clock
CLK2N) output specifications unless noted
Output Frequency fOUT 0.8 12.8 GHz
Output Differential Voltage VOD 320 mV VOH − VOL measurement across a differential
pair with output driver not toggling and
CLKOUT1_OP = CLKOUT2_OP = 0
420 mV VOH − VOL measurement across a differential

Data Sheet ADF4377
SPECIFICATIONS
Table 1.
Output Resistance 100 Ω Differential
Output Common Mode VCLK – 1.2 V
× VOD
Output Rise Time tR 15 ps 20% to 80%, CLKOUT1_OP = CLKOUT2_OP
=1
Output Fall Time tF 15 ps 80% to 20%, CLKOUT1_OP = CLKOUT2_OP
=1
Output Duty Cycle 50 %
Skew, CLK1P to CLK2P ±0.5 ps
REFERENCE INPUT TO OUTPUT DELAY Device setup4 for all delay specifications
unless noted, measure rising reference edge
at REFP input to rising edge at CLK1P output
Propagation Delay Temperature Coefficient tPD-TC 0.03 ps/°C REF_SEL = 0
Propagation Delay tPD 104 ps fOUT = 12 GHz, fREF = 200 MHz, fPFD = 200
MHz, R_DIV = 1, REF_SEL = 0
112 ps fOUT = 6 GHz, fREF = 200 MHz, fPFD = 200
110 ps fOUT = 1.6 GHz, fREF = 200 MHz, fPFD = 200
MHz, EN_RDBLR = 1, REF_SEL = 0
N_DEL, R_DEL Step Size 1 ps
N_DEL Range 110 ps N_DEL = 127, R_DEL = 0
R_DEL Range 127 ps N_DEL = 0, R_DEL = 127
LOGIC INPUTS (CSB, SCLK, SDIO, ENCLK1, and
ENCLK2 )
Input High Voltage VINH 1.2 V
Input Low Voltage VINL 0.6 V
Input Current IIH/IIL ±1 µA
Input Capacitance (CSB, SCLK, ENCLK1, ENCLK2) CIN 1 pF
SDIO CIN-SDIO 2 pF
LOGIC INPUT (CE Pin)
Input High Voltage VINH-CE 1.8 V
Input Low Voltage VINL-CE 0.8 V
Input Current IIH-CE/IIL-CE ±1 μA
Input Capacitance CIN-CE 1 pF
LOGIC OUTPUTS (SDIO, SDO, LKDET, MUXOUT)
Output High Voltage (1.8 V Mode) VOH 1.5 1.8 V IOH = 500 μA, 1.8 V output selected (default
setting)
Output High Voltage (3.3 V Mode) VOH-3V V3.3V − 0.4 IOH = 500 μA, 3.3 V output selected, set by
voltage on V3_LDO pin
Output Low Voltage VOL 0.4 V IOL = 500 μA
SDO High-Z Leakage IZH/IZL ±1 μA

Data Sheet ADF4377
SPECIFICATIONS
Table 1.
POWER SUPPLIES Device setup5 for all supply current
specifications, unless noted
V5_VCO Supply Range VV5_VCO 4.75 5 5.25 V
V5_CAL Supply Range VV5_CAL 4.75 5 5.25 V
V5_CP Supply Range VV5_CP 4.75 5 5.25 V
V3.3V_1 Supply Range V3.3V_1 3.15 3.3 3.45 V 3.3 V Power Supply Group 1 (V3_LS,
V3_LDO, V3_REF, V3_PFD, V3_NDIV, V3_IN)
V3.3V_2 Supply Range V3.3V_2 3.15 3.3 3.45 V 3.3 V Power Supply Group 2 (V3_CLK1,
V3_CLK2, V3_VCO, V3_CLKDIV)
V5_VCO Supply Current IV5_VCO 90 135 mA fOUT = 12.8 GHz
170 220 mA fOUT = 6.4 GHz, CLKOUT_DIV = 0
V5_CAL Supply Current IV5_CAL 50 160 μA
8 mA During VCO calibration
V5_CP Supply Current IV5_CP 55 65 mA CP current (ICP) = 11.1 mA, CP_I = 15
26 mA ICP = 0.79 mA, CP_I = 0
55.2 mA CP_I = 15, EN_BLEED = 1, BLEED_I[1:0] =
512
V3.3V_1 Supply Current I3.3V_1 173 200 mA
173 mA R_DEL = 127
176 mA REF_SEL = BST_REF = FILT_REF = 1
173 mA PD_RDET = 1
189 mA During VCO calibration, EN_DRCLK =
EN_DNCLK = EN_ADC_CLK = 1
V3.3V_2 Supply Current I3.3V_2 195 mA CLKOUT1_OP = CLKOUT2_OP = 0,
CLKOUT_DIV = 3
169 mA CLKOUT1_OP = CLKOUT2_OP = 0
197 mA CLKOUT1_OP = CLKOUT2_OP = 3,
139 160 mA ENCLK2 = low
Typical Power Dissipation PDIS 1.75 to 1.9 W ENCLK2 = low, V3.3V_1 = V3.3V_2 = 3.3 V,
VV5_VCO = 5 V, VCO Core 2 and Core 3
1.95 to W ENCLK2 = low, V3.3V_1 = V3.3V_2 = 3.3 V,
2.15 VV5_VCO = 5 V, VCO Core 0 and Core 1
Typical Power Down Current
3.3 V Supplies 11 15 mA PD_ALL = 1, I3.3V_1 + I3.3V_2
5 V Supplies 350 750 μA PD_ALL = 1, IV5_VCO + IV5_CAL + IV5_CP
Typical Disable Current
3.3 V Supplies 0.1 1.5 mA CE = low, I3.3V_1 + I3.3V_2
5 V Supplies 350 750 μA CE = low, IV5_VCO + IV5_CAL + IV5_CP
CLOCK OUTPUT NOISE CHARACTERISTICS
12 GHz Output Frequency Device setup6, fOUT = 12 GHz
Phase Noise Floor −160 dBc/Hz
RMS Jitter
12 kHz to 20 MHz Integration 17.6 fsrms
100 Hz to 100 MHz Integration 18 fsrms
Equivalent ADC SNR Method7 27 fsrms
Phase Noise Floor −159.5 dBc/Hz
RMS Jitter

Data Sheet ADF4377
SPECIFICATIONS
Table 1.
100 Hz to 100 MHz Integration 18.7 fsrms
RMS Jitter
12 kHz to 20 MHz Integration 18 fsrms
Phase Noise Floor −163 dBc/Hz
RMS Jitter
RMS Jitter
1.5 GHz Output Frequency Device setup6, fOUT = 1.5 GHz
RMS Jitter
Normalized In-Band Phase Noise Floor8 LNORM −239 dBc/Hz
Normalized 1/f Phase Noise Floor8 L1/f −287 dBc/Hz Normalized to 1 Hz
L1/f_1G_10k −147 dBc/Hz Normalized to 1 GHz at 10 kHz offset
Spurious
fREF −105 dBc LOCKED bit = 1, fREF = 100 MHz, fPFD = 200
MHz, fOUT = 12 GHz
fPFD −95 dBc LOCKED bit = 1, fREF = 100 MHz, fPFD = 200
MHz, fOUT = 12 GHz

Data Sheet ADF4377
SPECIFICATIONS
Table 1.
TEMPERATURE SENSOR (ADC)
ADC Clock Frequency fADC_CLK 400 kHz ADC clock divider output
ADC Clock Divider Frequency fADC_CLKDIV 125 MHz ADC clock divider input
Resolution 8 Bits
1 1.2 V < VCP < 3.4 V.

2 Valid for 1.60 V ≤ VVTUNE ≤ 2.85 V with device calibrated after a power cycle or software power-on reset.
3 Based on characterization.
4 Device setup: fREF = 200 MHz, fPFD = 200 MHz, fOUT = 3000 MHz, ENCLK1 = ENCLK2 = CE = HIGH. Bit fields: R_DEL= 0, N_DEL = 0, CP_I = 15, CLKOUT1_OP = 1,
CLKOUT2_OP = 1, REF_SEL = 0, EN_BLEED = 0, PD_RDET = 0, PD_ADC = 0, PD_LD = 0, LOCKED = 1.
5 Device Setup: fREF = 100 MHz, fPFD = 200 MHz, fOUT = 12.8 GHz, ENCLK1 = ENCLK2 = CE = HIGH. Bit fields: R_DEL= 0, N_DEL = 0, CP_I = 15, CLKOUT1_OP = 1,
CLKOUT2_OP = 1, REF_SEL = 0, EN_BLEED = 0, PD_RDET = 0, PD_ADC = 0, PD_LD = 0, LOCKED = 1, EN_DNCLK = EN_DRCLK = EN_ADC_CLK = 0.
6 Device Setup: fREF = 1000 MHz, fPFD = 500 MHz, ENCLK1 = ENCLK2 = CE = HIGH. Bit fields: R_DEL = 0, N_DEL_0, CP_I = 15, CLKOUT1_OP = 1, CLKOUT2_OP = 1,
REF_SEL = 0, EN_BLEED = 0, PD_RDET = 0, PD_ADC = 0, PD_LD = 0, LOCKED = 1, the reference oscillator is the 0-CEGM-058AWEL-R-1GHz from NEL Frequency
Control.
7 Phase integration range 1 kHz to fOUT produces the same result as when clocking an ADC.
8 ™
Refer to Equation 18 through Equation 22. These values are modeled in ADIsimPLL .
SERIAL INTERFACE TIMING CHARACTERISTICS

V3.3V_1 = V3.3V_2 = 3.15 V to 3.45 V, VV5_VCO = VV5_CP = VV5_CAL = 4.75 V to 5.25 V, all voltages are with respect to GND, TA = −40°C to
+105°C, operating temperature range, unless otherwise noted.
Table 2.
SERIAL INTERFACE (CSB, SCLK, SDIO, SDO) See Figure 2, Figure 3, and Figure 4
SCLK Frequency fSCLK 65 MHz fSCLK = 1/tSCLK
SCLK Pulse Width High tHIGH 7.6 ns
SCLK Pulse Width Low tLOW 7.6 ns
SDIO Setup Time tDS 3 ns
SDIO Hold Time tDH 3 ns
SCLK Fall Edge to SDIO Valid Prop Delay tACCESS_SDIO 7.6 ns
SCLK Fall Edge to SDO Valid Prop Delay tACCESS_SDO 7.6 ns
CSB Rising Edge to SDIO High-Z tZ 7.6 ns
CSB Falling Edge to SCLK Rise Setup Time tS 3 ns
SCLK Rising Edge to CSB Rise Hold Time tH 3 ns
Timing Diagrams
Figure 2. Write Timing Diagram

Data Sheet ADF4377
SPECIFICATIONS
Figure 3. 3-Wire Read Timing Diagram (SDO_ACTIVE = 0)
Figure 4. 4-Wire Read Timing Diagram (SDO_ACTIVE = 1)

Data Sheet ADF4377
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted. ELECTROSTATIC DISCHARGE (ESD) RATINGS

Table 3. Absolute Maximum Ratings The following ESD information is provided for handling of ESD-sen-
Parameter Rating sitive devices in an ESD protected area only.
V3.3V_1 (V3_LS, V3_LDO, V3_REF, V3_PFD, −0.3 V to +3.6 V Human body model (HBM) per ANSI/ESDA/JEDDEC JS-001.
V3_NDIV) to GND
Charged device model (CDM) per ANSI/ESDA/JEDEC JS-002.
V3.3V_2 (V3_VCO, V3_CLKDIV, V3_CLK1, −0.3 V to +3.6 V
V3_CLK2) to GND
ESD Ratings for ADF4377
V5V (V5_CAL, V5_VCO, V5_CP) to GND −0.3 V to +5.5 V
Voltage on CP Pin −0.3 V to VV5_CP + 0.3 V Table 5. ADF4377, 48-Lead LGA
Digital Outputs (MUXOUT, LKDET, SDO, SDIO) 5 mA ESD Model Withstand Threshold (V) Class
CLK1P, CLK1N, CLK2P, CLK2N Maximum (GND − 0.3 V,
HBM 3500 2
V3.3V_2 − 1.2 V) to V3.3V_2 +
0.3 V CDM 1250 C3
REFP, REFN −0.65 V to V3.3V_1 + 0.65 V
ESD CAUTION
Voltage on All Other Pins −0.3 V to V3.3V_1 + 0.3 V
REFP to REFN, when V3.3V_1 > 3 V ±1.35 V ESD (electrostatic discharge) sensitive device. Charged devi-
Operating Junction Temperature Range1 −40°C to +125°C ces and circuit boards can discharge without detection. Although
Storage Temperature Range −40°C to +125°C this product features patented or proprietary protection circuitry,
Maximum Junction Temperature 125°C damage may occur on devices subjected to high energy ESD.
Reflow Soldering Therefore, proper ESD precautions should be taken to avoid
performance degradation or loss of functionality.
Peak Temperature 260°C
Time at Peak Temperature 30 s
1 Device is guaranteed to meet the specified performance limits over the full
operating junction temperature range.
Stresses at or above those listed under Absolute Maximum Ratings

may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other
conditions above those indicated in the operational section of this
specification is not implied. Operation beyond the maximum operat-
ing conditions for extended periods may affect product reliability.
TRANSISTOR COUNT
The transistor count for the ADF4377 is 114258 (CMOS) and 2941
(bipolar).
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to PCB
thermal design is required. θJA is the natural convection, junction
to ambient thermal resistance measured in a one cubic foot sealed
enclosure. θJC is the junction to case thermal resistance.
Table 4. Thermal Resistance
Package θJC-
Type θJA θJC-TOP BOTTOM θJB ΨJT ΨJB Unit
CC-48-6 28.7 25.8 6.3 13.1 2.6 13.7 °C/W
1
1 Test Condition 1: thermal impedance simulated values are based on use of a

4-layer PCB with the thermal impedance paddle soldered to a ground plane.

Data Sheet ADF4377
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions

Pin No. Mnemonic Description
1, 2, 4, 10, 12, GND Negative Power Supply (Ground). These pins must be tied directly to the ground pad.
14, 16, 18, 19,
21, 23, 25, 26,
41, 48
3 V3_NDIV 3.15 V to 3.45 V Positive Power Supply Pin for the PLL Feedback Divider Circuitry. Short this pin to the other pins in 3.3 V Power Supply
Group 1.
5 V3_VCO 3.15 V to 3.45 V Positive Power Supply Pin for the 3.3 V Portion of the VCO Circuitry. Short this pin to the other pins in 3.3 V Power
Supply Group 2.
6 DCLBIAS Do not connect to this pin.
7 VTUNE VCO Tuning Input. This frequency control pin is normally connected to the external loop filter.
8 V5_CAL 4.75 V to 5.25 V Positive Power Supply Pin for VCO Calibration Circuitry. This pin can be shorted to the V5_VCO supply plane.
9 V5_VCO 4.75 V to 5.25 V Positive Power Supply Pin for the 5 V Portion of the VCO Circuitry.
11 V3_CLKDIV 3.15 V to 3.45 V Positive Power Supply Pin for the Output Divider Circuitry. Short this pin to the other pins in 3.3 V Power Supply Group 2.
13 V3_CLK2 3.15 V to 3.45 V Positive Power Supply Pin for the Clock 2 Buffer Circuitry. Short this pin to the other pins in 3.3 V Power Supply Group 2.
15, 17 CLK2N, CLK2P Clock 2 Output Signal. The VCO output divider is buffered and presented differentially on these pins. The outputs have 50 Ω (typical)
output resistance per side (100 Ω differential). The far end of the transmission line is typically terminated with 100 Ω connected across the
outputs. The output amplitude is programmable via the serial port.
20, 22 CLK1N, CLK1P Clock 1 Output Signal. The VCO output divider is buffered and presented differentially on these pins. The outputs have 50 Ω (typical)
output resistance per side (100 Ω differential). The far end of the transmission line is typically terminated with 100 Ω connected across the
outputs. The output amplitude is programmable via the serial port.
24 V3_CLK1 3.15 V to 3.45 V Positive Power Supply Pin for the Clock 1 Buffer Circuitry. Short this pin to the other pins in 3.3 V Power Supply Group 2.
27 LKDET PLL Lock Detect. This output presents the lock status of the PLL. PLL is locked when the LKDET pin is a logic high.
28 ENCLK2 Enable Clock 2 Output Buffer. 1.8 V and 3.3 V compatible CMOS input. When ENCLK1 = high, the CLK2P and CLK2N output buffer is
active. When ENCLK2 = low, the CLK2P and CLK2N output buffer is powered down.
29 ENCLK1 Enable Clock 1 Output Buffer. 1.8 V and 3.3 V compatible CMOS input. When ENCLK1 = high, the CLK1P and CLK1N output buffer is
active. When ENCLK1 = low, the CLK1P and CLK1N output buffer is powered down.
30 V3_LS 3.15 V to 3.45 V Positive Power Supply Pin for the Internal Level Shift Circuitry. Short this pin to the other pins in 3.3 V Power Supply
Group 1.
31 CE Chip Enable. 3.3 V CMOS input. Does not support 1.8 V CMOS levels. This CMOS input enables the device when driven high. A logic low
disables the device, putting the device in a full power-down state, causing the registers to reset. Conversely, the PD_ALL bit powers down
the device, but does not reset the registers.
32 CSB Serial Port Chip Select. 1.8 V and 3.3 V compatible CMOS input. This CMOS input initiates a serial port communication burst when driven
low, ending the burst when driven back high.

Data Sheet ADF4377
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 6. Pin Function Descriptions

Pin No. Mnemonic Description
33 SDIO Serial Data Input/Output. 1.8 V and 3.3 V programmable CMOS input/output. When configured as an input, the serial port uses this CMOS
input for data. In 3-wire readback mode (default mode), this pin outputs data from the serial port during a read communication burst.
34 SCLK Serial Port Clock. 1.8 V and 3.3 V compatible. This CMOS input clocks serial port input data on its rising edge.
35 SDO Optional Serial Data Output. 1.8 V and 3.3 V programmable CMOS output. In 3-wire mode (default mode), this three state CMOS pin
remains in a high impedance state. In 4-wire readback mode, this pin presents data from the serial port during a read communication
burst. When the CS is deasserted, SDO returns to a high impedance. Optionally, attach a resistor of > 200 kΩ to prevent a floating output.
36 V3_LDO 3.15 V to 3.45 V Positive Power Supply Pin for the Internal LDO Circuitry. Short this pin to the other pins in 3.3 V Power Supply Group 1.
37 MUXOUT Internal Device Mux Output. This output pin can be connected to multiple internal nodes for factory test and debug purposes.
38, 39 NC No Connect or GND. These pins are connected internally to ESD diodes.
40 V3_IN 3.15 V to 3.45 V Positive Power Supply. Short this pin to the other pins in 3.3 V Power Supply Group 1.
42, 43 REFP, REFN Reference Input Signal. This differential input is buffered with a delay matched amplifier (DMA) for well controlled reference to output
propagation delays (default mode, REF_SEL = 0). For low slew rate reference input signals, an alternate low noise amplifier (LNA) can
be selected via the serial port (REF_SEL = 1). Reference inputs are self-biased and must be ac-coupled with 1 μF capacitors. Reference
inputs accept differential or single-ended inputs.
44 V3_REF 3.15 V to 3.45 V Positive Power Supply Pin for the PLL Reference Circuitry. Short this pin to the other pins in 3.3 V Power Supply Group 1.
45 V3_PFD 3.15 V to 3.45 V Positive Power Supply Pin for PFD Circuitry. Short this pin to the other pins in 3.3 V Power Supply Group 1.
46 V5_CP 4.75 V to 5.25 V Positive Power Supply Pin for Charge Pump Circuitry. This pin must be isolated from the V5_VCO supply plane.
47 CP Charge Pump Output. This bidirectional current output is normally connected to the external loop filter.
Exposed Pad EP Exposed Pad. Negative power supply (ground). The exposed pad must be soldered directly to the PCB land. The PCB land pattern must
have multiple thermal vias to the ground plane for both low ground inductance and low thermal resistance.

Data Sheet ADF4377
TYPICAL PERFORMANCE CHARACTERISTICS
V3.3V_1 = V3.3V_2 = 3.3 V, V5V = 5 V, all voltages are with respect to GND, TA = 25°C, unless otherwise noted.
Figure 6. Jitter vs. Output Frequency at Various Output Amplitudes Figure 9. Closed Loop Phase Noise at Various Output Amplitudes
Figure 7. Closed Loop Phase Noise at Various Output Frequencies Figure 10. Closed Loop Phase Noise at Various CLKOUT_DIV Settings
Figure 8. Closed Loop Phase Noise at Various Temperatures Figure 11. Closed Loop Phase Noise at Various Power Supply Voltages

Data Sheet ADF4377
Figure 12. Jitter vs. R_DEL, N_DEL Figure 15. Jitter vs. BLEED_I
Figure 13. Closed Loop Phase Noise at Various R_DEL and N_DEL Settings Figure 16. Closed Loop Phase Noise at Various Charge Pump Bleed Delays
Figure 14. Closed Loop Phase Noise at Various Clock Invert Settings Figure 17. Closed Loop Phase Noise at Various Reference Doubler and
Reference Divider Settings

Data Sheet ADF4377
Figure 18. Propagation Delay (tPD) and Propagation Delay Temperature Figure 21. tPD and tPD-TC vs. N_DEL
Coefficient (tPD-TC) vs. R_DEL
Figure 22. tPD and tPD-TC vs. BLEED_I, BLEED_POL = 1

Figure 19. tPD and tPD-TC vs. BLEED_I , BLEED_POL = 0
Figure 23. tPD vs. Temperature, CLKOUT_OP Setting

Figure 20. Delta Propagation Delay (ΔtPD) vs. TA, Temperature, Device
Configuration

Data Sheet ADF4377
Figure 24. Normalized Propagation Delay (tPD) Histogram Figure 27. KVCO at Various Frequencies and Temperatures
Figure 25. tPD vs. Frequency Figure 28. KVCO Percentage at Various Frequencies and Temperatures
Figure 26. Open Loop VCO Phase Noise at Various Frequencies Figure 29. Open Loop VCO Phase Noise at Various Temperatures

Data Sheet ADF4377
Figure 30. Differential Output at 12 GHz Figure 33. Differential Output at 1.5 GHz
Figure 31. Differential Output at 6 GHz

Figure 34. Differential Output vs. Frequency, Temperature
Figure 32. Differential Output at 3 GHz

Figure 35. Differential Output vs. Frequency, Power Supply Voltage

Data Sheet ADF4377
Figure 36. LNORM and L1/f vs. BLEED_I Figure 39. LNORM and L1/f vs. N_DEL, R_DEL
Figure 37. LNORM and L1/f vs. Reference Slew Rate, Reference Amplifier Figure 40. LNORM and L1/f vs. CP_I Setting
Figure 38. LNORM vs. Temperature, Charge Pump Current Figure 41. L1/f vs. Temperature, Charge Pump Current

Data Sheet ADF4377
Figure 42. Reference and PFD Spurious Level at Various Reference Figure 45. Reference and PFD Spurious Level at Various Reference
Frequencies and Reference Amplitudes, EN_RDBLR = 0 Frequencies and Output Frequencies, EN_RDBLR = 1
Figure 43. Reference and PFD Spurious Level at Various Reference Figure 46. 3.3 V Supply Group 1 Current at Various Junction Temperatures
Frequencies and Output Frequencies, EN_RDBLR = 0 and Power Supply Voltages
Figure 44. Reference and PFD Spurious Level at Various Reference Figure 47. 3.3 V Supply Group 2 Current at Various Junction Temperatures
Frequencies and Reference Amplitudes, EN_RDBLR = 1 and Output Settings

Data Sheet ADF4377
Figure 48. 3.3 V Supply Group 2 Current at Various Power Supply Voltages Figure 51. 5 V Delta Supply Current (ΔCURRENT) at Various CP_I Settings
and CLKOUT_DIV Settings
Figure 52. DMA Reference Input Sensitivity at Various Reference

Figure 49. 5 V Supply Current at Various Output Frequencies and Junction Frequencies and Temperatures
Temperatures
Figure 53. LNA Reference Input Sensitivity at Various Reference Frequencies

Figure 50. 5 V Supply Current at Various Output Frequencies and Power and Temperatures
Supply Voltages

Data Sheet ADF4377
Figure 54. Reference Input Signal Detected at Various Reference Frequencies Figure 57. Charge Pump High-Z Current at Various Charge Pump Voltages
and Temperatures and Temperatures
Figure 55. Charge Pump Sink Current Error at Various Charge Pump Figure 58. Charge Pump Source Current Error at Various Charge Pump
Voltages and CP_I Settings Voltages and CP_I Settings
Figure 56. Charge Pump Sink Current Error at Various Charge Pump Figure 59. Charge Pump Source Current Error at Various Charge Pump
Voltages and Temperatures Voltages and Temperatures

Data Sheet ADF4377
THEORY OF OPERATION
the clock output pins (fOUT). The PFD, charge pump, output divider,
INTRODUCTION feedback divider, VCO, and external loop filter forms a feedback
A PLL is a complex feedback system that may conceptually be loop to accurately control the output frequency (see Figure 60). The
considered a frequency multiplier. The system multiplies the refer- reference divider or reference doubler is used to set the frequency
ence input frequency (fREF) and produces a higher frequency on resolution.
Figure 60. PLL Loop Diagram

Data Sheet ADF4377
THEORY OF OPERATION
OUTPUT FREQUENCY
When EN_RDBLR = 0
When the loop is locked, the frequency (fVCO ) (in Hz) produced at
the output of the VCO is determined by the reference frequency
(fREF) and the O, R, and N values given by Equation 1. Refer to
Table 11 and Table 18 for more information.
N×O
fVCO = fREF × R (1)
In the following equation, the PFD frequency (fPFD) produced is Figure 61. Reference Input Stage
given by Equation 2.
fREF A high quality signal must be applied to the REFP and REFN inputs
fPFD = R
(2)
because they provide the frequency reference to the entire PLL.
fVCO may be alternatively expressed as To achieve the in-band phase noise performance of the PLL, apply
a continuous waveform signal or a square wave with a slew rate
fVCO = fPFD × N × O (3) of at least 1000 V/µs. See the Reference Source Considerations
section for more information on reference input signal requirements
The output frequency (fOUT) produced at the output of the output and interfacing.
divider is given by Equation 4.
When the REF_SEL bit is set to 0, the DMA buffer is selected. The
fVCO
fOUT = O
(4) DMA is optimized for high slew rate signals, such as square waves
or higher frequency and higher amplitude sine waves. The DMA
The output frequency resolution (fSTEP) produced by a unit change has a controlled propagation delay from the reference input to clock
in N is given by Equation 5. output, which eases time zero and over temperature multichip clock
fSTEP = fPFD alignment.
(5)
When the REF_SEL bit is set to 1, the LNA is selected. The LNA
When EN_RDBLR = 1 is optimized for low slew rate signals, such as lower frequency or
lower amplitude sine waves.
When the loop is locked, the frequency (fVCO ) (in Hz) produced at
the output of the VCO is determined by the reference frequency The REF_SEL bit must be set correctly to optimize the in-band
(fREF) and the O, D, and N values given by Equation 6. phase noise performance and propagation delay. See Table 7,
Figure 37, and Equation 8 for recommended settings.
fVCO = fREF × D × N × O (6)
Table 7. REF_SEL Programming
When EN_RDBLR = 1, the PFD frequency (fPFD) produced is given REF_SEL Sine Wave Slew Rate (V/µs) Square Wave Optimized tPD
by Equation 7. 0 ≥1500 Preferred Yes
fPFD = fREF × D (7) 1 <1500 Not applicable Not applicable
Equation 3, Equation 4, and Equation 5 for fVCO, fOUT, and fSTEP To calculate the slew rate of sine wave,
remain the same when EN_RDBLR = 1. Slew Rate =2×π×f×V (8)
CIRCUIT DESCRIPTION where:
Reference Input Buffer f = sine wave frequency
The reference frequency of the PLL is applied differentially on V = sine wave amplitude (in VPK)
the REFP pin and REFN pin. These high impedance inputs are The FILT_REF bit controls the low-pass filter of the reference input
self-biased and must be ac-coupled with 1 µF capacitors (see LNA and must be set for sine wave signals based on fREF to limit
Figure 61 for a simplified schematic). Alternatively, the differential the wideband noise of the input reference signal. The FILT_REF bit
inputs may be configured as a single ended input by applying the must be set correctly to reach the LNORM normalized in-band phase
reference frequency at REFP and bypassing REFN to GND with a 1 noise floor. See Table 8 for recommended settings. Square wave
µF capacitor (see Figure 80). inputs must have FILT_REF set to 0.

Data Sheet ADF4377
THEORY OF OPERATION
Table 8. FILT_REF Programming Table 11. EN_RDBLR and R_DIV Programming

FILT_REF Sine Wave fREF Square Wave fREF EN_RDBLR R_DIV R D
0 ≥20 MHz All fREF 1 Not applicable Not applicable 2
1 < 20 MHz Not applicable 0 0 1 Not applicable
0 1 1 Not applicable
The BST_REF bit must be set based on the input signal level
0 … … Not applicable
to prevent the LNA reference input buffer from saturating. The
0 63 63 Not applicable
BST_REF programming is the same whether the input is a sine
wave or a square wave. See Table 9 for recommended settings and
the Applications Information section for programming examples. Reference Delay
Table 9. BST_REF Programming A 7-bit delay, R_DEL, is used to increase the propagation delay
BST_REF Sine Wave VREF from the reference input pins to the clock outputs pins. Use the
R_DEL bits to directly program the reference delay (tRDEL) which
0 ≥ 1.6 V p-p
typically ranges from 0 ps to 127 ps in 1 ps steps (see Figure 63).
1 < 1.6 V p-p
Reference Peak Detector

A reference input peak detection circuit is provided on the REFP
and REFN inputs to detect the presence of a reference signal and
provides the REF_OK status flag available through serial port regis-
ter REG0049. The circuit has hysteresis to prevent the REF_OK
flag from chattering at the detection threshold.
The peak detector approximates an rms detector. Therefore, sine
and square wave inputs give different detection thresholds by a
factor of 4/π. See Table 10 for REF_OK detection values.
Table 10. REF_OK Status Output vs. Reference Input
REF_OK Sine Wave VREF Square Wave VREF
1 ≥200 mV p-p ≥155 mV p-p Figure 63. Typical Reference Delay Step Size vs. R_DEL Register Setting
0 <160 mV p-p <125 mV p-p
INV_CLKOUT, N_DEL, and R_DEL can be used in conjunction to
Reference Divider (R) and Doubler (D) align the multichip output to output skew to within ±0.5 ps. Figure
39 shows that the largest R_DEL settings may increase LNORM by
When the EN_RDBLR bit is set to 1, a frequency multiplier is used 1 dB. INV_CLKOUT does not degrade performance and must be
to double the frequency seen at the PFD. When the EN_RDBLR bit used to adjust for multichip output to output skews greater than a
is set to 0, a 6-bit divider, R_DIV, is used to reduce the frequency quarter of the 1/fOUT period, in lieu of a large N_DEL or R_DEL
seen at the PFD. The reference divide ratio, R, may be set to any value. As a result, the maximum tRDEL adjustment never has to
integer from 1 to 63, inclusive of all the integer divide values. Use be more than a quarter of the 1/fOUT period. See the Aligning Multi-
the R_DIV bits found in REG0012 to directly program the R divide ple ADF4377 Output Phases section for the relationship between
ratio (see Figure 62 and Table 11). See the Output Frequency R_DEL, N_DEL, INV_CLKOUT, BLEED_I bit fields, Bits[9:0], and
section for the relationship between R, D, and the fREF, fPFD, BLEED_POL.
fVCO, and fOUT frequencies. The state of the DCLK_MODE bit is
determined by Table 17. Phase/Frequency Detector (PFD)
The PFD, in conjunction with the charge pump, produces source
and sink current pulses proportional to the phase difference be-
tween the outputs of the reference divider or reference doubler and
feedback divider. This action provides the necessary feedback to
phase-lock the loop, forcing a phase alignment at the inputs of the
PFD. See Figure 64 for a simplified schematic of the PFD.
Figure 62. Reference Divider and Doubler

Data Sheet ADF4377
THEORY OF OPERATION
Table 12. CP Programming

CP_I ICP
14 9.51 mA
15 11.1 mA
Charge Pump Test Mode

When the EN_CPTEST bit is set to 1, the CP_UP bit and
CP_DOWN bit can be programmed to force a constant ICP source
or sink current, respectively, on the CP pin. These bits are com-
monly used as an aid to debug PLL related issues during the
hardware and software development phase of a project. For normal
Figure 64. Simplified PFD Schematic operation, set EN_CPTEST, CP_UP, and CP_DOWN to 0. Refer to
Figure 65 and Table 13.
Charge Pump
Table 13. Charge Pump Debug Functions
The charge pump, controlled by the PFD, forces sink (down) or EN_CPTEST CP_UP CP_DOWN CP Pin State Debug Test
source (up) current pulses onto the CP pin, which must be connect-
1 0 0 High-Z VCO open loop
ed to an appropriate loop filter. See Figure 65 for a simplified
schematic of the charge pump. 1 1 0 ~VV5_CP Charge pump
1 0 1 ~GND output voltage
verification
0 0 0 Normal oper- Not applicable
ation
Charge Pump Bleed Current

A small programmable constant charge pump current, known as
bleed current, can be used to either increase or decrease the
propagation delay from the reference input pins to the clock output
Figure 65. Simplified Charge Pump Schematic
pins.
The output current magnitude (ICP) may be set from 0.79 mA to To enable the bleed current, set the EN_BLEED bit to 1. When
11.1 mA using the CP_I bits. A larger ICP can result in lower the BLEED_POL bit is set to 1, a small constant source current
in-band noise (LNORM) due to the lower impedance of the loop filter is forced onto the CP pin. When the BLEED_POL bit is set to 0,
components. A smaller ICP can result in better spurious perform- a small constant sink current is forced onto the CP pin. Refer to
ance. See Table 12 for programming specifics and the Applications Figure 65.
Information section for information on designing a loop filter.
The bleed current LSB step size is 536 nA. The bleed current delay
Table 12. CP Programming step size (tIDEL-STEP) is a function of the bleed current step size
CP_I ICP (ICP) and fPFD, as shown in Equation 9. Figure 66 provides a quick
0 0.79 mA reference of tIDEL-STEP vs. several common ICP and fPFD values.
1 0.99 mA 536 nA
tIDEL − STEP = ICP × fPFD (9)
2 1.19 mA
3 1.38 mA
4 1.59 mA
5 1.98 mA
6 2.39 mA
7 2.79 mA
8 3.18 mA
9 3.97 mA
10 4.77 mA
11 5.57 mA
12 6.33 mA
13 7.91 mA

Data Sheet ADF4377
THEORY OF OPERATION
both the EN_LOL bit and the EN_LDWIN bit to 1 and presents the
lock detector output on the LKDET pin and the LOCKED bit. The
lock detector output can also be presented on the MUXOUT pin by
programming the MUXOUT bits (see Figure 75). The CMOS_OV bit
determines if the logic high level for the MUXOUT, LKDET, SDO,
and SDIO output pins is 3.3 V or 1.8 V.
The PFD phase difference must be less than the phase difference
lock window time (tLDWIN) for a set number of PFD cycles before the
lock detector output indicates that the PLL has locked. The desired
number of PFD cycles varies if a designer prioritizes lock detect
accuracy or speed. Five loop filter time constants can be used as
an initial estimate of the desired number of PFD cycles, as shown
in Equation 12. The desired number of PFD cycles is set by the
LD_COUNT bits, as shown in Table 14. Refer to Figure 67 and
Figure 66. Bleed Current Delay Step Size Table 15 for more details.
5 × fPFD
Bleed current delay (tIDEL) is determined by tIDEL-STEP, the PFD Cycles = 2 × π × LPBW
(12)
BLEED_POL bit, and BLEED_I bit fields, Bits[9:0]. Refer to Equa-
tion 10 and Equation 11. where LPBW = loop filter bandwidth.
If BLEED_POL = 0, the propagation delay from the REFP and Table 14. LD_COUNT Programming
REFN input pins to the CLKxP and CLKxN output pins increases. LD_COUNT PFD Cycles
Refer to Figure 19. 0 23
tIDEL = tIDEL − STEP × BLD_I (10) 1 32
2 47
where BLD_I represents the decimal value of the BLEED_I bit field, 3 66
Bits[9:0]. 4 95
If BLEED_POL = 1, the propagation delay from the REFP and 5 134
REFN input pins to the CLKxP and CLKxN output pins decreases. 6 191
Refer to Figure 22 7 270
8 383
tIDEL = − tIDEL − STEP × BLD_I (11)
9 542
The maximum tIDEL for proper lock detector functionality is based 10 767
on the LDWIN_PW setting, as shown in Table 16. 11 1085
12 1535
INV_CLKOUT, BLEED_I bit fields, Bits[9:0], and BLEED_POL can
13 2171
be used in conjunction to align the multichip output to output skew
14 3071
to as small as ±0.05 ps (see Equation 9). The largest BLEED_I
bit fields, Bits[9:0] settings may increase LNORM by 1 dB and L1/f 15 4343
by 4 dB, as shown in Figure 36. INV_CLKOUT does not degrade 16 6143
performance and must be used to adjust for multichip output to 17 8687
output skews greater than a quarter of the 1/fOUT period, in lieu 18 12287
of a large BLEED_I bit fields, Bits[9:0] value. As a result, the 19 17376
maximum tIDEL adjustment never needs to be more than a quarter 20 24575
of the 1/fOUT period. See the Applications Information section for the 21 34754
relationship between R_DEL, N_DEL, INV_CLKOUT, BLEED_I bit 22 49151
fields, Bits[9:0], and BLEED_POL. 23 69510
24 98303
Lock Detector 25 139021
The lock detector uses internal signals from the PFD to measure 26 196607
phase coincidence between the output signal of the reference 27 278044
divider and doubler (RCLK) in Figure 62 and the output signal of 28 393215
the feedback divider (NCLK) in Figure 72. It is enabled by setting 29 556090

Data Sheet ADF4377
THEORY OF OPERATION
Table 14. LD_COUNT Programming bit. In most cases, LDWIN_PW must be set to 0. Refer to Table
LD_COUNT PFD Cycles 16 to understand the relationship between the LDWIN_PW bit and
30 786431 maximum allowable tIDEL.
31 1112181 Table 16. Maximum tIDEL
LDWIN_PW tIDEL(MAX)
0 ±150 ps
1 ±250 ps
VCO
The VCO core consists of 4 separate VCOs, each of which uses
256 overlapping bands, which allows the device to cover a wide
frequency range without large VCO sensitivity (KVCO). The output
Figure 67. Lock Detector Timing, Bleed Current Disabled frequency can be further extended by utilizing the output divider.
Table 15. Lock Detector Timing, Bleed Current Disabled
Absolute Phase
Region Difference at PFD Lock Detector State
1 > tLDWIN Low
2 < tLDWIN Low, counts PFD cycles
3 ~0
4 ~0 High, ≥ desired PFD cycle count
5 < tLDWIN High
6 > tLDWIN Low (immediately)
When the charge pump bleed current is enabled, a phase offset is

applied to the PFD inputs. This phase offset (tIDEL) is proportional Figure 69. VCO and Clock Output Divider
to the amount of bleed current programmed in Equation 10 and
Equation 11. Region 3 and Region 4 in Figure 67 and Figure 68 The correct register values for the VCO_CORE, VCO_BAND, and
highlight the PFD phase difference that the PLL settles to when the VCO_BIAS settings are determined by performing a VCO calibra-
charge pump bleed current is disabled or enabled, respectively. tion. See the VCO Calibration section for more information. After
a VCO calibration is performed for a specific device and frequen-
cy, the VCO_CORE, VCO_BAND, and VCO_BIAS values can be
recorded. These recorded values may be programmed manually on
subsequent power ups when the same device and frequency are
used, thereby avoiding the VCO calibration time.
VCO Calibration
A VCO calibration is required to select the correct VCO core, band,
and bias settings for a specific VCO frequency. This procedure
Figure 68. Lock Detector Timing, Bleed Current Enabled
assumes that the device is powered up, the desired reference
For proper operation of the lock detector, the absolute value of tIDEL frequency is present on the REFP and REFN pins, and all other
must be less than tLDWIN. The user sets the phase difference lock registers are programmed correctly. Figure 70 and Figure 71 are
window time (tLDWIN) for a valid lock condition with the LDWIN_PW provided as visual aids for this procedure.

Data Sheet ADF4377
THEORY OF OPERATION
Figure 70. VCO Calibration Dividers
Figure 71. VCO Calibration Block
To perform a VCO calibration, set up several registers as outlined in

the following procedure: ADC_CLK_DIV > Ceiling
1. Set register bits based on the RCLK column in Table 22.
fDIV_RCLK
(16)
2. Set DCLK_DIV1 = 1. Set CAL_CT_SEL, DCLK_DIV2, and −2
400 kHz
DCLK_MODE to the values in Table 17. Record fDIV_RCLK for 4
later use.
3. Calculate and set the minimum values for the 5. Set the N_INT bit fields, Bits[11:0], CLKOUT_DIV bits, R_DIV
SYNTH_LOCK_TIMEOUT bit fields, Bits[14:0], the bits, and EN_RDBLR bits by programming REG0010 last. Any
VCO_ALC_TIMEOUT bit fields, Bits[14:0], and the write to REG0010 starts the VCO automatic calibration.
VCO_BAND_DIV bits. Typical automatic VCO calibration times
6. This is an optional step. Monitor the register bits, ADC_BUSY
are 3 ms to 9 ms when minimum values are chosen for these
and FSM_BUSY. The calibration is finished when ADC_BUSY
parameters. Larger values produce longer VCO calibration
transitions from high to low, followed by FSM_BUSY transition-
times.
ing from high to low.
SYNTH_LOCK_TIMEOUT ≥ Ceiling 7. After the VCO calibration is complete, disable calibration clocks
(13) to limit unwanted spurious content by setting EN_DRCLK =
200 μs × fDIV_RCLK
EN_DNCLK = EN_ADC_CLK = 0.
VCO_ALC_TIMEOUT ≥ Ceiling 8. This is an optional step. Read back the VCO_CORE,
(14)
50 μs × fDIV_RCLK VCO_BAND, and VCO_BIAS bits, and then record the read-
back values. These values can be used to bypass calibration
VCO_BAND_DIV ≥ Ceiling and manually program the M_VCO_CORE, M_VCO_BAND,
(15) and M_VCO_BIAS bits for a given device and frequency, as
15 μs × fDIV_RCLK
described in the Fast Power-Up and Initialization, Manually
16 × 2DCLK_MODE Programmed VCO Calibration Settings (Optional) section.
4. Ensure that the ADC_CLK_DIV bits are set so that the desired
ADC clock frequency is <400 kHz.

Data Sheet ADF4377
THEORY OF OPERATION
Table 17. CAL_CT_SEL, DCLK_DIV2, and DCLK_MODE Setup Feedback Divider (N)
fPFD (MHz) CAL_CT_ DCLK_DIV2 DCLK_MOD fDIV_RCLK
SEL E (MHz) A 12-bit divider, the N_INT bit fields, Bits[11:0], in Figure 72, is
used to reduce the frequency seen at the output of the clock output
≤160 1 0 0 fPFD/2
divider. The feedback divider closes the feedback loop from the
>160 and ≤250 1 0 1 fPFD/2
VCO and clock output divider to the PFD.
>250 and ≤320 0 1 0 fPFD/4
>320 and ≤500 0 1 1 fPFD/4
Clock Output Divider

A 2-bit divider, CLKOUT_DIV, in Figure 69 is used to reduce
the frequency seen at the output buffer and feedback divider. Figure 72. Feedback Divider
The clock output divide value (O) may be set to 1, 2, 4, or 8.
Use the CLKOUT_DIV bit to directly program the divide ratio. The feedback divider divide ratio (N) may be programmed to any
CLKOUT_DIV is located inside the PLL loop. Therefore, any integer from 2 to 4095. Use the N_INT bit fields, Bits[11:0] to
change to CLKOUT_DIV requires a change to the N_INT bit fields, directly program the N divide ratio (see Table 20). See the Output
Bits[11:0] to maintain the same fPFD and results in the PLL losing Frequency section for the relationship between N, O, and the fREF,
lock for a few loop time constants. Refer to Table 18 for more infor- fPFD, fVCO, and fOUT frequencies. The state of the DCLK_MODE bit
mation. See the Theory of Operation section for the relationship is determined by Table 17.
between the fREF, fPFD, fVCO, and fOUT frequencies. Table 20. N_INT Programming
Table 18. CLKOUT_DIV Programming N_INT Bit Fields, Bits[11:0] N
CLKOUT_DIV O Output Frequency Range 0 Not applicable
(GHz)
1 Not applicable
0 1 6.4 ≥ fOUT ≤ 12.8 2 2
1 2 3.2 ≥ fOUT ≤ 6.4 3 3
2 4 1.6 ≥ fOUT ≤ 3.2 … …
3 8 0.8 ≥ fOUT ≤ 1.6 4095 4095
Output Invert (INV_CLKOUT) Feedback Delay

The output invert (INV_CLKOUT) is used to shift the output signal A 7-bit delay, N_DEL, is used to decrease the propagation delay
180° with respect to the rising edge of the reference input signal, from the REFP and REFN input pins to the CLKxP and CLKxN
when fOUT is an integer multiple of fREF. Refer to Table 19 for more output pins. Use the N_DEL bits to directly program the feedback
information. INV_CLKOUT is located inside the PLL loop, and any delay (tNDEL), which typically ranges from 0 ps to 110 ps in 0.85 ps
change to INV_CLKOUT results in the PLL losing lock for few a steps (see Figure 73).
loop time constants. Use the INV_CLKOUT bit to directly program
the output phase.
Table 19. INV_CLKOUT Programming
fOUT/fREF= INV_CLKOUT Each Reference Rising Edge
Aligned to
Integer 0 CLKP rising edge
Integer 1 CLKP falling edge
Noninteger x Varies
INV_CLKOUT, N_DEL, R_DEL, BLEED_I bit fields, Bits[9:0], and

BLEED_POL can be used in conjunction to align the multichip
output to output skew to sub ps levels. INV_CLKOUT does not
degrade performance and must be used to adjust for multichip out-
put-output skews greater than a quarter of the 1/fOUT period, in lieu
of a large N_DEL, R_DEL, or BLEED_I bit fields, Bits[9:0] value.
See the Aligning Multiple ADF4377 Output Phases section for the Figure 73. Step Size vs. N_DEL , Typical Feedback Delay
relationship between R_DEL, N_DEL, INV_CLKOUT, BLEED_I bit
fields, Bits[9:0], and BLEED_POL.

Data Sheet ADF4377
THEORY OF OPERATION
INV_CLKOUT, N_DEL, and R_DEL can be used in conjunction to MUXOUT

align the multichip output to output skew to within ±0.5 ps. Figure
39 shows that the largest N_DEL settings may increase LNORM by
1 dB. INV_CLKOUT does not degrade performance and can be
used to adjust for multichip output to output skews greater than a
quarter of the 1/fOUT period, in lieu of a large N_DEL or R_DEL
value. As a result, the maximum tNDEL adjustment never has to
be more than a quarter of the 1/fOUT period. See the Aligning Multi-
ple ADF4377 Output Phases section for the relationship between
R_DEL, N_DEL, INV_CLKOUT, BLEED_I bit fields, Bits[9:0], and
BLEED_POL.
Clock Output Buffer

The low noise, differential output buffer in Figure 74 produces
a differential output voltage. The output amplitude level and com-
mon mode voltage is settable with the CLKOUT1_OP bits and Figure 75. MUXOUT
CLKOUT2_OP bits, according to Table 21. Each output can be
either ac-coupled or dc-coupled and terminated with 100 Ω, differ- The state of the MUXOUT pin is determined by the serial port inter-
entially. If a single-ended output is desired, each side of the output face (SPI) register bit field MUXOUT, which allows the user access
must be individually ac-coupled and terminated with 50 Ω (see to various internal nodes. The MUXOUT pin and MUXOUT bits are
Figure 98). commonly used as an additional lock status output or to debug
Table 21. CLKOUT1_OP, CLKOUT2_OP Programming PLL related issues during the hardware and software development
CLKOUT1_OP, Differential Common-Mode Voltage
phase of a project. The CMOS_OV bit field determines if the logic
CLKOUT2_OP Amplitude (VOD) high level for the MUXOUT pin, LKDET pin, SDO pin, and SDIO pin
is 3.3 V or 1.8 V.
0 320 mVPEAK VCLK − 1.2 × VOD
Temperature Sensor
The outputs can be powered down individually by either setting

the ENCLK1 pin and ENCLK2 pin low or programming the
PD_CLKOUT1 and PD_CLKOUT2 bits to 1. The EN_CLK1 bit and
EN_CLK2 bit report the state of the ENCLK1 pin and ENCLK2 pin.
When powered down, the outputs source a common-mode voltage
around 2 V.
Figure 76. Temperature Sensor
The temperature sensor is composed of an 8-bit ADC, which

measures the proportional to absolute temperature (PTAT) voltage
with respect to the reference (VREF) voltage of a bandgap. The
purpose of the temperature sensor is to measure changes in die
temperature, not the absolute junction temperature.
The maximum ADC clock frequency is 400 kHz. Equation 16
Figure 74. Simplified Clock Outputs calculates the correct ADC_CLK_DIV value. The ADC clock may be
generated from either the SPI clock or the RCLK (see Figure 70).
Before an ADC measurement can occur, program the registers of
the ADF4377 as shown in Table 22.
Table 22. ADC Register Setup for SPI Clock and RCLK
Bits RCLK1 SPI Clock
ADC_CLK_SEL 0 1
EN_DRCLK, EN_DNCLK 1 Not applicable

Data Sheet ADF4377
THEORY OF OPERATION
Table 22. ADC Register Setup for SPI Clock and RCLK Table 24. Double Buffer Enable Bits and Bit Fields
Bits RCLK1 SPI Clock Double Buffer Enable Bits Double Buffered Bit Fields
ADC_A_CONV, EN_AUTOCAL 11 Not applicable Not applicable, always enabled N_INT bits, Bits[11:0], R_DIV,
EN_ADC_CNV, EN_ADC, 1 EN_RDBLR, CP_I
EN_ADC_CLK CLKODIV_DB CLKOUT_DIV
PD_ADC 0 DCLK_DIV_DB DCLK_DIV1, DCLK_DIV2
1 O_VCO_DB M_VCO_CORE, M_VCO_BAND,
Required when writing to REG0010 to start the ADC conversion and VCO
M_VCO_BIAS
calibration.
DEL_CTRL_DB INV_CLKOUT, BLEED_I bits, Bits[9:0],
After the bits in Table 22 are programmed, start an ADC conver- BLEED_POL, N_DEL, R_DEL
sion with either, a register write to REG0045 or a register write
to REG0010 (RCLK only). With a REG0010 write, a VCO calibra- Serial Port
tion (see the VCO Calibration section) begins immediately after
the ADC conversion is complete. An ADC conversion requires The SPI-compatible serial port provides control and monitoring
17 clock cycles to complete. In serial port register REG0049, functionality. The CMOS_OV bit determines if the logic high level
the ADC_BUSY bit monitors the conversion status. During a con- for the SDO and SDIO SPI output pins is 3.3 V or 1.8 V. CMOS_OV
version, ADC_BUSY is set to 1 and on conversion completion, also sets the output level for MUXOUT and LKDET.
ADC_BUSY is set to 0. The serial port can be programmed to support several different
Measurements are recorded in the CHIP_TEMP bit fields, Bits[8:0], configurations in REG0000 and REG0001.
in REG004C and REG004D (see Figure 76). The SDO_ACTIVE bit determines if the serial port is configured as
If an ambient temperature measurement is desired, program the a 3-wire or 4-wire serial interface (see the timing diagrams in Figure
ADF4377 to a low power state, as shown in Table 23. For ambient 2, Figure 3, and Figure 4).
temperature measurements, the SPI clock is the only available As shown in Figure 77 and Figure 78, the instruction cycle is
clock option. composed of 16 bits. The fifteen LSB bits determine the register
Table 23. Ambient Temperature Full Power Down Register Setup address, and the MSB determines if data is written to or read from
the serial interface during the data transfer cycle. The LSB_FIRST
Bit Fields State
bit determines the data orientation of the instruction cycle and data
ADC_CLK_SEL 1 transfer cycle of the serial interface.
PD_ADC 0
PD_CLK, PD_RDET, PD_CALDAC, PD_NDIV, 1
PD_VCO, PD_LD, PD_PFDCP, PD_CLKOUT1,
PD_CLKOUT2, PD_RDIV
Double Buffering Figure 77. Serial Interface, MSB First (LSB_FIRST = 0)

Double buffering refers to a main/subordinate configuration for the
bit fields shown in Table 24. Only the subordinate bit fields control
the actual state of the ADF4377. When double buffering is enabled
for a bit field, the serial interface only writes to the main bit field.
The subordinate bit field retains its previous value until a register
write is sent to REG0010. After writing to REG0010, all main bit Figure 78. Serial Interface, LSB First (LSB_FIRST = 1)
fields are automatically loaded to their respective subordinate bit
field. Writing to REG0010 also starts the autocalibration of the VCO The SPI register map can be programmed with single instructions,
(see the VCO Calibration section). This allows the user to update as shown in Figure 77 and Figure 78, or in streaming mode,
several bit fields that change the output frequency of the ADF4377 as shown in Figure 79. Streaming mode allows for efficient data
and start a new VCO calibration on the same register write. When transfer read or write cycles to multiple registers. Streaming mode
double buffering is disabled, the serial interface writes directly to the allows the user to program a bit stream composed of one register
subordinate bit field. address in the instruction header and data for that register address,
which is then followed by data in subsequent register addresses.
It is possible to read back the state of either the main or The ADDRESS_ASCENSION bit determines if the subsequent reg-
subordinate bit fields by enabling or disabling the MAIN_READ- ister addresses are incremented or decremented. It is recommend-
BACK_CONTROL bit. ed to decrement the register addresses in streaming mode (AD-
DRESS_ASCENSION = 0). The reason for this recommendation is

Data Sheet ADF4377
THEORY OF OPERATION
because REG0010 triggers the VCO calibration and loading of all The PD_CLK, PD_CALDAC, PD_RDIV, PD_NDIV, PD_VCO,
double buffers and, therefore, must be the last SPI register written PD_LD, and PD_PFDCP bits must be set to the same state at
to. The SINGLE_INSTRUCTION bit disables streaming mode when all times. The only time this group is allowed to be set to 1 is when
it is set to 1. When SINGLE_INSTRUCTION is set to 0, streaming a full power-down ambient temperature measurement is performed
mode is enabled. (see Table 23). In all other cases, this bit grouping must be set to 0.
Block Power Down Control

The power down control bits of the ADF4377 reside in REG0019
and REG001A. The PD_ALL, PD_RDET, PD_CLKOUT1, and
PD_CLKOUT2 bits may be programmed independently.
Figure 79. Serial Interface, Recommended Streaming Mode (SINGLE_INSTRUCTION = 0) with Decrementing Registers (ADDRESS_ASCENCION = 0)

Data Sheet ADF4377
APPLICATIONS INFORMATION
LOOP FILTER DESIGN

A stable loop filter design requires care in selecting the loop filter
components of the ADF4377. It is recommended to download and
install ADIsimPLL™ for loop filter design and simulation. ADIsimPLL
has an integrated tutorial for first time users and a help manual for
more complex topics. There are also several ADIsimPLL training
videos available on www.analog.com. After a loop filter has been
designed and simulated, it is recommended to verify the new loop
filter using the ADF4377 evaluation hardware. Figure 80. Single-Ended 50 Ω Source (VREF < 2.6 V p-p)
A full loop filter design tutorial is beyond the scope of this data
sheet. However, some best practices are shown in the following
lists. ADIsimPLL aids in defining and simulating these parameters.
Any significant change to these items requires a new loop filter
design.
A stable loop filter must meet the following criteria:
► Loop filter phase margin > 45°
► Loop filter bandwidth <
fPFD ÷ 10 Figure 81. Single-Ended 50 Ω Source (VREF > 2.6 V p-p)
The desired loop filter bandwidth is determined by the following

features of the ADF4377:
► ICP
► KVCO
► PFD frequency
► Reference input phase noise (see the Reference Phase Noise
section).
► Trade-off between minimizing jitter or settling time (see the
Output Phase Noise Characteristics section and Equation 12,
Figure 82. Single-Ended CMOS
respectively).
The VTUNE pin has an internal 30 pf capacitor to GND that must
be included in the loop filter design. ADIsimPLL takes this internal
capacitance into account automatically.
REFERENCE SOURCE CONSIDERATIONS
Reference Input Network

The reference input buffer of the ADF4377, shown in Figure 61,
provides a flexible interface to either differential or single-ended
frequency sources. Figure 80 to Figure 85 show recommended Figure 83. Differential LVPECL
interfaces for different reference signal types. All ZO signal traces
are 50 Ω transmission lines in Figure 80, Figure 81, Figure 82,
Figure 83, Figure 84, and Figure 85.
Figure 84. Differential LVDS

Data Sheet ADF4377
or
LOUT = LNORM + 10 × log10 fPFD + 20 × log10
N
(19)
O
where LNORM = −239 dBc/Hz. See Figure 36 to Figure 41, which

show LNORM variation vs. ICP, N_DEL, R_DEL, BLEED_I bit fields,
Bits[9:0], and reference slew rate.
Figure 85. Differential CML

As shown from Equation 18 and Equation 19 for a given PFD
frequency (fPFD), the output in-band phase noise increases at a 20
dB per decade rate with the N divider count. Therefore, for a given
Reference Phase Noise
output frequency (fOUT), fPFD must be as large as possible (or N
The ADF4377 achieves an in-band normalized phase noise floor must be as small as possible) while still satisfying the frequency
of LNORM = −239 dBc/Hz typical. To calculate the equivalent input step size requirements of the application.
phase noise floor (LIN), use the following Equation 17. Equation 17
is plotted in Figure 86. Output Phase Noise Due to 1/f Noise
LIN = LNORM + 10 × log10 fREF (17) In-band phase noise at very low offset frequencies may be influ-
enced by the 1/f noise of the ADF4377, depending on fPFD. Use the
normalized in-band 1/f noise (L1/f ) of −287 dBc/Hz with Equation
20 to approximate the output 1/f phase noise at a given frequency
offset (fOFFSET).
LOUT 1/f = L1/f + 20 × log10 fOUT − 10
(20)
× log10 fOFFSET
Often L1/f is normalized to a 1 GHz signal at a 10 kHz offset, as
shown in Equation 21.
L1/f_1G_10k = L1/f + 20 × log10 1 GHz − 10
(21)
× log10 10 kHz = L1/f + 140 dB
Unlike the in-band noise floor (LOUT), the 1/f noise (LOUT(1/f)) does
not change with fPFD and is not constant over offset frequency. See
Figure 86. Equivalent Input Reference Noise Floor vs. Reference Input Figure 87 for an example of in-band phase noise for fPFD equal to
Frequency 100 MHz and 500 MHz. The total phase noise is the summation of
LOUT and LOUT(1/f), calculated by Equation 22.
For example, a 100 MHz reference input frequency gives an LIN
of −159 dBc/Hz. The phase noise of the reference frequency LOUT TOTAL fOFFSET = 10 × log10
source must be at least 6 dB less than LIN to avoid impacting and (22)
increasing the overall system phase noise. LOUT LOUT 1/f fOFFSET
10 10 + 10 10
To maintain typical LNORM performance, Table 7 provides criteria
for selecting the optimal REF_SEL setting based on the input
reference signal type and amplitude.
OUTPUT PHASE NOISE CHARACTERISTICS
In-Band Output Phase Noise

The in-band phase noise floor (LOUT) produced at fOUT may be
calculated by Equation 18 and Equation 19.
LOUT = LNORM + 10 × log10 fPFD + 20 × log10

fOUT
(18)
fPFD

Data Sheet ADF4377
4. The ADF4377 remains in power-down mode until the PD_ALL

bit is programmed to 0. After PD_ALL is disabled, wait at least
10 μs for the VCO calibration circuitry and other circuit blocks to
settle before starting a VCO calibration.
5. A write to REG0010 starts a VCO autocalibration. At this point,
the device is fully operational and new frequencies can be
programmed as often as desired.
6. Setting PD_ALL to 1 powers down the ADF4377, retaining
the latest programmed SPI settings and full SPI programming
capability.
7. If only the state of PD_ALL was modified in Step 6, setting
PD_ALL to 0 returns the ADF4377 to the frequency program-
med in Step 5. After a 10 μs wait, all circuit blocks are
completely powered up internally. This 10 μs wait does not
Figure 87. Theoretical In-Band Phase Noise, fOUT = 10 GHz include the frequency settling time associated with the loop filter
bandwidth.
POWER-UP AND INITIALIZATION SEQUENCE 8. Toggling the CE pin level causes the ADF4377 to return to
full power-down mode and return the SPI registers to the POR
state (see Step 2 and Step 3).
POWER SUPPLY AND BYPASSING
The ADF4377 is a high performance, low noise device. Phase
noise and spurious performance may be degraded by noisy power
supplies. To achieve maximum performance and ensure that power
supply noise does not degrade the performance of the ADF4377,
it is recommended to use the Analog Devices low noise, high pow-
er supply rejection ratio (PSRR) regulators. Preferred regulators
include the LT3045, ADM7150, and the ADM7151.
The ADF4377 eliminates the need for on-board supply bypass
capacitors, by integrating all necessary local power supply bypass
Figure 88. Power-Up and Initialization Sequence capacitors on the ADF4377 package laminate. As shown in Figure
89, by removing the requirement for local power supply bypass
The following steps describe the recommended power-up and initi- capacitors, the ADF4377 consumes 40% less effective PCB area
alization sequence of the ADF4377: and reduces the number of board layout design challenges.
1. Apply specified voltages to the V5V, V3.3V_1, and V3.3V_2 power
supply groups. The ADF4377 is in full power-down mode at this
point and SPI programming is not possible.
2. Set the CE pin to a logic high. It is acceptable to connect
the CE pin to the V3_LDO pin via a pull-up resistor, therefore
performing Step 1 and Step 2 coincidentally.
3. After waiting ≥200 μs for all SPI register bits to settle to their
power-on reset state (POR), begin programming the SPI to
configure the ADF4377 to a desired state. The following is the
recommended SPI programming:
a. Set the SDO_ACTIVE and CMOS_OV bits to a desired
state for future readback operations.
Figure 89. Layout Advantages with Integrated Power Supply Decoupling
b. Program all register addresses in descending order, Capacitors
REG0045 to REG0010. There are several required re-
served register field settings provided in Table 42 that are
required for proper device operation.

Data Sheet ADF4377
DESIGN AND PROGRAMMING EXAMPLE 1: the output phase noise characteristics as described in the Output
SINGLE ADF4377 Phase Noise Characteristics section.
A single ADF4377 clocks a single ADC. The purpose of this exam- The In-Band Output Phase Noise section states the maximum fPFD
ple is to provide a method to determine the correct inputs required minimizes LOUT. The maximum fPFD is obtained with the reference
to design a loop filter in ADIsimPLL, provide a method to manually doubler enabled and the reference divider bypassed (see the Refer-
generate all ADF4377 register settings, and provide the method to ence Divider (R) and Doubler (D) section). To enable the reference
perform a VCO autocalibration on initial power-up and bypass or doubler, set EN_RDBLR = 1. The reference divider is bypassed and
override the VCO autocalibration on all future device power-ups. can remain at its power on reset state (R_DIV = 1). Solve Equation
In practice, the ADF4377 evaluation board graphical user interface 7 for the maximum fPFD.
(GUI) register automates the register generation process and can fPFD = D × fREF = 2 × 125 MHz = 250 MHz
replace and/or verify the manual register generation method.
The Charge Pump section states that larger ICP results in lower
For this design example, assume the following design goals:
LNORM, as shown in Figure 40. Set CP_I = 15 to minimize LNORM.
► Reference input, 125 MHz, single-ended 7 dBm sine wave, 50 Ω
Selecting the optimal reference input buffer amplifier (see the Ref-
environment
erence Input Buffer section) based on the reference input slew
► Output of 12 GHz
rate also minimizes LNORM (see Figure 37). Solve Equation 23 and
► SPI requirements of 1.8 V, 4 wire SPI, optimize SPI write se- Equation 8 for the reference input slew rate.
quence
PdBm /10 × 50 Ω/1000 mW (23)
► Prioritize designing for the lowest jitter performance over other VPK = 2 × 10
design criteria
7 dBm/10 × 50 Ω/1000 mW
VPK = 2 × 10 = 0 . 707
Design Procedure VPK
The following design procedure aids in schematic design and SPI Slew Rate = 2 × π × f REF × VPK = 2 × π × 125
register generation:
MHz × 0 . 707 = 556 V/υs
1. Select the settings for reference and loop filter design (see the
Reference and Loop Filter Design section) Based on Table 7 and Figure 37, a reference input slew rate of 556
V/μs minimizes LNORM when the LNA reference amplifier is selected
2. Select the output, frequency, and amplitude (see the Output by setting REF_SEL = 1. When the LNA reference amplifier is
Selection, Frequency and Amplitude section) selected, Table 8 requires FILT_REF = 0 when fREF = 125 MHz, and
3. Select the settings for the reference to output propagation Table 9 requires BST_REF = 1 when VREF = 2 × 0.707 VPK = 1.414
delay (see the Reference to Output Propagation Delay Settings V p-p.
section)
4. Select the lock detector settings (see the Lock Detector Set- The reference peak detector (see the Reference Peak Detector
tings section) section) consumes minimal power, ~10 mW, and does not degrade
5. Select the VCO automatic calibration settings (see the VCO performance. As a result, PD_RDET can be set to 0 or 1 to meet
Automatic Calibration Settings section) the design goals. The reference and loop filter design was created
with PD_RDET = 0 to allow for the option to monitor the reference
6. Select the double buffer and manual VCO calibration settings
signal with the REF_OK bit.
(see the Double Buffer and Manual VCO Calibration Settings
section) Table 25. SPI Summary, Reference and Loop Filter Design
7. Select the SPI protocol settings (see the SPI Protocol Settings Bit Field Value
section) EN_RDBLR 0x1
8. Select the remaining register settings (see the Remaining Reg-
R_DIV 0x1
ister Settings section)
CP_I 0xF
Reference and Loop Filter Design REF_SEL 0x1
FILT_REF 0x0
To design a loop filter in ADIsimPLL, the user must determine the
desired reference input settings, charge pump settings, and PFD BST_REF 0x1
frequency. The design goals provided in the Design and Program- PD_RDET 0x0
ming Example 1: Single ADF4377 section state to prioritize the
For the recommended reference input network, refer to Figure 80,
lowest jitter performance over other design criteria. To design the
single-ended 50 Ω source (VREFIN < 2.6 V p-p).
lowest jitter loop filter, determine the register settings that minimize

Data Sheet ADF4377
For ADIsimPLL loop filter design, note that the selected LNA refer- Reference to Output Propagation Delay
ence amplifier has a higher gain than the DMA reference amplifier. Settings
As a result, the LNA generates larger reference spurious content,
which requires a 5th order loop filter design to achieve the stated Reference to output propagation delay was not mentioned in the
typical spurious performance of −100 dBc. However, the DMA has Design and Programming Example 1: Single ADF4377 section. In
less reference spurious content and can use a simpler 4th order the Design and Programming Example 1: Single ADF4377 section,
loop filter design for the same spurious result. For the purposes of it was stated to prioritize to the lowest jitter performance. Setting
the reference and loop filter design, assume ADIsimPLL created a the reference to output delay controls to their minimum setting
loop filter with a 460 kHz loop bandwidth. The loop filter bandwidth achieves the lowest jitter by minimizing LNORM and L1/f (see Figure
is used to determine the LD_COUNT setting in the Lock Detector 12, Figure 15, Figure 36, and Figure 39). As shown in Figure 14,
Settings section. the INV_CLKOUT setting does not affect jitter performance and can
remain at its power on reset state of 0.
Output Selection, Frequency and Amplitude Table 27. SPI Summary, Propagation Delay
The Design and Programming Example 1: Single ADF4377 section Bit Field Value
design goals require fOUT = 12 GHz. Table 18 sets CLKOUT_DIV EN_BLEED 0x0
= 0 and O = 1 when fOUT = 12 GHz. The PLL feedback divider
BLEED_I bit fields, Bits[9:0] 0x0
bit fields, N_INT, Bits[11:0], can be determined from Equation 4,
Equation 6, and Table 20. BLEED_POL 0x0
R_DEL 0x0
fOUT = fVCO/O=fVCO
N_DEL 0x0
fVCO = fREF×D×N×O, solving for N produces INV_CLKOUT 0x0
N=fVCO / fREF×D×O = 12 GHz/ 125 MHz×2×1
= 48, N_INT setting Lock Detector Settings
The clock output buffer amplitude (see the Clock Output Buffer To enable the lock detector (see the Lock Detector section), set
section) does not have a noticeable effect on jitter performance, the EN_LOL and EN_LDWIN bits to 1. The LD_COUNT bit field
see Figure 9. However, Figure 47 indicates that lower amplitudes is determined by Equation 12. As mentioned in the Reference and
decrease the supply current. Therefore, choose the lowest ampli- Loop Filter Design section, a 460 kHz loop bandwidth (LPBW) was
tude setting the ADC clock input accepts. For the frequency and assumed.
amplitude output selection, choose the CLK1P and CLK1N clock
output buffer amplitude by setting CLKOUT1_OP = 1 (see Figure PFD Cycles = fPFD × 5/ 2 × π × LPBW = 250
30 and Table 21). MHz × 5/ 2 × π × 460 kHz = 432
Enable the output of CLK1P and CLK1N by setting the ENCLK1 pin The calculated minimum PFD cycle count of 432 is then compared
to logic high and setting PD_CLKOUT1 = 0. Because this example to the PFD cycle column in Table 14, which results in 542 PFD
clocks a single ADC, the output of CLK2P and CLK2N is pow- cycles and LD_COUNT = 9.
ered down. Power down CLK2P and CLK2N either by setting the To determine the LDWIN_PW setting from Table 16, calculate tIDEL
ENCLK2 pin to a logic low and/or setting the PD_CLKOUT2 bit = 1. from Equation 10 or Equation 11. Because the BLEED_I bit fields,
Because CLK2P and CLK2N is powered down, the CLKOUT2_OP Bits[9:0], is set to 0 in the Reference to Output Propagation Delay
amplitude setting can remain at its power on reset state of 0. Settings section, tIDEL = 0. Based on Table 16, when tIDEL = 0,
Common ADF4377 clock output networks are shown in Figure 98. LDWIN_PW is set to 0. The RST_LD bit is related to the lock
detector and is set to 0 in normal use cases.
Table 26. SPI Summary, Output Selection, Frequency and Amplitude
Bit Field Value Table 28. SPI Summary, Lock Detector
Bit Field Value
CLKOUT_DIV 0x0
N_INT, Bits[11:0] 0x30 EN_LOL 0x1
CKLOUT1_OP 0x1 EN_LDWIN 0x1
CLKOUT2_OP 0x0 LD_COUNT 0x9
PD_CLKOUT1 0x0 LDWIN_PW 0x0
PD_CLKOUT2 0x1 RST_LD 0x0

Data Sheet ADF4377
VCO Automatic Calibration Settings 125 MHz − 2

400 kHz
ADC_CLK_DIV > Ceiling 4 = Ceiling
The procedure to determine the SPI registers for an automatic VCO
calibration is outlined in the VCO Calibration section. 77 . 625 = 78
The VCO calibration Step 1 enables the automatic calibration Table 31. SPI Summary, VCO Automatic Calibration, Step 3 and Step 4
bit, EN_AUTOCAL, along with enabling several VCO calibration Bit Field Value
dividers, clocks, and the temperature sensor.
SYNTH_LOCK_TIMEOUT 0x61A8
Table 29. SPI Summary, VCO Automatic Calibration, Step 1
VCO_ALC_TIMEOUT 0x186A
Bit Field Value VCO_BAND_DIV 0x3B
EN_DNCLK 0x1 ADC_CLK_DIV 0x4E
EN_DRCLK 0x1
ADC_CLK_SEL 0x0 Double Buffer and Manual VCO Calibration
ADC_A_CONV 0x1 Settings
EN_AUTOCAL 0x1 If multiple frequency settings are desired, double buffering (see the
EN_ADC_CNV 0x1 Double Buffering section) and manual programming of the VCO
EN_ADC 0x1 settings can improve frequency switching times. In a single fixed
EN_ADC_CLK 0x1 frequency application, such as this design procedure, these modes
PD_ADC 0x0
are rarely required. Therefore, related bits can remain in their
power-up default state.
In VCO calibration Step 2, Table 17 determines the state of Table 32. SPI Summary, Double Buffer and Manual VCO Calibration Settings
CAL_CT_SEL, DCLK_DIV2, and DCLK_MODE based off the 250
Bit Field Value
MHz PFD frequency. DCLK_DIV1 must always be set to 1 regard-
less of PFD frequency. Table 17 provides an equation to calculate M_VCO_CORE 0x0
fDIV_RCLK M_VCO_BAND 0x0
fDIV_RCLK = fPFD /2 = 250 MHz/2 = 125 M_VCO_BIAS 0x0
MHz O_VCO_CORE 0x0
O_VCO_BAND 0x0
Table 30. SPI Summary, VCO Automatic Calibration, Step 2
O_VCO_BIAS 0x0
Bit Field Value
CLKO_DIV_DB 0x0
CAL_CT_SEL 0x1
DCLK_DIV_DB 0x0
DCLK_DIV2 0x0
O_VCO_DB 0x0
DCLK_MODE 0x1
DCLK_DIV1 0x1 DEL_CTRL_DB 0x0
In the VCO calibration Step 3 and Step 4, Equation 13, SPI Protocol Settings
Equation 14, Equation 15, and Equation 16 are provided
to calculate the SYNTH_LOCK_TIMEOUT bit fields, Bits[14:0], The design goals stated for the SPI protocol (see the Serial Port
VCO_ALC_TIMEOUT bit fields, Bits[14:0], VCO_BAND_DIV bits, section) are 1.8 V logic, 4-wire SPI, and optimize SPI write se-
and ADC_CLK_DIV bits from fDIV_RCLK. quence. REG0000, REG0001, and REG0018 have the SPI related
register bits, which are shown in Table 33 with the desired state
SYNTH_LOCK_TIMEOUT ≥ Ceiling based on the design goals. The power-on default state is assumed
200 μs × 125 MHz = 25000 if the bit function is not listed as a design goal.
VCO_ALC_TIMEOUT ≥ Ceiling 50 μs × 125 MHz Table 33. SPI Summary - SPI Protocol
= 6250 Bit Field Value
15 μs × 125 MHz CMOS_OV 0x0
VCO_BAND_DIV ≥ Ceiling
16 × 21 SDO_ACTIVE, SDO_ACTIVE_R 0x1
= Ceiling 58 . 59375 = 59 ADDRESS_ASCENSION, AD- 0x0
DRESS_ASCENSION_R
SINGLE_INSTRUCTION 0x0
LSB_FIRST, LSB_FIRST_R 0x0

Data Sheet ADF4377
Table 33. SPI Summary - SPI Protocol 1. Follow Step 1 through Step 5 in the Power-Up and Initialization
Bit Field Value Sequence section, using the register settings provided in the
Design Procedure section.
MAIN_READBACK_CONTROL 0x0
2. It is optional to monitor the status of the VCO calibration bit
Remaining Register Settings fields, ADC_BUSY and FSM_BUSY. A VCO calibration is com-
pleted when ADC_BUSY transitions from high to low, followed
The Charge Pump Test Mode section,MUXOUT section, and Block by FSM_BUSY transitioning from high to low. Typical automatic
Power Down Control section list several bit fields that are rec- VCO calibration times range from 3 ms to 9 ms.
ommended for special purposes, such as debug or ambient die 3. After the VCO calibration is complete, disable the VCO
temperature measurements. For this normal use case, these bit calibration clocks by setting EN_DRCLK = EN_DNCLK =
fields must be set to their POR state (see Table 34). SOFT_RESET, EN_ADC_CLK = 0. Disabling the VCO calibration clocks re-
SOFT_RESET_R, RST_SYS, and ADC_ST_CNV are the only reduces the V3.3V_1 current by roughly 15 mA and reduces
maining RW bit fields not mentioned yet, and must also be set to unwanted spurious content.
their POR state (see Table 34). 4. PLL is locked when the lock detector sets the LKDET pin and
The bit columns in Table 42 have several cells without a name. the LOCKED bit high.
These unnamed, reserved cells must be programmed to the state
Fast Power-Up and Initialization, Manually
provided in Table 42 for proper operation.
Programmed VCO Calibration Settings
Table 34. SPI Summary, Remaining Registers (Optional)
Bit Field Value
The purpose of the fast power-up and initialization method is to
EN_CPTEST 0x0 avoid the automatic VCO calibration time, which is typically 3 ms to
CP_UP 0x0 9 ms. For fixed clock frequency converter applications, such as this
CP_DOWN 0x0 design and programming Example 1, automatic VCO calibration
MUXOUT 0x0 times are typically acceptable. The following list provides the steps
PD_CLK 0x0
to record the VCO calibration results on the initial power-up and
manually program VCO Calibration settings on subsequent power
PD_CALDAC 0x0
ups:
PD_ALL 0x0
PD_RDIV 0x0 1. On initial power, follow the procedure in the Standard Power-Up
and Initialization Sequence, Automatic VCO Calibration section.
PD_NDIV 0x0
2. Record calibration results from the VCO_CORE, VCO_BAND,
PD_VCO 0x0
and VCO_BIAS bit fields and store the recorded results in
PD_LD 0x0 memory. Note that each unique device and frequency com-
PD_PFDCP 0x0 bination generates different VCO_CORE, VCO_BAND, and
SOFT_RESET, SOFT_RESET_R 0x0 VCO_BIAS values.
RESET_SYS 0x0 3. Subsequent power-up and initialization sequences (see the-
ADC_ST_CNV 0x0 Power-Up and Initialization Sequence section) can bypass the
automatic VCO calibration procedure by programming the over-
ride (O_VCO_CORE, O_VCO_BAND, and O_VCO_BIAS) and
Programming Procedure
manual (M_VCO_CORE, M_VCO_BAND, and M_VCO_BIAS)
There are two different methods to power up the ADF4377. The VCO register bits with the register settings provided in Table 35.
most commonly used method provided in the Standard Power-Up All other bit fields from the Design Procedure section remain the
and Initialization Sequence, Automatic VCO Calibration section is same.
mandatory on the initial device power-up. Table 35. Manually Programmed VCO Calibration Settings
The method provided in the Fast Power-Up and Initialization, Man- Bit Fields Value
ually Programmed VCO Calibration Settings (Optional) section is an EN_AUTOCAL 0x0
optional power-up procedure after the initial power-up. EN_DRCLK 0x0
EN_DNCLK 0x0
Standard Power-Up and Initialization
EN_ADC_CLK 0x0
Sequence, Automatic VCO Calibration
O_VCO_CORE 0x1
The following standard power-up and initialization sequence is the O_VCO_BAND 0x1
recommended procedure to power up and program the ADF4377: O_VCO_BIAS 0x1

Data Sheet ADF4377
Table 35. Manually Programmed VCO Calibration Settings Equation 24 provide several sources of possible output skew error
Bit Fields Value in a typical system. The Analog Dialogue article, "Clock Skew in
M_VCO_CORE Program M_VCO_CORE, Large Multi-GHz Clock Trees" (Volume 53, January 2019), outlines
M_VCO_BAND M_VCO_BAND, and M_VCO_BIAS with the skew trade-offs in component selection, board design, and
M_VCO_BIAS recorded VCO_CORE, VCO_BAND, end-user cost requirements in large clock trees.
and VCO_BIAS values, respectively,
from the Standard Power-Up and
Initialization Sequence, Automatic VCO
Calibration section
ALIGNING MULTIPLE ADF4377 OUTPUT

PHASES
Aligning multiple ADF4377 output phases can be broken into two
steps. The first step ensures that the reference dividers, reference Figure 90. Total System Skew
doubler, and clock output divider of the multiple devices are setup
correctly to ensure phase alignment. The second step minimizes tSKEW_SYSTEM = tSKEW_A + tSKEW_B + tSKEW_C
(24)
output to output skew between multiple ADF4377 devices. + tSKEW_D + tMEAS_ERROR
where:
Step 1: Phase Alignment
tSKEW_A = tA1 − tA0
The ADF4377 architecture includes the clock output divider and the
output invert inside the integer PLL feedback loop (see Figure 1), tSKEW_B = tPD_B1 − tPD_B0
which allows the locked PLL to align the clock output divider phase tSKEW_C = tPD_C1 − tPD_C0
to the reference input phase. Therefore, to align multiple ADF4377
output phases, ensure that the reference phases are aligned at all tSKEW_D = tPD_D1 − tPD_D0
the reference input pins of the ADF4377.
tMEAS_ERROR = tCHAN1 − tCHAN2
Because the reference divider and reference doubler are outside
To further minimize clock skew between multiple clocks, the
of the PLL loop, refer to Table 36 to ensure that phase alignment
ADF4377 devices provide SPI programmable adjustments to in-
between multiple ADF4377 devices is guaranteed.
crease or decrease the tPD in sub-ps steps. Table 37 and Table
Table 36. Reference Settings to Align Multiple ADF4377 Devices 38 provide a comparison of the multiple reference to output delay
Guaranteed Reference to Output controls. In large clock trees, these tPD adjustments can alleviate
Reference Divider and Doubler State Phase Alignment output to output skew trade-offs in component selection, board
design, and end-user cost requirements.
EN_RDBLR = 1 Yes
R_DIV = 1 Yes Table 37. ADF4377 Reference to Output Delay Control Comparison
R_DIV > 1 When fOUT/fREF = integer, and fREF ≤ Parameter Referenc Feedback Charge Pump Bleed
s e Delay Delay Current Output Invert
fOUT
Register R_DEL N_DEL EN_BLEED, BLEED_I INV_CLKOUT
Bits bit fields, Bits[9:0],
Step 2: Output to Output Skew Adjustment BLEED_POL
Any variation in reference input to output propagation delay (tPD) tPD Increases Decrease BLEED_POL = 0, Inverts output,
between multiple ADF4377 devices presents itself as output skew s increases see Table 19
between multiple ADF4377 devices. BLEED_POL = 1,
decreases
To minimize tPD across process and temperature, select the DMA Number of 127 127 1023
of the reference input buffer by setting REF_SEL = 0. When the Steps
DMA is selected, the typical tPD standard deviation due to process Step Size ~1 ps ~1 ps ~0.01 ps to 65 ps, 1
variation is 3 ps with a temperature coefficient (tPD-TC) of 0.03 2 × fOUT
varies with CP_I and
ps/°C, as shown in Figure 24 and Figure 20, respectively. fPFD Equation 9
Due to the controlled tPD of the ADF4377 devices, it is reasona-
ble to expect that a significant portion of the total system skew
(tSKEW_SYSTEM) is due to propagation delay mismatches in traces or
cables (tSKEW_B, tSKEW_D), and skew in other components (tSKEW_A)
or instruments (tMEAS_ERROR, tCHAN1, and tCHAN2). Figure 90 and

Data Sheet ADF4377
Table 38. ADF4377 Reference to Output Typical Performance Impact Table 39. Method 2: Skew Adjustment
Reference and Charge Pump tSKEW_SYSTEM Procedure
Parameters Feedback Delay Bleed Current Output Invert 0 < tSKEW_SYSTEM INV_CLKOUT = 0 and decrease tPD
Temperature Minimal, Figure None, Figure 19 None 1
≤ 4 × fOUT
Coefficient 18 and Figure 21 and Figure 22
LNORM < 1 dB, Figure 39 < 1 dB, Figure 36 None 1 INV_CLKOUT = 1 and increase tPD
4 × fOUT < tSKEW_SYSTEM
L1/f < 1 dB, Figure 39 < 4 dB, Figure 36 None 2
≤ 4 × fOUT
Spurious Minimal fPFD ≥ 50 MHz: Minimal
minimal, fPFD < 50 2 INV_CLKOUT = 1 and decrease tPD
MHz, contact ADI
3
Lock Detector None See the Lock None ≤ 4 × fOUT
Detector section 3 INV_CLKOUT = 0 and increase tPD
Figure 39 and Figure 37 show a general trend that an increasing ≤ 1 fOUT
magnitude of R_DEL, N_DEL, or BLEED_I bit fields, Bits[9:0] caus-
es a small increase in LNORM and L1/f . Increases in LNORM and L1/f DESIGN EXAMPLE 2: JESD204B/C MULTICHIP
result in clock jitter (see Figure 12 and Figure 15). Therefore, in the CLOCK AND SYSREF ALIGNMENT
most performance sensitive applications, identifying ways to mini-
mize the magnitude of the R_DEL, N_DEL, or BLEED_I bit fields, This design Example 2 focuses on the system level approach
Bits[9:0] values is desired. As an example, Figure 91 provides two of ADI to minimize clock skew between converters, such as the
skew adjustment methods to minimize the skew in Figure 90. Meth- AD9213, that include a time to digital converter (TDC). For detailed
od 1 only adjusts one of the reference to output delay adjustments ADF4377 loop filter and register map design, follow the proce-
provided in Table 37. Method 1 results in an R_DEL, N_DEL, or dure outlined in the Design and Programming Example 1: Single
BLEED_I bit fields, Bits[9:0] maximum adjustment equal to half an ADF4377 section. Device specific programming and programming
output cycle, or 1/(2 × fOUT). Method 2 minimizes the magnitude details of the AD9213 and Stage 1 distribution IC are beyond the
of R_DEL, N_DEL, or BLEED_I bit fields, Bits[9:0] by utilizing the scope of this example.
output invert along with either R_DEL, N_DEL, or BLEED_I bit For this design example, assume the following goals:
fields, Bits[9:0] adjustments. When compared to Method 1, Method
2 results in a lower R_DEL, N_DEL, or BLEED_I bit fields, Bits[9:0] ► Clock two AD9213 devices with two separate ADF4377 devices
maximum adjustment of a quarter cycle output cycle, or 1/(4 × ► Minimize clock skew at time zero
fOUT). Method 2 is furthered described in Table 39. ► Provide procedure to measure and reduce clock skew errors
Figure 91. Skew Adjustment Methods

Data Sheet ADF4377
Figure 92. Design Example 2: JESD204B/C Multichip Clock and SYSREF Alignment

Data Sheet ADF4377
Design Considerations Table 40. Trace Length Matching for Skew Optimization
If Skew Adjustments Skew Temperature Coef-
The Reference and SYSREF Distribution Selection section, Board
Performed Skew Optimization ficient Optimization
Layout Considerations section, Skew Adjustment Options section,
Skew Measurement, Adjustments and System Error section, and No ℓREFA = ℓREFB, ℓCLKA = ℓSYSREFx = ℓREFx + ℓCLKx
Power-Up, Programming, and Measurement Sequence section pro- ℓCLKB, and ℓSYSREFA =
vide an overview of several design considerations when designing ℓSYSREFB
a low clock skew system with multiple ADF4377 devices and Yes ℓSYSREFA = ℓSYSREFB ℓSYSREFx = ℓREFx + ℓCLKx
multiple JESD204B/C converters that include a TDC.
Refer to the Analog Dialogue article, "Clock Skew in Large Multi-
Reference and SYSREF Distribution Selection GHz Clock Trees" (Volume 53, January 2019) for more information
on PCB material selection, transmission line selection, cable selec-
In high performance applications that require minimum clock skew tion, and several other concerns related to clock skew.
and drift, it is recommended to choose a reference distribution de-
vice whose additive noise floor meets the requirements described Signal attenuation is proportional to the length of the trace and
in the Reference Source Considerations section, and whose output signal frequency. Converter clock traces must be treated as RF
slew rate allows for the DMA option of the ADF4377 reference input traces because any unwanted spurious or noise that couples onto
buffer (see Table 7). The DMA option minimizes tPD-TC, as shown the clock signals can affect the performance of the converters.
in Figure 20. Most reference distribution ICs output a square wave. Therefore, it is recommended to minimize the ℓCLKA and ℓCLKB trace
The slew rate of a square wave is determined by Equation 25. lengths to optimize performance and limit attenuation. Refer to the
ADC Clock and Jitter Considerations section for additional informa-
𝑆𝑙𝑒𝑤 𝑅𝑎𝑡𝑒 = tion on clock performance concerns, routing, and recommended
(25) schematics.
𝑉 𝑝-𝑝 × % 𝑈𝑝𝑝𝑒𝑟 𝑡𝑅𝐼𝑆𝐸 𝑇ℎ𝑟𝑒𝑠ℎ𝑜𝑙𝑑 − % 𝐿𝑜𝑤𝑒𝑟 𝑡𝑅𝐼𝑆𝐸 𝑇ℎ𝑟𝑒𝑠ℎ𝑜𝑙𝑑
𝑡𝑅𝐼𝑆𝐸 In most cases, trace matching board layout errors can be corrected
with the ∆t functions in the reference and SYSREF distribution IC,
The HMC7044, HMC7043, LTC6952, LTC6953, LTC6955, the ADF4377 or the AD9213, shown in Figure 92.
LTC6954, or LTC6957-1 are adequate reference distribution ICs
for the noise floor and rise time requirements. Skew Adjustment Options
By using multiple outputs from a single reference and SYSREF
Figure 92 has skew adjustment (∆t) blocks in the Stage 1 IC, the
distribution IC, the reference and SYSREF temperature delay drift
ADF4377, and the AD9213. In most cases, the ADF4377 is the pre-
match. See the LTC6952, LTC6953, and LTC6957-1 data sheets for
ferred skew adjustment option in terms of maximizing performance.
more information on output skew variation over process per output
to aid in SYSREF output selection. Choosing the outputs with the The ADF4377 ∆t blocks are discussed in Table 37. For this design
least skew for SYSREF outputs improves the skew adjustment example, either R_DEL and N_DEL or BLEED_I bit fields, Bits[9:0]
errors, as described in the Skew Measurement, Adjustments and are valid options. However, in Figure 92, only R_DEL and N_DEL
System Error section. are shown.
Selecting a JESD204B/C reference and SYSREF distribution IC The AD9213 also provides a ∆t block capable of sub-ps step sizes.
requires knowledge of the AD9213 JESD204B serial lane rates and Like any ∆t block, there is an opportunity for increased phase noise.
the clock and SYSREF requirements of the field programmable The ADF4377 and AD9213 ∆t blocks affect phase noise at different
gate array (FPGA). Both these topics are beyond the scope of this frequency offsets, as shown in Table 41.
data sheet. However, ADI has created several JESD204B/C devel-
Table 41. Clock Phase Noise Region Affected by ADF4377 and AD9213 Δt
opment platforms that provide hardware and software examples
Blocks
that can aid further in the reference and SYSREF distribution IC
selection. Several of these platforms are available on the Analog In-Band Phase Noise Wideband Phase Noise
Devices website. < ADF4377 Loop Filter
Δt Block Bandwidth ~10 MHz to fCLK
Board Layout Considerations ADF4377 ∆t Minimal additive noise, None
During hardware design, it is best to match the electrical lengths (ℓ) refer to Table 38
for the reference, clock, and SYSREF traces in Figure 92, as shown AD9213 ∆t None Minimal additive noise
in Table 40.
The reference and SYSREF distribution IC in Figure 92 has a ∆t
block for each output. The typical Stage 1 IC skew adjustment
step size is in the 11 ps (LTC6952, LTC6953) to 25 ps (HMC7044,
HMC7043) range. These ∆t blocks typically increase the phase

Data Sheet ADF4377
noise floor of the output, which then impacts the in-band perform- 3. Allow temperature of the components to settle
ance of the ADF4377. As a result, the Stage 1 reference and 4. Perform clock skew measurement
SYSREF distribution IC ∆t blocks are recommended for SYSREF 5. Program skew adjustments per Method 2, as shown in Figure
signals only. 91
6. Perform JESD204B/C initialization
Skew Measurement, Adjustments and System
Error ADC CLOCK AND JITTER CONSIDERATIONS
In Figure 92, a TDC is shown in the AD9213. The AD9213 TDC has Estimating ADC SNR and Clock Jitter
the ability to measure the time delta between the rising edge of the Requirements
AD9213 SYSREF input (tSYSREF) and the rising edge of the AD9213
clock input (tCLK) as shown in Equation 26. Adding noise directly to a clean signal reduces its signal-to-noise
ratio (SNR). In data acquisition applications, digitizing a clean signal
∆ tCLK_SYSREF = tCLK − tSYSREF (26)
with a noisy clock signal also degrades the SNR. This issue is
To determine the clock skew between the clock inputs of the best explained in the time domain by using jitter instead of phase
first AD9213 device and the second AD9213 device, measure the noise. For this discussion, assume that the jitter is white (flat with
∆tCLK_SYSREF for both AD9213 devices. frequency) and of Gaussian distribution.
∆ tCLK_SYSREFA = tCLKA − tSYSREFA Figure 93 shows a sine wave signal entering a typical data acquisi-
∆ tCLK_SYSREFB = tCLKB − tSYSREFB tion circuit composed of an ADC, an input signal amplifier, and a
sampling clock. Also shown in Figure 93 are three signal sampling
By making the assumption that the SYSREFA and SYSREFB scenarios for sampling the sine wave at its zero crossing.
signals arrive at both AD9213 devices at the same moment in time,
In the first scenario, a perfect sine wave input is buffered by a
the clock to clock skew between both AD9213 devices can be
noiseless amplifier to drive the ADC. Sampling is performed by
calculated as shown in the following equation.
a perfect, zero jitter clock. Without any added noise or sampling
Assume, tSYSREFA − tERROR = tSYSREFB clock jitter, the digitized output value of the ADC is very clearly
determined and perfectly repeatable from cycle to cycle.
tCLK_SKEW = ∆ tCLK_SYSREFA − ∆ tCLK_SYSREFB
tCLK_SKEW = tCLKA − tSYSREFA − tCLKB − tSYSREFB In the second scenario, a perfect sine wave input is buffered by
a noisy amplifier to drive the ADC. Sampling is performed by a
substituting, tSYSREFA − tERROR for tSYSREFB
perfect, zero jitter clock. The added noise results in an uncertainty
tCLK_SKEW = tCLKA − tCLKB + tERROR in the digitized value, causing an error term that degrades the SNR.
If care is taken in the Board Layout Considerations section, tERROR The degraded SNR in this scenario, from adding noise to the signal,
limits the clock skew accuracy to roughly 5 ps to 10 ps. This error is is expected.
due to the sum of errors from the SYSREF output skew from Stage In the third scenario, a perfect sine wave input is buffered by a
1, SYSREFA, and SYSREFB electrical trace matching, and the first noiseless amplifier to drive the ADC. Sampling is performed by a
AD9213 and the second AD9213 TDC measurement error. Contact clock signal with added jitter. Note that as the signal is slewing, the
ADI if less than 5 ps to 10 ps clock skew accuracy at the clock jitter of the clock signal leads to an uncertainty in the digitized value
inputs of the AD9213 is required. and an error term, like in the second scenario. Again, this error term
After tCLK_SKEW is calculated, program the second ADF4377 skew degrades the SNR.
adjustment using Method 2, as shown in Figure 91. After the A real-world system has both additive amplifier noise and sample
skew adjustment is programmed, a tCLK_SKEW measurement can clock jitter. After the signal is digitized, determining the root cause
be repeated as necessary to further fine tune the adjustment or of any SNR degradation, amplifier noise or sampling clock jitter, is
average out measurement repeatability error. essentially impossible.
Power-Up, Programming, and Measurement

Sequence
The following list provides the recommended system level power-
up, device programming, and skew measurement sequence:
1. Power up system
2. Program Stage 1 IC, ADF4377 devices, and AD9213 devices to Figure 93. A Typical Data Acquisition Circuit Showing the Sampling Error
their expected frequency plan Effects of a Noisy Amplifier and a Jittery Clock

Data Sheet ADF4377
Degradation of the SNR due to sample clock jitter only occurs if These calculations are also theoretical. They assume a noiseless
the analog input signal is slewing. If the analog input signal is ADC with infinite resolution. All realistic ADCs have both added
stationary (dc), it does not matter when in time the sampling occurs. noise and a resolution limit. The limitations of the ADC must be
Additionally, a faster slewing input signal yields a greater error accounted for to prevent overspecifying the sampling clock.
(more noise) than a slower slewing input signal.
Figure 95 plots the previous equations and provides a way to
Figure 94 demonstrates this effect. Note how much larger the error estimate the sampling clock jitter requirement for a given input
term is with the fast slewing signal than with the slow slewing signal or the expected SNR performance for a given sample clock
signal. To maintain the SNR performance of the data converter, jitter.
digitization of high input frequency signals requires a clock with
much less jitter than applications with lower frequency input signals.
Figure 94. Fast and Slow Sine Wave Signals Sampled with a Jittery Clock
It is important to note that the frequency of the analog input signal

determines the jitter requirement of the sample clock. The actual
Figure 95. SNR vs. Analog Input Frequency with Various Levels of Clock
sample clock frequency does not matter. Many ADC applications Jitter
that under sample high frequency signals have especially challeng-
ing sample clock jitter requirements.
Measuring Clock Jitter Indirectly Using ADC
This information is useful for gaining an intuitive feel for the SNR SNR
degradation due to sampling clock jitter. Quantitatively, the actual
sample clock jitter requirement for a given application is calculated For some applications, integrating the phase noise of a clock
as follows: generator within a defined offset frequency range (for example, 12
kHz to 20 MHz) is sufficient to calculate the impact of the clock on
−SNRdB the overall system performance. In these situations, the rms jitter
10 20 (27)
tJ TOTAL = 2 × π × fSIG can be calculated from a phase noise measurement.
where: However, other applications require knowledge of the phase noise
of the clock at frequency offsets that exceed the capabilities of
tJ(TOTAL) is the total RMS jitter in seconds phase noise analyzers. This limitation makes it difficult to calculate
SNRdB is the SNR requirement in decibels jitter from a phase noise measurement.
fSIG is the highest frequency signal to be digitized, expressed in Hz The rms jitter of an ADC clock source can be indirectly measured
by comparing a jitter dominated SNR measurement to a non-jitter
The total jitter is the rms sum of the aperture jitter of the ADC and dominated SNR measurement. A jitter dominated SNR measure-
the sample clock jitter, calculated as follows: ment (SNRJITTER) is created by applying a low jitter, high frequency
2 2 full-scale sine wave to the ADC analog input. A non-jitter dominated
tJ TOTAL = tJ CLK + tJ ADC (28)
SNR measurement (SNRBASE) is created by applying a very low
Alternatively, for a given total jitter, the attainable SNR is calculated amplitude (or low frequency) sine wave to the ADC analog input.
as follows: The total clock jitter (tJ(TOTAL)) can be calculated using Equation 30.
SNRdB = − 20 × log 2 × π × fSIG × t J (29)

tJ TOTAL
TOTAL
−SNR JITTER −SNRBASE
1 10 − 10 10 (30)
These calculations assume a full-scale sine wave input signal. If 10 2 × log10 10
= 2 × π × fSIG
the input signal is a complex, modulated signal with a moderate
crest factor, the peak slew rate of the signal may be lower and the
sample clock jitter requirement may be relaxed.

Data Sheet ADF4377
Assuming the inherent aperture jitter of the ADC (tJ(ADC)) is known, back toward the other end of the transmission line. In the extreme
the jitter of the clock generator (tJ(CLK)) is obtained using Equation case of an open or short-circuit termination, all of the signal is
28. reflected back. This signal reflection leads to overshoot and ringing
on the waveform. Figure 97 shows the preferred method of far-end
ADC Sample Clock Input Drive Requirements termination of the transmission line.
Modern high speed, high resolution ADCs have a high dynamic
range and are sensitive to any unwanted noise or spurious source.
Noise or interfering signals on the analog signal input, the voltage
reference, or the sampling clock input can easily appear in the
digitized data. To deliver the full performance of any ADC, the
sampling clock input must be driven with a clean, low jitter signal.
Figure 96 shows a simplified version of a typical ADC sample clock Figure 97. Far-End Transmission Line Termination (ZO = 50 Ω)
input. In Figure 96, the input pins may be labeled ENC± for encode
or CLK± for clock in different ADCs. The input is composed of a ADF4377 Output Networks
differential limiting amplifier stage followed by a buffer that directly The differential outputs of the ADF4377 are designed to interface
controls the track and hold stage of the ADC. with most differential signal devices while driving transmission lines
with far-end termination. Figure 98, Figure 99, and Figure 100
shows ac-coupled output configurations. Note that some receiver
devices have the 100 Ω termination resistor internal to the device,
in which case the external 100 Ω resistor is unnecessary. The
ADF4377 also interfaces with single-ended 50 Ω end terminations.
In this case, the unused output requires an ac-coupled 50 Ω termi-
nation. For the single-ended example in Figure 100, the CLKxP and
CLKxN pins may be swapped.
Figure 96. Simplified Sample Clock Input Circuit

Figure 98. Common Clock Interface: Differential Clock with On Board End
The sample clock input amplifier also benefits from a fast slewing Termination (ZO = 50 Ω)
input signal because the amplifier has noise of its own. By slewing
through the crossover region quickly, the amplifier noise creates
less jitter than if the transition were slow. As shown in Figure 96,
the sample clock input of the ADC is typically differential, with a dif-
ferential sampling clock delivering the best performance. Figure 96
also shows the sample clock input with a different common-mode
input voltage than the outputs of the ADF4377. Most ADC applica-
tions require ac coupling to convert between the two common-mode
voltages. Figure 99. Common Clock Interface: Differential Clock with On-Chip End
Termination (ZO = 50 Ω)
Transmission Lines and Termination
Interconnection of high speed signaling with fast rise and fall times
requires the use of transmission lines with properly matched termi-
nation. The transmission lines may be stripline, microstrip or any
other design topology. A detailed discussion of transmission line
design is beyond the scope of this data sheet. Any mismatch be-
tween the characteristic impedance of the transmission line and the
terminating impedance results in a portion of the signal reflecting

Data Sheet ADF4377
occurs at the top and bottom pedestal voltage of the square wave.
However, only amplitude modulation near a zero crossing affects
the clock.
The best way to remove this measurement error is to drive the
clock generator output differentially into a limiting buffer on a sep-
arate clean power supply. One of the differential outputs of the
limiting buffer can then connect to a spectrum analyzer to correctly
measure the spurious energy. An example of this technique using
Figure 100. Common Clock Interface: Single Ended Clock with End the ADF4377 as the clock generator and an HMC940 as the limiter
Termination (ZO = 50 Ω)
is shown in Figure 101.
MEASURING DIFFERENTIAL SPURS WITH A
SINGLE-ENDED TEST INSTRUMENT
Using a spectrum analyzer to measure spurious signals on the
single-ended output of a clock generation chip gives pessimistic
results, particularly for outputs that approximate square waves.
There are two reasons for this.
Figure 101. Example of Spurious Measurement Techniques
First, because the spurious energy is often an ac signal superim-
posed on the power supply, a differential output rejects the spurs to APPLICATION CIRCUITS
within the matching of the positive and negative outputs. Observing
only one side of the differential output provides no rejection. Parallel ADF4377 Devices, 13 fs RMS Jitter
Second, and most importantly, the spectrum analyzer displays all
of the energy at its input, including amplitude modulation that
Figure 102. Block Diagram of Parallel ADF4377 Devices

Data Sheet ADF4377
Figure 103. 12 GHz Parallel ADF4377s, 13 fsrms Jitter
AD9082 Error Vector Magnitude (EVM) with

ADF4377 as Clock
Figure 104. AD9082 and ADF4377 Measurement Schematic
Figure 105. AD9082 EVM with ADF4377 as 12 GHz Clock

Data Sheet ADF4377
REGISTER MAP
Table 42. ADF4377 Register Map

Reg Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x00 SOFT_RESET_ LSB_FIRST_R ADDRESS_AS SDO_ACTIVE SDO_ACTIVE ADDRESS_AS LSB_FIRST SOFT_RESET 0x00 R/W
R CENSION_R _R CENSION
0x01 SINGLE_INSTR 0 MAIN_READB 0 0 0 0 0 0x00 R/W
UCTION ACK_CONTR
OL
0x02 RESERVED R002_RSV1 0x00 R
0x03 RESERVED CHIP_TYPE 0x00 R
0x04 PRODUCT_ID[7:0] 0x00 R
0x05 PRODUCT_ID[15:8] 0x00 R
0x06 R006_RSV2 R006_RSV1 0x00 R
0x0A SCRATCHPAD 0x00 R/W
0x0B SPI_REVISION 0x00 R
0x0C VENDOR_ID[7:0] 0x56 R
0x0D VENDOR_ID[15:8] 0x04 R
0x0F 0 0 0 0 0 0 0 0 0x00 R/W
0x10 N_INT[7:0] 0x80 R/W
0x11 EN_AUTOCAL EN_RDBLR DCLK_DIV2 N_INT[11:8] 0x00 R/W
0x12 CLKOUT_DIV R_DIV 0x01 R/W
0x13 0 0 M_VCO_CORE M_VCO_BIAS 0x00 R/W
0x14 M_VCO_BAND 0x00 R/W
0x15 BLEED_I[1:0] BLEED_POL EN_BLEED CP_I 0x00 R/W
0x16 BLEED_I[9:2] 0x00 R/W
0x17 INV_CLKOUT N_DEL 0x00 R/W
0x18 CMOS_OV R_DEL 0x00 R/W
0x19 CLKOUT2_OP CLKOUT1_OP PD_CLK PD_RDET PD_ADC PD_CALDAC 0x04 R/W
0x1A PD_ALL PD_RDIV PD_NDIV PD_VCO PD_LD PD_PFDCP PD_CLKOUT1 PD_CLKOUT2 0x83 R/W
0x1B EN_LOL LDWIN_PW EN_LDWIN LD_COUNT 0x00 R/W
0x1C EN_DNCLK EN_DRCLK 0 0 0 RST_LD 0 1 0x00 R/W
0x1D MUXOUT 0 EN_CPTEST CP_DOWN CP_UP 0x00 R/W
0x1E 0 0 0 0 0 0 0 0 0x00 R/W
0x1F BST_REF FILT_REF REF_SEL 0 0 1 1 1 0x00 R/W
0x20 0 0 0 RST_SYS EN_ADC_CLK 0 0 1 0x00 R/W
0x21 1 1 0 1 0 0 1 1 0x00 R/W
0x22 0 0 1 1 0 0 1 0 0x00 R/W
0x23 CAL_CT_SEL 0 0 1 1 0 0 0 0x00 R/W
0x24 0 0 0 0 0 DCLK_MODE 0 0 0x00 R/W
0x25 CLKODIV_DB DCLK_DIV_DB 0 1 0 1 1 0 0x00 R/W
0x26 VCO_BAND_DIV 0x00 R/W
0x27 SYNTH_LOCK_TIMEOUT[7:0] 0x00 R/W
0x28 O_VCO_DB SYNTH_LOCK_TIMEOUT[14:8] 0x00 R/W
0x29 VCO_ALC_TIMEOUT[7:0] 0x00 R/W
0x2A DEL_CTRL_DB VCO_ALC_TIMEOUT[14:8] 0x00 R/W
0x2B 0 0 0 0 0 0 0 0 0x00 R/W
0x2C 1 1 0 0 0 0 0 0 0x00 R/W
0x2D ADC_CLK_DIV 0x00 R/W
0x2E EN_ADC_CNV 0 0 0 0 0 EN_ADC ADC_A_CONV 0x00 R/W
0x2F 0 0 0 0 0 0 DCLK_DIV1 0x00 R/W

Data Sheet ADF4377
REGISTER MAP
Table 42. ADF4377 Register Map

Reg Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reset RW
0x30 0 0 0 0 0 0 0 0 0x00 R/W
0x31 0 0 0 0 1 0 0 1 0x00 R/W
0x32 0 ADC_CLK_SEL 0 0 1 0 0 1 0x00 R/W
0x33 0 0 0 1 1 0 0 0 0x00 R/W
0x34 0 0 0 0 1 0 0 0 0x00 R/W
0x35 0 0 0 0 0 0 0 0 0x00 R/W
0x36 0 0 0 0 0 0 0 0 0x00 R/W
0x37 0 0 0 0 0 0 0 0 0x00 R/W
0x38 R038_RSV1 0x00 R
0x39 0 0 0 0 0 0 0 0 0x00 R/W
0x3A 0 1 0 1 1 1 0 1 0x00 R/W
0x3B 0 0 1 0 1 0 1 1 0x00 R/W
0x3C 0 0 0 0 0 0 0 0 0x00 R/W
0x3D 0 0 0 0 O_VCO_BAND O_VCO_COR O_VCO_BIAS 0 0x00 R/W
E
0x3E 0 0 0 0 0 0 0 0 0x00 R/W
0x3F 0 0 0 0 0 0 0 0 0x00 R/W
0x40 0 0 0 0 0 0 0 0 0x00 R/W
0x41 0 0 0 0 0 0 0 0 0x00 R/W
0x42 0 0 0 0 0 1 0 1 0x00 R/W
0x43 0 0 0 0 0 0 0 0 0x00 R/W
0x44 0 0 0 0 0 0 0 0 0x00 R/W
0x45 0 0 0 0 0 0 0 ADC_ST_CNV 0x00 R/W
0x46 R046_RSV1[7:0] 0x00 R
0x47 R046_RSV1[15:8] 0x00 R
0x48 R046_RSV1[23:16] 0x00 R
0x49 EN_CLK2 EN_CLK1 R049_RSV2 R049_RSV1 REF_OK ADC_BUSY FSM_BUSY LOCKED 0x00 R
0x4A R04A_RSV1 0x00 R
0x4B RESERVED VCO_CORE 0x00 R
0x4C CHIP_TEMP[7:0] 0x00 R
0x4D RESERVED CHIP_TEMP[8] 0x00 R
0x4E R04E_RSV1 0x00 R
0x4F VCO_BAND 0x00 R
0x50 R050_RSV1 0x00 R
0x51 RESERVED VCO_BIAS 0x00 R
0x52 RESERVED R052_RSV1 0x00 R
0x53 RESERVED R053_RSV2 R053_RSV1 0x00 R
0x54 VERSION 0x00 R
REGISTER DETAILS
Address: 0x00, Reset: 0x00, Name: REG0000

Data Sheet ADF4377
REGISTER MAP
Figure 106.
Table 43. Bit Descriptions for REG0000

Bits Bit Name Description Reset Access
7 SOFT_RESET_R Repeat of SOFT_RESET. 0x0 R/W
6 LSB_FIRST_R Repeat of LSB_FIRST. 0x0 R/W
5 ADDRESS_ASCENSION_R Repeat of ADDRESS_ASCENSION. 0x0 R/W
4 SDO_ACTIVE_R Repeat of SDO_ACTIVE. 0x0 R/W
3 SDO_ACTIVE Choose Between 3-Wire or 4-Wire Operation. 0x0 R/W
0: 3-wire.
1: 4-wire SPI (enables SDO and SDIO becomes an input only).
2 ADDRESS_ASCENSION Address Ascension When Streaming. 0x0 R/W
0: address auto-decrements when streaming.
1: address auto-increments when streaming.
1 LSB_FIRST I/O Data Oriented LSB First. 0x0 R/W
0: MSB first.
1: LSB first.
0 SOFT_RESET Reset SPI Registers Except REG0000 to POR State. Self-clearing reset. 0x0 R/W
0: Normal operation.
1: Soft reset.
Figure 107.

7 SINGLE_INSTRUCTION Single Instruction. 0x0 R/W
0: SPI streaming enabled.
1: SPI streaming disabled.
6 R001_RSV6 Reserved. Table 42 provides required reserved register settings. 0x0 R/W
5 MAIN_READBACK_CONTROL Main/Subordinate Readback Control. 0x0 R/W
0: double buffering, readback subordinate register.

Data Sheet ADF4377
REGISTER MAP

1: double buffering, readback main register.
3 RESERVED Reserved. 0x0 R
0 RESERVED Reserved. 0x0 R
Figure 108.

[7:4] RESERVED Reserved. 0x0 R
[3:0] R002_RSV1 Reserved. 0x0 R
Figure 109.

[3:0] CHIP_TYPE Chip Type = 0x06. 0x0 R
Figure 110.

[7:0] PRODUCT_ID[7:0] Product ID = 0x0005. 0x0 R

Data Sheet ADF4377
REGISTER MAP
Figure 111.

[7:0] PRODUCT_ID[15:8] Product ID = 0x0005. 0x0 R
Figure 112.

Address: 0x0A, Reset: 0x00, Name: REG000A
Figure 113.
Table 50. Bit Descriptions for REG000A

[7:0] SCRATCHPAD SPI Scratchpad. 0x0 R/W
Address: 0x0B, Reset: 0x00, Name: REG000B
Figure 114.
Table 51. Bit Descriptions for REG000B

[7:0] SPI_REVISION SPI Revision = 0x01. 0x0 R
Address: 0x0C, Reset: 0x56, Name: REG000C

Data Sheet ADF4377
REGISTER MAP
Figure 115.
Table 52. Bit Descriptions for REG000C

[7:0] VENDOR_ID[7:0] Vendor ID = 0x0456. 0x56 R
Address: 0x0D, Reset: 0x04, Name: REG000D
Figure 116.
Table 53. Bit Descriptions for REG000D

[7:0] VENDOR_ID[15:8] Vendor ID = 0x0456. 0x4 R
Address: 0x0F, Reset: 0x00, Name: REG000F
Figure 117.
Table 54. Bit Descriptions for REG000F

0 R00F_RSV1 Reserved. Table 42 provides required reserved register settings. 0x0 R/W
Figure 118.

[7:0] N_INT[7:0] Feedback Divider, 12-Bit Integer Divider in REG0010 and REG0011. Set to any divide value from 2 to 4095, 0x80 R/W
inclusive. Double buffering always enabled.

Data Sheet ADF4377
REGISTER MAP
Figure 119.

7 EN_AUTOCAL Enable VCO Calibration. 0x0 R/W
0: disabled.
1: enabled.
6 EN_RDBLR Enable Reference Doubler. 0x0 R/W
0: reference divider path selected.
1: reference doubler path selected.
[5:4] DCLK_DIV2 VCO Calibration Divider 2. 0x0 R/W
00: divide by 1.
01: divide by 2.
10: divide by 4.
11: divide by 8.
[3:0] N_INT[11:8] Feedback Divider, 12-Bit Integer Divider in REG0010 and REG0011. Set to any divide value from 2 to 4095, 0x0 R/W
inclusive. Double buffering always enabled.
Figure 120.

[7:6] CLKOUT_DIV Clock Output Divider. 0x0 R/W
00: divide by 1.
01: divide by 2.
10: divide by 4.
11: divide by 8.
[5:0] R_DIV Reference Divider, 6-Bit Integer Divider. 0x1 R/W
Figure 121.

Data Sheet ADF4377
REGISTER MAP

[7:6] R013_RSV1 Reserved. Table 42 provides required reserved register settings. 0x0 R/W
[5:4] M_VCO_CORE Selects VCO Core When O_VCO_CORE = 1. 0x0 R/W
00: VCO 0 lowest frequency.
01: VCO 1.
10: VCO 2.
11: VCO 3 highest frequency.
[3:0] M_VCO_BIAS Sets VCO Bias When O_VCO_BIAS = 1. 0x0 R/W
0000: bias = 0.
0001: bias = 1.
0010: bias = 2.
0011: bias = 3.
0100: bias = 4.
0101: bias = 5.
0110: bias = 6.
0111: bias = 7.
1000: bias = 8.
1001: bias = 9.
1010: bias = 10.
1011: bias = 11.
1100: bias = 12.
1101: bias = 13.
1110: bias = 14.
1111: bias = 15.
Figure 122.

[7:0] M_VCO_BAND When O_VCO_BAND = 1, Selects Between 256 Possible VCO Bands Within VCO Core. 0x0 R/W
0: highest frequency VCO band
255: lowest frequency VCO band
Figure 123.

Data Sheet ADF4377
REGISTER MAP

[7:6] BLEED_I[1:0] Charge Pump Bleed Current, 10 Bits in REG0015 and REG0016. Refer to the Charge Pump Bleed Current 0x0 R/W
section. Double buffering option.
5 BLEED_POL Charge Pump Bleed Current Polarity. 0x0 R/W
0: sink current. Increases reference input to clock output propagation delay.
1: source current. Decreases reference input to clock output propagation delay.
4 EN_BLEED Enable Charge Pump Bleed Current. 0x0 R/W
0: disabled.
1: enabled.
[3:0] CP_I Charge Pump Current. 0x0 R/W
0000: 0.79 mA.
0001: 0.99 mA.
0010: 1.19 mA.
0011: 1.38 mA.
0100: 1.59 mA.
0101: 1.98 mA.
0110: 2.39 mA.
0111: 2.79 mA.
1000: 3.18 mA.
1001: 3.97 mA.
1010: 4.77 mA.
1011: 5.57 mA.
1100: 6.33 mA.
1101: 7.91 mA.
1110: 9.51 mA.
1111: 11.1 mA.
Figure 124.

[7:0] BLEED_I[9:2] Charge Pump Bleed Current, 10 Bits in REG0015 and REG0016. Refer to the Charge Pump Bleed Current 0x0 R/W
section. Double buffering option.
Figure 125.

7 INV_CLKOUT Clock Output Invert. Double buffering option. 0x0 R/W

Data Sheet ADF4377
REGISTER MAP

0: not inverted.
1: inverted.
[6:0] N_DEL Feedback Delay. Decreases reference input to clock output propagation delay. Double buffering option. 0x0 R/W
Figure 126.

7 CMOS_OV Logic High Voltage for MUXOUT, LKDET, SDO, SDIO. 0x0 R/W
0: 1.8 V logic.
1: 3.3 V logic.
[6:0] R_DEL Reference Delay. Increases reference input to clock output propagation delay. Double buffering option. 0x0 R/W
Figure 127.

[7:6] CLKOUT2_OP Programs a Clock Output Buffer Amplitude for Pins CLK2N and CLK2P. 0x0 R/W
00: minimum amplitude, see the Specifications section.
01: see the Specifications section.
11: maximum amplitude, see the Specifications section.
[5:4] CLKOUT1_OP Programs Clock Output Buffer Amplitude for Pins CLK1N and CLK1P. 0x0 R/W
00: minimum amplitude, see the Specifications section.
11: maximum amplitude, see the Specifications section.
3 PD_CLK Power Down the VCO Multiplexer and Clock Divider. 0x0 R/W
0: active. Normal operation.
1: power-down. Refer to the Block Power Down Control section.
2 PD_RDET Power Down the Reference Detector. 0x1 R/W

Data Sheet ADF4377
REGISTER MAP

1: power-down.
1 PD_ADC Power Down the Temperature ADC. 0x0 R/W
1: power-down.
0 PD_CALDAC Power Down the VCO Calibration Digital to Analog Converter (DAC). 0x0 R/W
Figure 128.

7 PD_ALL Main Power Down. 0x1 R/W
0: active.
1: power-down. Does not reset SPI registers to POR state. Refer to the Power-Up and Initialization Sequence
section.
6 PD_RDIV Power Down the Reference Divider and Doubler. 0x0 R/W
5 PD_NDIV Power Down the Feedback Divider. 0x0 R/W
4 PD_VCO Power Down the VCO. 0x0 R/W
3 PD_LD Power Down the Lock Detector. 0x0 R/W
2 PD_PFDCP Power Down the PFD and CP. 0x0 R/W
1 PD_CLKOUT1 Power Down Clock Output Buffer to Pins CLK1N and CLK1P. 0x1 R/W
1: power-down.
0 PD_CLKOUT2 Power Down Clock Output Buffer to Pins CLK2N and CLK2P. 0x1 R/W
1: power-down.

Data Sheet ADF4377
REGISTER MAP
Figure 129.

7 EN_LOL Enable Loss-of-Lock Detector. 0x0 R/W
0: disabled.
1: enabled. Normal operation.
6 LDWIN_PW Lock Detector Pulse Window. 0x0 R/W
0: narrow window. Normal operation.
1: wide window. Refer to the Lock Detector section.
5 EN_LDWIN Enable the Lock Detector Pulse Window. 0x0 R/W
0: disabled.
[4:0] LD_COUNT Number of Valid PFD Cycles Before the Lock Detector Indicates PLL is Locked. Refer to the Lock Detector 0x0 R/W
section.
Figure 130.

7 EN_DNCLK Enable VCO Calibration Divider. See Figure 70. 0x0 R/W
0: disabled. Disable when not in use to reduce spurious content.
1: enabled. Enable before a VCO calibration begins.
6 EN_DRCLK Enable Divider to the VCO Calibration Block and ADC Clock Divider. See Figure 70. 0x0 R/W
0: disabled. Disable when not in use to reduce spurious content.
1: enabled. Enable before a VCO calibration or temperature sensor measurement begins.
5 R01C_RSV4 Reserved. Table 42 provides required reserved register settings. 0x0 R/W
2 RST_LD Reset Lock Detector to the Unlocked State. This bit is not self-clearing. 0x0 R/W
0: reset inactive. Normal operation.
1: reset active.

Data Sheet ADF4377
REGISTER MAP

[1:0] R01C_RSV1 Reserved. Table 42 provides required reserved register settings. 0x0 R/W
Figure 131.

[7:4] MUXOUT Select Test Signal Presented on MUXOUT Pin. 0x0 R/W
0000: high-Z.
0001: LKDET. Lock detector output.
0010: low.
0011: low.
0100: fDIV_RCLK/2.
0101: fDIV_NCLK/2.
0110: reserved.
0111: low.
1000: high.
1001: reserved.
1010: reserved.
1011: low.
1100: low.
1101: low.
1110: reserved.
1111: reserved.
3 R01D_RSV1 Reserved. Table 42 provides required reserved register settings. 0x0 R/W
2 EN_CPTEST Enable Charge Pump Test Mode. 0x0 R/W
0: disabled. Normal operation.
1: enabled.
1 CP_DOWN Enables Charge Pump Sink Current when EN_CPTEST is Enabled. 0x0 R/W
0: disabled.
1: enabled.
0 CP_UP Enables Charge Pump Source Current when EN_CPTEST is Enabled. 0x0 R/W
0: disabled.
1: enabled.
Address: 0x1E, Reset: 0x00, Name: REG001E

Data Sheet ADF4377
REGISTER MAP
Figure 132.
Table 69. Bit Descriptions for REG001E

7 R01E_RSV6 Reserved. Table 42 provides required reserved register settings. 0x0 R/W
[5:4] R01E_RSV4 Reserved. Table 42 provides required reserved register settings. 0x0 R/W
[1:0] R01E_RSV1 Reserved. Table 42 provides required reserved register settings. 0x0 R/W
Figure 133.

7 BST_REF Enable LNA Reference Input Buffer Gain Boost for Low Amplitude Input. Refer to Table 9. 0x0 R/W
0: disabled.
1: enabled.
6 FILT_REF Enable LNA Reference Input Buffer Filter. Refer to Table 8. 0x0 R/W
0: disabled.
1: enabled.
5 REF_SEL Select the Reference Input Buffer. Refer to Table 7. 0x0 R/W
0: DMA for an improved reference input to clock output propagation delay temperature coefficient.
1: LNA for improved PLL in-band noise when a low slew rate signal is applied to the reference input.
[3:0] R01F_RSV1 Reserved. Table 42 provides required reserved register settings. 0x0 R/W

Data Sheet ADF4377
REGISTER MAP
Figure 134.

4 RST_SYS Reset Digital Functions to POR State. Does not reset the SPI interface and SPI registers. This bit is not 0x0 R/W
self-clearing.
0: reset inactive. Normal operation.
1: reset active.
3 EN_ADC_CLK Enable the ADC Clock. See Figure 70. 0x0 R/W
0: disabled.
Figure 135.

Figure 136.

[7:0] R022_RSV0[7:0] Reserved. Table 42 provides required reserved register settings. 0x0 R/W

Data Sheet ADF4377
REGISTER MAP
Figure 137.

7 CAL_CT_SEL VCO Calibration Count Select. Refer to Table 17. 0x0 R/W
0 R022_RSV0[8] Reserved. Table 42 provides required reserved register settings. 0x0 R/W
Figure 138.

2 DCLK_MODE Enable Frequency Reduction During VCO Calibration. Divides fDIV_RCLK and fDIV_NCLK by 2 when enabled. 0x0 R/W
Refer to Table 17.
0: disabled.
1: enabled.
Figure 139.

7 CLKODIV_DB Enables Double Buffering for CLKOUT_DIV Bit Field. 0x0 R/W

Data Sheet ADF4377
REGISTER MAP

0: disabled.
1: enabled.
6 DCLK_DIV_DB Enables Double Buffering for the DCLK_DIV1 and DCLK_DIV2 Bit Fields. 0x0 R/W
0: disabled.
1: enabled.
Figure 140.

[7:0] VCO_BAND_DIV Time for Each VCO Calibration Decision. Determined by Equation 13 in the VCO Calibration section. 0x0 R/W
Figure 141.

[7:0] SYNTH_LOCK_TIMEOUT[7:0] Timeout for the Calibration DAC Settling Time During a VCO Calibration. Determined by 0x0 R/W
Equation 13 in the VCO Calibration section.
Figure 142.

7 O_VCO_DB Enables Double Buffering for the M_VCO_CORE, M_VCO_BAND, and M_VCO_BIAS 0x0 R/W
Bit Fields.
0: disabled.
1: enabled.

Data Sheet ADF4377
REGISTER MAP

[6:0] SYNTH_LOCK_TIMEOUT[14:8] Timeout for the Calibration DAC Settling Time During a VCO Calibration. Determined 0x0 R/W
by Equation 13 in the VCO Calibration section.
Figure 143.

[7:0] VCO_ALC_TIMEOUT[7:0] Timeout for Automatic Level Control (ALC) Algorithm During VCO Calibration. Determined by 0x0 R/W
Figure 144.

7 DEL_CTRL_DB Enables Double Buffering for the R_DEL, N_DEL, INV_CLKOUT, BLEED_I, and 0x0 R/W
BLEED_POL Bit Fields.
0: disabled.
1: enabled.
[6:0] VCO_ALC_TIMEOUT[14:8] Timeout for Automatic Level Control (ALC) Algorithm During VCO Calibration. Determined by 0x0 R/W
Figure 145.

[7:0] R02B_RSV1[7:0] Reserved. Table 42 provides required reserved register settings. 0x0 R/W

Data Sheet ADF4377
REGISTER MAP
Figure 146.

[3:0] R02B_RSV1[11:8] Reserved. Table 42 provides required reserved register settings. 0x0 R/W
Figure 147.

[7:0] ADC_CLK_DIV ADC Clock Divider. Determined by Equation 13 in the VCO Calibration section. 0x0 R/W
Figure 148.

7 EN_ADC_CNV Enable ADC Conversion. Refer to the Temperature Sensor section. 0x0 R/W
0: disabled.
1 EN_ADC Enable ADC. Refer to the Temperature Sensor section. 0x0 R/W
0: ADC conversion only possible with write to ADC_ST_CNV bit field.

Data Sheet ADF4377
REGISTER MAP

0 ADC_A_CONV Enable ADC Conversion During a VCO Calibration. 0x0 R/W
0: ADC conversion only possible with write to ADC_ST_CNV bit field.
1: enabled. Normal operation. Automatically begins ADC conversion at the start of a VCO calibration or with
write to ADC_ST_CNV bit field.
Figure 149.

[1:0] DCLK_DIV1 VCO Calibration Divider 1. 0x0 R/W
00: divide by 1.
01: divide by 2.
10: divide by 8.
11: divide by 32.
Figure 150.


Data Sheet ADF4377
REGISTER MAP
Figure 151.

Figure 152.

6 ADC_CLK_SEL Select Clock Source Presented to ADC Clock Divider. See Figure 70. 0x0 R/W
0: select internal clock. Normal operation. Used during VCO calibrations and full power die temperature
measurement.
1: select SCLK pin. Ambient die temperature measurements with the temperature sensor. See the
Temperature Sensor section.

Data Sheet ADF4377
REGISTER MAP
Figure 153.

Figure 154.

Figure 155.


Data Sheet ADF4377
REGISTER MAP
Figure 156.

Figure 157.

Figure 158.


Data Sheet ADF4377
REGISTER MAP
Figure 159.

Figure 160.

[7:0] R03A_RSV1 Reserved. Table 42 provides required reserved register settings. 0x0 R/W
Figure 161.

[7:6] R03B_RSV2 Reserved. Table 42 provides required reserved register settings. 0x0 R/W
[5:0] R03B_RSV1 Reserved. Table 42 provides required reserved register settings. 0x0 R/W
Figure 162.


Data Sheet ADF4377
REGISTER MAP
Figure 163.

[7:4] R03D_RSV2 Reserved. Table 42 provides required reserved register settings. 0x0 R/W
3 O_VCO_BAND Override VCO Band with M_VCO_BAND. 0x0 R/W
0: VCO band code from VCO calibration state machine.
1: VCO band code from M_VCO_BAND.
2 O_VCO_CORE Override VCO Core with M_VCO_CORE. Refer to the VCO Calibration section. 0x0 R/W
0: VCO core set by the VCO calibration state machine.
1: VCO core set by M_VCO_CORE.
1 O_VCO_BIAS Override VCO Bias with M_VCO_BIAS. Refer to the VCO Calibration section. 0x0 R/W
0: VCO bias set by the VCO calibration state machine.
1: VCO bias set by M_VCO_VBIAS.
0 R03D_RSV1 Reserved. Table 42 provides required reserved register settings. 0x0 R/W
Figure 164.


Data Sheet ADF4377
REGISTER MAP
Figure 165.

Figure 166.

Figure 167.

Figure 168.


Data Sheet ADF4377
REGISTER MAP

Figure 169.

Figure 170.


Refer to the Temperature Sensor section.
Figure 171.

0 ADC_ST_CNV Write This Bit to Start an ADC Conversion. 0x0 R/W

Data Sheet ADF4377
REGISTER MAP
Figure 172.

[7:0] R046_RSV1[7:0] Reserved. 0x0 R
Figure 173.

[7:0] R046_RSV1[15:8] Reserved. 0x0 R
Figure 174.

[7:0] R046_RSV1[23:16] Reserved. 0x0 R
Figure 175.

7 EN_CLK2 Logic State on ENCLK2 Input Pin. See Figure 74. 0x0 R
6 EN_CLK1 Logic State on ENCLK1 Input Pin. See Figure 74. 0x0 R
5 R049_RSV2 Reserved. 0x0 R

Data Sheet ADF4377
REGISTER MAP

3 REF_OK 1 = Reference Input Amplitude Above Reference Peak Detector Threshold. 0x0 R
2 ADC_BUSY 1 = ADC Conversion in Progress. Refer to the VCO Calibration section and the Temperature Sensor section. 0x0 R
1 FSM_BUSY 1 = VCO Calibration in Progress. 0x0 R
0 LOCKED Lock Detector Output. 0x0 R
Figure 176.

[7:0] R04A_RSV1 Reserved. 0x0 R
Figure 177.

[1:0] VCO_CORE VCO Core Readback. See the VCO Calibration section. 0x0 R
Figure 178.

[7:0] CHIP_TEMP[7:0] Temperature Measured by the ADC. CHIP_TEMP[8] is the sign bit, where 0 = positive and 1 = negative. 0x0 R
CHIP_TEMP[7:0] = magnitude.
Figure 179.

Data Sheet ADF4377
REGISTER MAP

0 CHIP_TEMP[8] Temperature Measured by the ADC. CHIP_TEMP[8] is the sign bit, where 0 = positive and 1 = negative. 0x0 R
CHIP_TEMP[7:0] = magnitude.
Figure 180.

[7:0] R04E_RSV1 Reserved. 0x0 R
Figure 181.

[7:0] VCO_BAND VCO Band Readback. See the VCO Calibration section. 0x0 R
Figure 182.

Figure 183.


Data Sheet ADF4377
REGISTER MAP

[3:0] VCO_BIAS VCO Bias Readback. See the VCO Calibration section. 0x0 R
Figure 184.

Figure 185.

Figure 186.

[7:0] VERSION Die Revision Code. 0x0 R

Data Sheet ADF4377
OUTLINE DIMENSIONS
Figure 187. 48-Lead Land Grid Array Package [LGA] (CC-48-6) 7 mm × 7 mm Body, Dimensions shown in millimeters.
Updated: September 04, 2022

ORDERING GUIDE
Package
Model1 Temperature Range Package Description Packing Quantity Option
ADF4377BCCZ -40°C to +105°C LGA/CASON/CH ARRY SO NO LD CC-48-6
ADF4377BCCZ-RL7 -40°C to +105°C LGA/CASON/CH ARRY SO NO LD Reel, 1500 CC-48-6
1 Z = RoHS Compliant Part.
EVALUATION BOARDS
Model1 Description
EV-ADF4377SD1Z ADF4377 LGA Evaluation Board
1 Z = RoHS Compliant Part.
©2022 Analog Devices, Inc. All rights reserved. Trademarks and Rev. 0 | 79 of 79
registered trademarks are the property of their respective owners.
One Analog Way, Wilmington, MA 01887-2356, U.S.A.

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Data Sheet

FEATURES GENERAL DESCRIPTION

FUNCTIONAL BLOCK DIAGRAM

Features................................................................ 1 Reference Source Considerations................... 32

10/2022—Revision 0: Initial Version

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1 1.2 V < VCP < 3.4 V.

SERIAL INTERFACE TIMING CHARACTERISTICS

Figure 2. Write Timing Diagram

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Figure 3. 3-Wire Read Timing Diagram (SDO_ACTIVE = 0)

Figure 4. 4-Wire Read Timing Diagram (SDO_ACTIVE = 1)

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TA = 25°C, unless otherwise noted. ELECTROSTATIC DISCHARGE (ESD) RATINGS

Stresses at or above those listed under Absolute Maximum Ratings

1 Test Condition 1: thermal impedance simulated values are based on use of a

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Figure 5. Pin Configuration

Table 6. Pin Function Descriptions

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Table 6. Pin Function Descriptions

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Figure 22. tPD and tPD-TC vs. BLEED_I, BLEED_POL = 1

Figure 23. tPD vs. Temperature, CLKOUT_OP Setting

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Figure 31. Differential Output at 6 GHz

Figure 32. Differential Output at 3 GHz

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Figure 52. DMA Reference Input Sensitivity at Various Reference

Figure 53. LNA Reference Input Sensitivity at Various Reference Frequencies

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Figure 60. PLL Loop Diagram

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Table 8. FILT_REF Programming Table 11. EN_RDBLR and R_DIV Programming

Reference Peak Detector

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Table 12. CP Programming

Charge Pump Test Mode

Charge Pump Bleed Current

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When the charge pump bleed current is enabled, a phase offset is

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Figure 70. VCO Calibration Dividers

Figure 71. VCO Calibration Block

To perform a VCO calibration, set up several registers as outlined in