Data Sheet

ADE9430
High Performance, Polyphase Energy, and Class S Power Quality Monitoring IC

FEATURES ► Total and fundamental IRMS and VRMS

► Power factor
► 7 high performance, 24-bit Σ-Δ ADCs
► Supports active energy standards: IEC 62053-21 and IEC
► 101 dB SNR at 8 kSPS with PGA = 1
62053-22, EN50470-3, OIML R46, and ANSI C12.20
► Wide input voltage range: ±1 V, 707 mV rms full scale at gain
► Supports reactive energy standards: IEC 62053-23 and IEC
=1 62053-24
► Differential inputs
► High speed communication port: 20 MHz SPI
► ±25 ppm/°C maximum channel drift (including ADC, internal ► Integrated temperature sensor with 12-bit successive approxima-
VREF, PGA drift) enabling 10000:1 dynamic input range, Class tion register (SAR) ADC
0.2 metrology with standard external components
► ±3°C accuracy from −40°C to +85°C
► With the optional ADSW-PQ-CLS Power Quality Library, the
complete IEC 61000-4-30 Class S power quality standard is APPLICATIONS
implemented including:
► Energy and power monitoring
► Power frequency 10 sec average
► Standards compliant power quality monitoring
► Magnitude of the supply
► Protective devices
► Dips and swells
► Machine health
► Interruptions
► Smart power distribution units
► Rapid voltage change
► Polyphase energy meters
► Flicker
► Mains signaling voltage
► Underdeviation and overdeviation
► Voltage and current
► Magnitude
► Harmonics
► Interharmonics
► Unbalance
► THD
► Waveform recording

► Optional ADSW-PQ-CLS Power Quality Library compatible with

®
ARM Cortex microcontrollers
► VRMS one-cycle and IRMS one-cycle refreshed each cycle
► VRMS and IRMS filtered and updated every sample
► 10 cycle rms/12 cycle rms
► Period registers to calculate line frequency, one per phase
► Zero crossing and zero-crossing timeout
► Phase angle measurements
► Supports CTs
► Multipoint phase and gain compensations for CTs
► Rogowski coils with the addition of an external analog integrator
► Continuous resampled data available
► Waveform buffer
► Advanced metrology feature set
► Total and fundamental active power, volt amperes reactive
(VAR), volt amperes (VA), watthour, VAR hour, and VA hour
Rev. 0
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Data Sheet ADE9430
TABLE OF CONTENTS

Features................................................................ 1 Energy Linearity Repeatability..........................17

Applications........................................................... 1 RMS Linearity over Temperature and RMS
General Description...............................................3 Error over Frequency..................................... 18
Typical Applications Circuit....................................4 Signal-to-Noise Ratio Performance..................20
Specifications........................................................ 5 Test Circuit...........................................................21
Timing Characteristics........................................8 Terminology......................................................... 22
Absolute Maximum Ratings...................................9 Theory of Operation.............................................23
Thermal Resistance........................................... 9 Measurements..................................................23
Electrostatic Discharge (ESD) Ratings...............9 Power Quality Measurements.......................... 29
ESD Caution.......................................................9 Applications Information...................................... 34
Pin Configuration and Function Descriptions...... 10 Waveform Buffer...............................................34
Typical Performance Characteristics................... 12 Interrupts and Events....................................... 34
Energy Linearity over Supply and Accessing On-Chip Data.................................. 34
Temperature................................................... 12 Outline Dimensions............................................. 35
Energy Error over Frequency and Power Ordering Guide.................................................35
Factor............................................................. 15 Evaluation Boards............................................ 35

REVISION HISTORY

5/2022—Revision 0: Initial Version

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Data Sheet ADE9430
GENERAL DESCRIPTION

The ADE9430 is a highly accurate, fully integrated, polyphase en-

ergy and power quality monitoring device. Superior analog perform-
ance and a digital signal processing (DSP) core enable accurate
energy monitoring over a wide dynamic range. An integrated high
end reference ensures low drift over temperature with a combined
drift of less than ±25 ppm/°C maximum for the entire channel
including a programmable gain amplifier (PGA) and an analog-to-
digital converter (ADC).
The ADE9430 offers a complete power quality monitoring capability
by providing instantaneous total as well as fundamental measure-
ments on rms, frequency, phase angle, power factor active, reac-
tive, and apparent powers and energies. Using the optional ADSW-
PQ-CLS Power Quality Library, advanced power quality features,
such as dip and swell monitoring, power frequency, voltage total
harmonic distortion (VTHD), and current total harmonic distortion
(ITHD), are enabled. The one cycle rms, 10 cycle rms/12 cycle rms,
and the optional ADSW-PQ-CLS Power Quality Library features
are calculated according to IEC 61000-4-30 Class S. To request
access to the ADSW-PQ-CLS, fill out the software request form at:
Software Request Form | Analog Devices, where the target technol-
ogy must be power quality monitoring and the processor/system on
chip (SoC) is the ADE9430.
The ADE9430 offers a resampled waveform of 1024 points per
10 cycles or 12 cycles. Resampling simplifies the fast Fourier
transform (FFT) calculation of at least 40 harmonics in an external
processor.
The ADE9430 simplifies the implementation and certification of
energy and power quality monitoring systems by providing tight
integration of acquisition and calculation engines. The integrated
ADCs and DSP engine calculate various parameters and provide
data through user accessible registers or indicate events through
interrupt pins. With seven dedicated ADC channels, the ADE9430
can be used on a 3-phase system or up to three single-phase
systems. This device supports current transformers (CTs) or Ro-
gowski coils when used with external analog integrator for current
measurements.
The ADE9430 absorbs most of the complexity in calculations for
a power quality monitoring system. Combining a simple host micro-
controller and the optional ADSW-PQ-CLS Power Quality Library,
the ADE9430 enables the design of standalone monitoring or pro-
tection systems, or low cost nodes uploading data into the cloud.
Note that throughout this data sheet, multifunction pins, such as
CF4/EVENT/DREADY, are referred to either by the entire pin name
or by a single function of the pin, for example, EVENT, when only
that function is relevant.

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Data Sheet ADE9430
TYPICAL APPLICATIONS CIRCUIT

Figure 1. Typical Application Circuit

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Data Sheet ADE9430
SPECIFICATIONS

VDD = 2.97 V to 3.63 V, GND = AGND = DGND = 0 V, on-chip reference, CLKIN = 24.576 MHz crystal (XTAL), TMIN to TMAX = −40°C to +85°C,
and TA = 25°C (typical), unless otherwise noted.

Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
ACCURACY (MEASUREMENT ERROR PER PHASE)
Total Active Energy 0.1 % Over a dynamic range of 5000 to 1, 10 sec accumulation
0.2 % Over a dynamic range of 10,000 to 1, 20 sec accumulation
Total Reactive Energy 0.1 % Over a dynamic range of 5000 to 1, 10 sec accumulation
0.2 % Over a dynamic range of 10,000 to 1, 20 sec accumulation
Total Apparent Energy 0.1 % Over a dynamic range of 1000 to 1, 2 sec accumulation
0.5 % Over a dynamic range of 5000 to 1, 10 sec accumulation
Fundamental Active Energy 0.1 % Over a dynamic range of 5000 to 1, 2 sec accumulation
0.2 % Over a dynamic range of 10,000 to 1, 10 sec accumulation
Fundamental Reactive Energy 0.1 % Over a dynamic range of 5000 to 1, 2 sec accumulation
0.2 % Over a dynamic range of 10,000 to 1, 10 sec accumulation
Fundamental Apparent Energy 0.1 % Over a dynamic range of 5000 to 1, 2 sec accumulation
0.5 % Over a dynamic range of 10,000 to 1, 10 sec accumulation
IRMS and VRMS 0.1 % Over a dynamic range of 1000 to 1
0.5 % Over a dynamic range of 5000 to 1
Fundamental IRMS, VRMS 0.1 % Over a dynamic range of 1000 to 1
0.5 % Over a dynamic range of 5000 to 1
Active Power, VAR, VA 0.2 % Over a dynamic range of 1000 to 1
0.4 % Over a dynamic range of, 3000 to 1
Power Factor (PF) Error ±0.001 % Over a dynamic range of 5000 to 1
128-Point per Line Cycle or 1024 Point over 10 0.1 % An FFT is performed to receive the magnitude response;
Cycles Resampled Data this error is the worst case error in the magnitude caused by
the resampling algorithm distortion; the input signal is 50 Hz
fundamental and ninth harmonic both at half of full scale
−72 dB Amplitude of highest spur; input signal is 50 Hz fundamental
and ninth harmonic both at half of full scale
1.25 % An FFT is performed to receive the magnitude response;
this error is the worst case error in the magnitude caused
by resampling algorithm distortion; input signal is 50 Hz
fundamental and 31st harmonic, both at half of full scale
−38 dB Amplitude of highest spur; input signal is 50 Hz fundamental
and 31st harmonic, both at half of full scale
10 Cycle/12 Cycle IRMS and VRMS1 0.2 % Data sourced before high-pass filter (HPF), no dc offset at
inputs, over a dynamic range of 100 to 1
VRMS and IRMS 1 Cycle 0.2% % Data sourced before HPF, no dc offset at inputs, over a
dynamic range of 100 to 1
Line Period Measurement 0.001 Hz Resolution at 50 Hz
Current to Current, Voltage to Voltage, and Voltage 0.018 Degrees Resolution at 50 Hz
to Current Angle Measurement
ADC
PGA Gain Settings (PGA_GAIN) 1, 2, or 4 V/V PGA gain setting is referred to as the PGA_GAIN register
Differential Input Voltage Range (VxP to VxN, IxP to −1/Gain +1/Gain V 707 mV rms, when VREF = 1.25 V, this voltage corresponds
IxN) to 53 million codes
Maximum Operating Voltage on Analog Input Pins −0.6 +0.6 V Voltage on the pin with respect to ground (GND = AGND =
(VxP, VxN, IxP, and IxN) DGND = REFGND)
Signal-to-Noise Ratio (SNR)2
PGA = 1 96 dB 32 kSPS, sinc4 output, input voltage (VIN) = −0.5 dB from
half of full scale

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Data Sheet ADE9430
SPECIFICATIONS

Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
101 dB 8 kSPS, sinc4 + infinite impulse response (IIR), low-pass
filter (LPF) output, VIN = −0.5 dB from half of full scale
PGA = 4 93 dB 32 kSPS, sinc4 output
96 dB 8 kSPS, sinc4 + IIR LPF output
Total Harmonic Distortion (THD)2
PGA = 1 −101 −95 dB 32 kSPS, sinc4 output, VIN = −0.5 dB from half of full scale
−101 −95 dB 8 kSPS, sinc4 + IIR LPF output, VIN = −0.5 dB from half of
full scale
PGA = 4 −107 −99 dB 32 kSPS, sinc4 output
−107 −99 dB 8 kSPS, sinc4 + IIR LPF output
Signal-to-Noise and Distortion Ratio
PGA = 1 95 dB 32 kSPS, sinc4 output, VIN = −0.5 dB from half of full scale
98 dB 8 kSPS, sinc4 + IIR LPF output, VIN = −0.5 dB from half of
full scale
PGA = 4 93 dB 32 kSPS, sinc4 output
96 dB 8 kSPS, sinc4 + IIR LPF output
Spurious-Free Dynamic Range (SFDR)2
PGA = 1 100 dB 32 kSPS, sinc4 output, VIN = −0.5 dB from half of full scale
100 dB 8 kSPS, sinc4 + IIR LPF output, VIN = −0.5 dB from half of
full scale
Output Pass Band (0.1dB)
Sinc4 Outputs 1.344 kHz 32 kSPS, sinc4 output
Sinc4 + IIR LPF Outputs 1.344 kHz 8 kSPS output
Output Bandwidth (−3 dB)2
Sinc4 Outputs 7.2 kHz 32 kSPS, sinc4 output
Sinc4 + IIR LPF Outputs 3.2 kHz 8 kSPS output
Crosstalk2 −120 dB At 50 Hz or 60 Hz, see the Terminology section
AC Power Supply Rejection Ratio (AC PSRR)2 −120 dB At 50 Hz, see the Terminology section
Common-Mode Rejection Ratio (AC CMRR)2 115 dB At 100 Hz and 120 Hz
Gain Error ±0.3 ±1 %Typ See the Terminology section
Gain Drift2 ±3 ppm/°C See the Terminology section
Offset ±0.040 ±3.8 mV See the Terminology section
Offset Drift2 0 ±2 µV/°C See the Terminology section
Channel Drift (PGA, ADC, and Internal Voltage ±7 ±25 ppm/°C PGA = 1, internal VREF
Reference (VREF))
±7 ±25 ppm/°C PGA = 2, internal VREF
±7 ±25 ppm/°C PGA = 4, internal VREF
Differential Input Impedance (DC) 165 185 kΩ PGA = 1, see the Terminology section
80 90 kΩ PGA = 2
40 45 kΩ PGA = 4
INTERNAL VOLTAGE REFERENCE Nominal = 1.25 V ± 1 mV
Voltage Reference 1.250 V TA = 25°C, REF pin
Temperature Coefficient2 ±5 ±20 ppm/°C TA = −40°C to +85°C, tested during device characterization
EXTERNAL VOLTAGE REFERENCE
Input Voltage (REF) 1.2 or 1.25 V REFGND must be tied to GND, AGND, and DGND, a 1.25
V external reference is preferred; the half of full-scale values
mentioned in this data sheet are for a voltage reference of
1.25 V
Input Impedance 7.5 kΩ

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Data Sheet ADE9430
SPECIFICATIONS

Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
TEMPERATURE SENSOR
Temperature Accuracy ±2 °C −10°C to +40°C
±3 °C −40°C to +85°C
Temperature Readout Step Size 0.3 °C
CRYSTAL OSCILLATOR All specifications use CLKIN = 24.576 MHz ± 30 ppm
Input Clock Frequency 24.33 24.576 24.822 MHz
Internal Capacitance on CLKIN and CLKOUT 4 pF
Internal Feedback Resistance Between CLKIN and 2.45 MΩ
CLKOUT
Transconductance (gm) 5 8 mA/V
EXTERNAL CLOCK INPUT
Input Clock Frequency 24.330 24.576 24.822 MHz ±1%
Duty Cycle2 45:55 50:50 55:45 %
CLKIN Logic Input Voltage 3.3 V tolerant
High, VINH 1.2 V VDD = 2.97 V to 3.63 V
Low, VINL 0.5 V VDD = 2.97 V to 3.63 V
LOGIC INPUTS (PM0, PM1, RESET, MOSI, SCLK,
and SS)
Input Voltage
VINH 2.4 V
VINL 0.8 V
Input Current, IIN 15 µA VIN = 0 V
Internal Capacitance, CIN 10 pF
LOGIC OUTPUTS
MISO, IRQ0, and IRQ1
Output Voltage
High, VOH 2.4 V Source current (ISOURCE) = 4 mA
Low, VOL 0.8 V Sink current (ISINK) = 4 mA
CIN 10 pF
CF1, CF2, CF3, and CF4
Output Voltage
VOH 2.4 V ISOURCE = 7 mA
VOL 0.8 V ISINK = 8 mA
CIN 10 pF
LOW DROPOUT (LDO) REGULATORS
Analog Supply Voltage (AVDD) 1.9 V
Digital Supply Voltage (DVDD) 1.7 V
POWER SUPPLY
VDD 2.97 3.3 3.63 V Power-on reset (POR) level is 2.4 V to 2.6 V
Supply Current (IDD)
Power Save Mode 0 (PSM0) 15 17 mA Normal mode
14.5 16.5 mA Normal mode, six ADCs enabled
Power Save Mode 3 (PSM3) 90 300 nA Idle, VDD = 3.3 V, AVDD = 0 V, DVDD = 0 V
1 Enables implementation of IEC 61000-4-30 Class S.
2 Tested during device characterization.

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Data Sheet ADE9430
SPECIFICATIONS

TIMING CHARACTERISTICS

Table 2.
Parameter Symbol Min Typ Max Unit
SS to SCLK Edge tSS 10 ns
SCLK Frequency fSCLK 20 MHz
SCLK Low Pulse Width tSL 20 ns
SCLK High Pulse Width tSH 20 ns
Data Output Valid After SCLK Edge tDAV 20 ns
Data Input Setup Time Before SCLK Edge tDSU 10 ns
Data Input Hold Time After SCLK Edge tDHD 10 ns
Data Output Fall Time tDF 10 ns
Data Output Rise Time tDR 10 ns
SCLK Fall Time tSF 10 ns
SCLK Rise Time tSR 10 ns
MISO Disable Time After SS Rising Edge tDIS 100 ns
SS High After SCLK Edge tSFS 0 ns

Figure 2. Serial Port Interface (SPI) Timing Diagram

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Data Sheet ADE9430
ABSOLUTE MAXIMUM RATINGS

TA = 25°C, unless otherwise noted. ELECTROSTATIC DISCHARGE (ESD) RATINGS

Table 3. The following ESD information is provided for handling of ESD-sen-
Parameter Rating sitive devices in and ESD-protected area only.
VDD to GND −0.3 V to +3.96 V Human body model (HBM) per ANSI/ESDA/JEDEC JS-001-2012.
Analog Input Voltage to GND, IAP, IAN, IBP, IBN, ICP, −2 V to +2 V
ICN, INP, INN, VAP, VAN, VBP, VBN, VCP, VCN Field induced charged-device model (FICDM) per JESD22-C101E.
Reference Input Voltage to REFGND −0.3 V to +2 V
Machine model (MM) per ANSI/ESD STMD5.2 MM ratings are for
Digital Input Voltage to GND −0.3 V to VDD + 0.3 V characterization only.
Digital Output Voltage to GND −0.3 V to VDD + 0.3 V
Operating Temperature ESD Ratings for the ADE9430
Industrial Range −40°C to +85°C
Table 5. ADE9430, 40-Lead LFCSP
Storage Range −65°C to +150°C
ESD Model1 Withstand Threshold Class
Junction 125°C
Lead (Soldering, 10 sec)1 260°C HBM 3.75 kV 2
FICDM 1.25 kV IV
1 Analog Devices recommends that reflow profiles used in soldering RoHS MM 300 V Not applicable
compliant devices conform to J-STD-020D.1 from JEDEC. Refer to JEDEC for
1 Analog Devices recommends that reflow profiles used in soldering RoHS
the latest revision of this standard.
compliant devices conform to J-STD-020D.1 from JEDEC. Refer to JEDEC for
Stresses at or above those listed under Absolute Maximum Ratings the latest revision of this standard.
may cause permanent damage to the product. This is a stress
rating only; functional operation of the product at these or any other ESD CAUTION
conditions above those indicated in the operational section of this ESD (electrostatic discharge) sensitive device. Charged devi-
specification is not implied. Operation beyond the maximum operat- ces and circuit boards can discharge without detection. Although
ing conditions for extended periods may affect product reliability. this product features patented or proprietary protection circuitry,
THERMAL RESISTANCE damage may occur on devices subjected to high energy ESD.
Therefore, proper ESD precautions should be taken to avoid
Thermal performance is directly linked to printed circuit board performance degradation or loss of functionality.
(PCB) design and operating environment. Careful attention to PCB
thermal design is required.
θJA and θJC are specified for the worst case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type θJA θJC Unit
CP-40-71 27.14 3.13 °C/W
1 The junction to air measurement uses a 2S2P JEDEC test board with 4 × 4
standard JEDEC vias. The junction to case measurement uses a 1S0P JEDEC
test board with 4 × 4 standard JEDEC vias. See JEDEC standard JESD51-2.

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Data Sheet ADE9430
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Figure 3. Pin Configuration

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description
1 PULL_HIGH Pull High. Tie this pin to VDD.
2 DGND Digital Ground. This pin provides the ground reference for the digital circuitry in the ADE9430. Because the digital return currents
in the ADE9430 are small, it is acceptable to connect this pin to the analog ground plane of the whole system. Connect all grounds
(GND, AGND, DGND, and REFGND) together at one point.
3 DVDDOUT 1.8 V Output of the Digital LDO Regulator. Decouple this pin with a 0.1 µF ceramic capacitor in parallel with a 4.7 µF ceramic
capacitor.
4 PM0 Power Mode Pin 0. PM0, combined with PM1, defines the power mode. For normal operation, ground PM0 and PM1.
5 PM1 Power Mode Pin 1. PM1 combined with PM0, defines the power mode. For normal operation, ground PM0 and PM1.
6 RESET Reset Input, Active Low. This pin must stay low for at least 1 µs to trigger a hardware reset.
7, 8 IAP, IAN Analog Inputs, Channel IA. The IAP (positive) and IAN (negative) inputs are fully differential voltage inputs with a maximum
differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.
9, 10 IBP, IBN Analog Inputs, Channel IB. The IBP (positive) and IBN (negative) inputs are fully differential voltage inputs with a maximum
differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.
11, 12 ICP, ICN Analog Inputs, Channel IC. The ICP (positive) and ICN (negative) inputs are fully differential voltage inputs with a maximum
differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.
13, 14 INP, INN Analog Inputs, Channel IN. The INP (positive) and INN (negative) inputs are fully differential voltage inputs with a maximum
differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.
15 REFGND Ground Reference, Internal Voltage Reference. Connect all grounds (GND, AGND, DGND, and REFGND) together at one point.
16 REF Voltage Reference. The REF pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of
1.25 V. An external reference source of 1.2 V to 1.25 V can also be connected at this pin. In either case, decouple REF to REFGND
with a 0.1 µF ceramic capacitor in parallel with a 4.7 µF ceramic capacitor. After reset, the on-chip reference is enabled. To use the
internal voltage reference with the external circuits, a buffer is required.
17 NC1 No Connection. It is recommended to tie this pin to ground.
18 NC2 No Connection. It is recommended to tie this pin to ground.
19, 20 VAN, VAP Analog Inputs, Channel VA. The VAP (positive) and VAN (negative) inputs are fully differential voltage inputs with a maximum
differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.
21, 22 VBN, VBP Analog Inputs, Channel VB. The VBP (positive) and VBN (negative) inputs are fully differential voltage inputs with a maximum
differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.
23, 24 VCN, VCP Analog Inputs, Channel VC. The VCP (positive) and VCN (negative) inputs are fully differential voltage inputs with a maximum
differential level of ±1 V. This channel also has an internal PGA of 1, 2, or 4.
25 AVDDOUT 1.9 V Output of the Analog LDO Regulator. Decouple AVDDOUT with a 0.1 µF ceramic capacitor in parallel with a 4.7 µF ceramic
capacitor. Do not connect external active circuitry to this pin.
26 AGND Analog Ground Reference. Connect all grounds (GND, AGND, DGND, and REFGND) together at one point.

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Data Sheet ADE9430
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

Table 6. Pin Function Descriptions

Pin No. Mnemonic Description
27 VDD Supply Voltage. The VDD pin provides the supply voltage. Decouple VDD to GND with a ceramic 0.1 µF capacitor in parallel with a
10 µF ceramic capacitor.
28 GND Supply Ground Reference. Connect all grounds (GND, AGND, DGND, and REFGND) together at one point.
29 CLKIN Crystal/Clock Input. Connect a crystal across CLKIN and CLKOUT to provide a clock source. Alternatively, an external clock can be
provided at this logic input.
30 CLKOUT Crystal Output. Connect a crystal across CLKIN and CLKOUT to provide a clock source. When using CLKOUT to drive external
circuits, connect an external buffer.
31 IRQ0 Interrupt Request Output. This pin is an active low logic output. See the Interrupts and Events section for information about events
that trigger interrupts.
32 IRQ1 Interrupt Request Output. This pin is an active low logic output. See the Interrupts and Events section for information about events
that trigger interrupts.
33 CF1 Calibration Frequency Logic Output 1. The CF1, CF2, CF3, and CF4 outputs provide power information based on the CFxSEL bits
in the CFMODE register. Use these outputs for operational and calibration purposes. Scale the full-scale output frequency by writing
to the CFxDEN registers (see the Digital to Frequency Conversion—CFx Output section and the ADE9430 Technical Reference
Manual).
34 CF2 CF Logic Output 2. This pin indicates CF2.
35 CF3/ZX CF Logic Output 3/Zero Crossing. This pin indicates CF3 or zero crossing.
36 CF4/EVENT/DREADY CF Logic Output 4/Event Pin/Data Ready. This pin indicates CF4, events, or when new data is ready.
37 SCLK Serial Clock Input for the SPI Port. All serial data transfers synchronize to this clock (see the Accessing On-Chip Data section).
The SCLK pin has a Schmitt trigger input for use with a clock source that has a slow edge transition time, for example, optoisolator
outputs.
38 MISO Data Output for the SPI Port.
39 MOSI Data Input for the SPI Port.
40 SS Chip Select for the SPI Port.
EPAD Exposed Pad. Create a similar pad on the PCB under the exposed pad. Solder the exposed pad to the pad on the PCB to confer
mechanical strength to the package and connect all grounds (GND, AGND, DGND, and REFGND) together at this point.

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Data Sheet ADE9430
TYPICAL PERFORMANCE CHARACTERISTICS

ENERGY LINEARITY OVER SUPPLY AND TEMPERATURE

Total energies obtained from a sinusoidal voltage with an amplitude of 50% of full scale and a frequency of 50 Hz, a sinusoidal current with
variable amplitudes from 100% of full scale down to 0.01% or 0.02% of full scale and a frequency of 50 Hz. Fundamental energies obtained
with a fundamental voltage component, with an amplitude of 50% of full scale in phase with a fifth harmonic, a current with a 50 Hz component
that has variable amplitudes from 100% of full scale down to 0.01% of full scale, and a fifth harmonic with a constant amplitude of 40% of
fundamental unless otherwise noted.

Figure 4. Total Active Energy Error as a Percentage of Full-Scale Current Figure 6. Total Apparent Energy Error as a Percentage of Full-Scale Current
over Temperature, Power Factor = 1 over Temperature, Power Factor = 1

Figure 5. Total Reactive Energy Error as a Percentage of Full-Scale Current Figure 7. Total Active Energy Error as a Percentage of Full-Scale Current
over Temperature, Power Factor = 0 over Supply Voltage, Power Factor = 1, TA = 25°C

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Data Sheet ADE9430
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 8. Total Reactive Energy Error as a Percentage of Full-Scale Current Figure 11. Fundamental Reactive Energy Error as a Percentage of Full-Scale
over Supply Voltage, Power Factor = 0, TA = 25°C Current over Temperature, Power Factor = 0

Figure 9. Total Apparent Energy Error as a Percentage of Full-Scale Current Figure 12. Fundamental Apparent Energy Error as a Percentage of Full-Scale
over Supply Voltage, Power Factor = 1, TA = 25°C Current over Temperature, Power Factor = 1

Figure 10. Fundamental Active Energy Error as a Percentage of Full-Scale Figure 13. Fundamental Active Energy Error as a Percentage of Full-Scale
Current over Temperature, Power Factor = 1 Current over Supply Voltage, Power Factor = 1, TA = 25°C

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Data Sheet ADE9430
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 14. Fundamental Reactive Energy Error as a Percentage of Full-Scale Figure 15. Fundamental Apparent Energy Error as a Percentage of Full-Scale
Current over Supply Voltage, Power Factor = 0, TA = 25°C Current over Supply Voltage, Power Factor = 1, TA = 25°C

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Data Sheet ADE9430
TYPICAL PERFORMANCE CHARACTERISTICS

ENERGY ERROR OVER FREQUENCY AND POWER FACTOR

Total energies obtained from a sinusoidal voltage with an amplitude of 50% of full scale, a sinusoidal current with a constant amplitude of 10%
of full scale, and a variable frequency between 45 Hz and 65 Hz. Fundamental energies obtained with a fundamental voltage at 50 Hz, with an
amplitude of 50% of full scale in phase with the fifth harmonic, a current that has constant amplitude of 10% of full scale, and a fifth harmonic
with a constant amplitude of 40% of fundamental, unless otherwise noted.

Figure 16. Total Active Energy Error vs. Line Frequency, Power Factor = −0.5, Figure 18. Total Apparent Energy Error vs. Line Frequency
Power Factor = +0.5, and Power Factor = +1

Figure 19. Fundamental Active Energy Error vs. Line Frequency, Power
Figure 17. Total Reactive Energy Error vs. Line Frequency, Power Factor = Factor = −0.5, Power Factor = +0.5, and Power Factor = +1
−0.866, Power Factor = 0, and Power Factor = +0.866

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Data Sheet ADE9430
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 20. Fundamental Reactive Energy Error vs. Line Frequency, Power
Factor = −0.866, Power Factor = 0, and Power Factor = +0.866

Figure 21. Fundamental Apparent Energy Error vs. Line Frequency

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Data Sheet ADE9430
TYPICAL PERFORMANCE CHARACTERISTICS

ENERGY LINEARITY REPEATABILITY

Total energies obtained from a sinusoidal voltage with an amplitude of 50% of full scale and a frequency of 50 Hz, a sinusoidal current with
variable amplitudes from 100% of full scale down to 0.01% of full scale, and a frequency of 50 Hz. Fundamental energies obtained with a
fundamental voltage component, with an amplitude of 50% of full scale in phase with the fifth harmonic, a current with a 50 Hz component
that has variable amplitudes from 100% of full scale down to 0.01% of full scale, and a fifth harmonic with a constant amplitude of 40% of
fundamental. Measurements at 25°C repeated 30 times, unless otherwise noted.

Figure 22. Total Active Energy Error as a Percentage of Full-Scale Current, Figure 24. Fundamental Active Energy Error as a Percentage of Full-Scale
Power Factor = 1 (Standard Deviation σ = 0.02% at 0.01% of Full-Scale Current, Power Factor = 1 (Standard Deviation σ = 0.03% at 0.01% of Full-
Current) Scale Current)

Figure 23. Total Reactive Energy Error as a Percentage of Full-Scale Current, Figure 25. Fundamental Reactive Energy Error as a Percentage of Full-Scale
Power Factor = 0 (Standard Deviation σ = 0.03% at 0.01% of Full-Scale Current, Power Factor = 0 (Standard Deviation σ = 0.04% at 0.01% of Full-
Current) Scale Current)

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Data Sheet ADE9430
TYPICAL PERFORMANCE CHARACTERISTICS

RMS LINEARITY OVER TEMPERATURE AND RMS ERROR OVER FREQUENCY

RMS linearity obtained with a sinusoidal current and voltage with variable amplitudes from 100% of full scale down to 0.01% of full scale using
a frequency of 50 Hz. Total rms error over frequency obtained with a sinusoidal current amplitude of 10% of full scale and voltage amplitude of
50% of full scale. Fundamental rms error over frequency obtained with a sinusoidal current amplitude of 10% of full scale, a voltage amplitude
of 50% of full scale, and a fifth harmonic with a constant amplitude of 40% of fundamental, unless otherwise noted.

Figure 26. Current RMS Error as a Percentage of Full-Scale Current over Figure 28. 10 Cycle Current RMS/12 Cycle Current Error as a Percentage of
Temperature Full-Scale Current over Temperature, Data Sourced Before High-Pass Filter
and Calibrated for Offset, Register CONFIG0, Bit RMS_SRC_SEL = 1

Figure 27. One-Cycle Current RMS Error as a Percentage of Full-Scale

Current over Temperature, Data Sourced Before High-Pass Filter and Figure 29. Fundamental Current RMS Error as a Percentage of Full-Scale
Calibrated for Offset, Register CONFIG0, Bit RMS_SRC_SEL = 1 Current over Temperature

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Data Sheet ADE9430
TYPICAL PERFORMANCE CHARACTERISTICS

Figure 30. One-Cycle Current RMS Error as a Percentage of Full-Scale Figure 33. Fundamental Current RMS Error vs. Line Frequency
Current over Temperature, Data Sourced After High-Pass Filter, Register
CONFIG0, Bit RMS_SRC_SEL = 0

Figure 34. One-Cycle Current RMS Error vs. Line Frequency, Data Sourced
After High-Pass Filter, Register CONFIG0, Bit RMS_SRC_SEL = 0
Figure 31. 10 Cycle Current RMS/12 Cycle Current Error as a Percentage of
Full-Scale Current over Temperature, Data Sourced After High-Pass Filter,
Register CONFIG0, Bit RMS_SRC_SEL = 0

Figure 35. 10 Cycle Current RMS/12 Cycle Current Error vs. Line Frequency,
Data Sourced After High-Pass Filter, Register CONFIG0, Bit RMS_SRC_SEL =
0
Figure 32. Current RMS Error vs. Line Frequency

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Data Sheet ADE9430
TYPICAL PERFORMANCE CHARACTERISTICS

SIGNAL-TO-NOISE RATIO PERFORMANCE

Figure 36. SNR Histogram of ADC SNR for 1000 Devices Tested at TA = 25°C
with PGA_GAIN = 1 and 8 kSPS Data Rate

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Data Sheet ADE9430
TEST CIRCUIT

Figure 37. Test Circuit

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Data Sheet ADE9430
TERMINOLOGY

Crosstalk AC Power Supply Rejection (PSRR)

Crosstalk is measured by grounding one channel and applying a AC PSRR quantifies the measurement error as a percentage of
full-scale 50 Hz or 60 Hz signal on all other channels. The crosstalk reading when the dc power supply is nominal (VNOM) and modu-
is equal to the ratio between the grounded ADC output value and its lated with ac, and the inputs are grounded. For the ac PSRR
ADC full-scale output value. The ADC outputs are acquired for 100 measurement, 20 sec samples are captured with nominal supplies
sec. Crosstalk is expressed in decibels. (3.3 V, which is V1) and a second set (V2) is captured with an
additional ac signal (330 mV peak at 50 Hz) introduced onto the
Differential Input Impedance DC supplies. Then, the PSRR is expressed as PSRR = 20 log10(V2/
The differential input impedance dc represents the impedance be- V1).
tween the IxP and IxN pair or VxP and VxN pair. It varies with the Signal-to-Noise Ratio (SNR)
PGA gain selection as indicated in the Table 1.
SNR is calculated by inputting a 50 Hz signal, and samples are
ADC Offset acquired for 2 sec. The amplitudes for each frequency up to the
ADC offset is the difference between the average measured ADC bandwidth given in as the ADC output bandwidth (−3 dB) are
output code with both inputs connected to GND and the ideal ADC calculated. To determine the SNR, the signal at 50 Hz is compared
output code of zero. ADC offset is expressed in mV. to the sum of the power from all the other frequencies, removing
power from its harmonics. The value for SNR is expressed in
ADC Offset Drift over Temperature decibels.
The ADC offset drift is the change in offset over temperature. It is Signal-to-Noise-and-Distortion Ratio (SINAD)
measured at −40°C, +25°C, and +85°C. Calculate the offset drift
over temperature as follows: SINAD is calculated by inputting a 50 Hz signal, and samples
are acquired for 2 sec. The amplitudes for each frequency up
Drift = to the bandwidth given in as the ADC output bandwidth (−3 dB)
Offset −40°C − Offset +25°C
, are calculated. To determine the SINAD, the signal at 50 Hz is
−40°C − + 25°C (1) compared to the sum of the power from all the other frequencies.
max
Offset +85°C − Offset +25°C The value for SINAD is expressed in decibels.
+85°C − + 25°C
Total Harmonic Distortion (THD)
Offset drift is expressed in µV/°C.
THD is calculated by inputting a 50 Hz signal, and samples are
ADC Gain Error acquired for over 2 sec. The amplitudes for each frequency up
ADC gain error represents the difference between the measured to the bandwidth given in as the ADC output bandwidth (−3 dB)
ADC output code (minus the offset) and the ideal output code when are calculated. To determine the THD, the amplitudes of the 50 Hz
an external voltage reference of 1.2 V is used. The difference is harmonics up to the bandwidth are root sum squared. The value for
expressed as a percentage of the ideal code. It represents the THD is expressed in decibels.
overall gain error of one channel. Spurious-Free Dynamic Range (SFDR)
ADC Gain Drift over Temperature SFDR is calculated by inputting a 50 Hz signal, and samples are
This temperature coefficient includes the temperature variation of acquired for over 2 sec. The amplitudes for each frequency up
the ADC gain while using an external voltage reference of 1.2 V. to the bandwidth given in as the ADC output bandwidth (−3 dB)
It represents the overall temperature coefficient of one current or are calculated. To determine the SFDR, the amplitude of the largest
voltage channel. With an external voltage reference of 1.2 V in use, signal that is not a harmonic of 50 Hz is recorded. The value for
the ADC gain is measured at −40°C, +25°C, and +85°C. Then, the SFDR is expressed in decibels.
temperature coefficient is computed as follows: ADC Output Pass Band
Drift =
The ADC output pass band is the bandwidth within 0.1 dB, resulting
Gain −40°C − Gain +25°C from the digital filtering in the sinc4 and sinc4 + IIR LPF.
Gain( + 25°C) × −40°C − + 25°C
, (2)
max ADC Output Bandwidth
Gain +85°C − Gain +25°C
Gain( + 25°C) × +85°C − + 25°C
The ADC output bandwidth is the bandwidth within −3 dB, resulting
Gain drift is measured in ppm/°C. from the digital filtering in the sinc4 and sinc4 + IIR LPF.

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Data Sheet ADE9430
THEORY OF OPERATION

MEASUREMENTS IC is shown in Figure 38 and datapath for the neutral channel is

shown in Figure 39. See the ADE9430 Technical Reference Manual
Current Channel for additional information.
The ADE9430 has three phase current channels and one neutral
current channel. The phase current channel datapath for IA, IB, and

Figure 38. Current Channel (IA, IB, IC) Datapath

Figure 39. Neutral Current Channel (IN) Datapath

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Data Sheet ADE9430
THEORY OF OPERATION

ADC_REDIRECT Multiplexer The phase calibration range is −15° to +2.25° at 50 Hz and −15° to
+2.7° at 60 Hz.
The ADE9430 provides a multiplexer that allows any ADC output to
be redirected to any digital processing datapath (see Figure 40). Use the following equation to calculate the xPHCALx value for a
given phase correction (φ)° angle. Phase correction (φ)° is positive
By default, each modulator is mapped to its corresponding data- to correct a current that lags the voltage and negative to correct a
path. See the ADE9430 Technical Reference Manual for additional current that leads the voltage, as seen in a current transformer.
information.
sin ϕ – ω + sinω
xPHCALx = sin 2ω – ϕ
× 227 (3)

ω = 2π × fLINE/fDSP
where:
fLINE is the line frequency.
fDSP is 8 kHz.
See the ADE9430 Technical Reference Manual for additional infor-
Figure 40. ADC_REDIRECT Modulator to Digital Datapath Multiplexing mation.

Current Channel Gain, xIGAIN Multipoint Phase and Gain Calibration

The ADE9430 provides current gain calibration registers (AIGAIN, The ADE9430 allows multipoint gain and phase compensation with
BIGAIN, CIGAIN, and NIGAIN), one for each current channel. hysteresis on the IA, IB, and IC current channels. The multipoint
gain and phase compensation is not applied the resampled data.
The current channel gain varies with xIGAIN as shown in the The current channel gain and phase compensation vary as a
following equation: function of the calculated input current rms amplitude in xIRMS.
Current Channel Gain = (1 + (xIGAIN/227)) There are five gain registers (xIGAIN0 to xIGAIN4) and five phase
calibration registers (xPHCAL0 to xPHCAL4) for each channel. Set
See the ADE9430 Technical Reference Manual for additional infor- the MTEN bit in the CONFIG0 register to enable multipoint gain and
mation. phase calibration. MTEN = 0 by default.
IB Calculation Using ICONSEL The gain and phase calibration factor is applied based on
the xIRMS current amplitude and the MTTHR_Lx and the
Write to the ICONSEL bit in the ACCMODE register to calculate MTTHR_Hx register values, as shown in Figure 41.
IB = −IA − IC. This setting can help save the cost of a current
transformer in some 3-wire delta configurations. See the ADE9430 See the ADE9430 Technical Reference Manual for additional infor-
Technical Reference Manual for additional information. mation.

High-Pass Filter
A high-pass filter removes dc offsets for accurate rms and energy
measurements. This filter is enabled by default with a corner fre-
quency of 1.25 Hz.
To disable the high-pass filter on all current and voltage channels Figure 41. Multipoint Phase and Gain Calibration
set the HPFDIS bit in the CONFIG0 register. The corner frequency
is configured with the HPF_CRN bits in the CONFIG2 register. Voltage Channel
See the ADE9430 Technical Reference Manual for additional infor- The ADE9430 has three voltage channels. The datapaths for the
mation. VA, VB, and VC voltage channels are shown in Figure 42. The
xVGAIN registers calibrate the voltage channel of each phase. The
Phase Compensation
xVGAIN registers have the same scaling as the xIGAIN registers.
The ADE9430 provides a phase compensation register for See the ADE9430 Technical Reference Manual for additional infor-
each current channel: APHCALx, BPHCALx, CPHCALx, and mation.
NPHCAL.

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Data Sheet ADE9430
THEORY OF OPERATION

Figure 42. Voltage Channel Datapath

RMS and Power Measurements registers are also updated every 8 kSPS. The fundamental rms is
not available for the neutral channel.
The ADE9430 calculates the total and fundamental values of rms
current, rms voltage, active power, reactive power, and apparent The xRMS and xFRMS value at full scale is 52,702,092 decimals.
power. The fundamental algorithm requires initialization of the net- The total and fundamental rms measurements can be calibrated for
work frequency using the SELFREQ bit in the ACCMODE register gain and offset. Perform gain calibration on the respective current
and the nominal voltage in the VLEVEL register. Calculate the and voltage channel datapath. The following equations indicate how
VLEVEL value according to the following equation: the offset calibration registers modify the result in the corresponding
VLEVEL = x × 1,144,084 rms registers:
Where x is the dynamic range that the nominal input signal is at xRMS = xRMS02 + 215 × xRMOSOS (4)
with respect to full scale.
Where xRMS0 is the initial xRMS register value before offset cali-
For instance, if the signal is at ½ of full scale, x = 2. bration.
VLEVEL = 2 × 1,144,084
xFRMS = xFRMS02 + 215 × xFRMOSOS (5)
See the ADE9430 Technical Reference Manual for additional infor-
mation. The ADE9430 also calculates the rms of the sum of IA + IB +
IC ± IN and stores the result in ISUMRMS. The ISUM_CFG bits
Total and Fundamental RMS in the CONFIG0 register configure the components included in
summation.
The ADE9430 offers the total and fundamental current and voltage
rms measurements on all phase channels. The datapath is shown See the ADE9430 Technical Reference Manual for additional infor-
in Figure 43. mation.

Total and Fundamental Active Power

The ADE9430 offers total and fundamental active power measure-
ments on all channels. To calculate the total active power for Phase
A, see Figure 44.

Figure 43. Filter-Based Total RMS

The total rms calculations, one for each channel (AIRMS, BIRMS, Figure 44. Total Active Power, AWATT, Calculation for Phase A
CIRMS, NIRMS, AVRMS, BVRMS, and CVRMS), are updated
every 8 kSPS. The fundamental rms calculations available in the The active power calculations, one for each channel (AWATT,
AIFRMS, BIFRMS, CIFRMS, AVFRMS, BVFRMS, and CVFRMS BWATT, and CWATT), are updated every 8 kSPS. The fundamental
active power is also updated every 8 kSPS and is available in the

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Data Sheet ADE9430
THEORY OF OPERATION

AFWATT, BFWATT, and CFWATT registers. With full-scale inputs, Total and Fundamental Apparent Power
the xWATT and xFWATT value are 20,694,066 decimals.
The ADE9430 offers the total and fundamental apparent power
Enable the LPF2 (DISAPLPF = 0) for normal operation. Disable measurements on all channels. See Figure 46 for how to calculate
LFP2 by setting DISAPLPF in the CONFIG0 register to obtain the total apparent power for Phase A.
instantaneous total active power. DISAPLPF is zero at reset.
The total and fundamental measurements can be calibrated for gain
and offset. The following equations indicate how the gain and offset
calibration registers modify the results in the corresponding power
registers:
xPGAIN
xWATT = 1 + xWATT0 + xWATTOS (6)
227

xPGAIN Figure 46. Total Apparent Power, AVA, Calculation for Phase A
xFWATT = 1 + xFWATT0
227
(7) The total apparent power calculations, one for each channel AVA,
+ xFWATTOS BVA, and CVA, are updated every 8 kSPS. The fundamental appa-
rent power is also updated every 8 kSPS and is available in the
xPGAIN is a common gain to total and fundamental components of AFVA, BFVA, and CFVA registers. With full-scale inputs, the xVA
active, reactive, and apparent powers. and xFVA value are 20,694,066 decimals.
See the ADE9430 Technical Reference Manual for additional infor- The ADE9430 offers a register (VNOM) that can be set to a value to
mation. correspond to the desired voltage rms value. If the VNOMx_EN bits
in the CONFIG0 register are set, VNOM multiplies by xIRMS when
Total and Fundamental Reactive Power calculating xVA.
The ADE9430 offers the total and fundamental reactive power See the ADE9430 Technical Reference Manual for additional infor-
measurements on all channels. Figure 45 shows how to perform mation.
the total reactive power calculation.
No Load Detection, Energy Accumulation, and
Power Accumulation Features
The ADE9430 calculates the total and fundamental values of ac-
tive, reactive, and apparent energy for all the three phases. The
ADE9430 can have signed, absolute, positive, or negative only
Figure 45. Total Reactive Power, AVAR, Calculation accumulation on active and reactive energies using the WATTACC
and VARACC bits in the ACCMODE register. The default accumu-
The reactive power calculations, one for each channel AVAR, lation mode is signed. See the ADE9430 Technical Reference
BVAR, and CVAR, are updated every 8 kSPS. The fundamental Manual for additional information.
reactive power is also updated every 8 kSPS and is available in the
AFVAR, BFVAR, and CFVAR registers. With full-scale inputs, the No Load Detection Feature
xVAR and xFVAR value are 20,694,066.
The ADE9430 has a no load detection for each phase and energy
Enable the LPF2 (DISRPLPF = 0) for normal operation. Disable to prevent energy accumulation due to noise. If the accumulated
LFP2 by setting DISRPLPF in the CONFIG0 register to obtain energy over the user defined time period is below the user defined
instantaneous total reactive power. DISRPLPF is 0 at reset. threshold, zero energy is accumulated into the energy register.
The NOLOAD_TMR bits in the EP_CFG register determine the
The following equations indicate how the gain and offset calibration no load time period and the ACT_NL_LVL, REACT_NL_LVL, and
registers modify the result in the corresponding power registers: APP_NL_LVL registers contain the user defined no load threshold.
xPGAIN The no load status is available in the PHNOLOAD register, the
xVAR = 1 + xVAR0 + xVAROS (8)
227 IRQ1 interrupt, and the EVENT pin.

xFVAR = 1 + xPGAIN
xFVAR0 + xFVAROS See the ADE9430 Technical Reference Manual for additional infor-
(9)
227 mation.
See the ADE9430 Technical Reference Manual for additional infor-
mation.

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Data Sheet ADE9430
THEORY OF OPERATION

Energy Accumulation After EGY_TIME + 1 samples or half line cycles, the EGYRDY bit
is set in the STATUS0 register and the energy register is updated.
The energy is accumulated into a 42-bit signed internal energy The data from the internal energy register is added or latched to the
register at 8 kSPS. The internal register can accumulate a user user energy register depending on the EGY_LD_ACCUM bit setting
defined number of samples or half line cycles configured by in the EP_CFG register.
EGY_TMR_MODE bit in the EP_CFG register. When half line
cycle accumulation is enabled, configure the zero-crossing source The energy register is signed and is 45 bits wide, split between two
using the ZX_SEL bits in the ZX_LP_SEL register. The number 32-bit registers, as shown in Figure 47. The user energy can reset
of samples or half line cycles is set in the EGY_TIME register. on a read using the RD_RST_EN bit in the EP_CFG register. With
The maximum value of EGY_TIME is 8191d. With full-scale inputs, full-scale inputs, the user energy register overflows in 106.3 sec.
the internal register overflows in 13.3 sec. For a 50 Hz signal, See the ADE9430 Technical Reference Manual for additional infor-
EGY_TIME must be lower than 1329 decimals to prevent overflow mation.
during half line cycle accumulation.

Figure 47. Internal Energy Register to AWATTHR_HI and AWATTHR_LO

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Data Sheet ADE9430
THEORY OF OPERATION

Power Accumulation The ADE9430 allows the user to accumulate total active power
and VAR powers into separate positive and negative values into
The ADE9430 accumulates the total and fundamental values of the PWATT_ACC and NWATT_ACC, and PVAR_ACC and NVAR_
active, reactive, and apparent power for all the three phases ACC registers. A new accumulation from zero begins when the
into respective xWATT_ACC and xFWATT_ACC, xVAR_ACC and power update interval set in PWR_TIMER elapses.
xFVAR_ACC, and xVA_ACC, and xFVA_ACC 32-bit signed reg-
isters. The number of samples accumulated is set using the See the ADE9430 Technical Reference Manual for additional infor-
PWR_TIME register. The PWRRDY bit in the STATUS0 register mation.
is set after PWR_TIME + 1 samples accumulate at 8 kSPS. The
maximum value of the PWR_TIME register is 8191 decimals, and Digital to Frequency Conversion—CFx Output
the maximum power accumulation time is 1.024 sec.
The ADE9430 includes four pulse outputs that are proportional
The xSIGN bits in the PHSIGN register indicate the sign of to the energy accumulation in the CF1 through CF4 output pins.
accumulated powers over the PWR_TIME interval. The PWR_ Figure 48 shows a block diagram of the CFx pulse generation. CF3
SIGN_SEL[1:0] bits allow the user to select whether the power sign is multiplexed with ZX, and CF4 is multiplexed with EVENT and
change follows the total or fundamental energies. When sign of the DREADY.
accumulated power changes, the corresponding REVx bits in the
STATUS0 register are set and IRQ0 generates an interrupt. See the ADE9430 Technical Reference Manual for additional infor-
mation.

Figure 48. Digital to Frequency Conversion for CFx

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Data Sheet ADE9430
THEORY OF OPERATION

Energy and Phase Selection not contain a zero-crossing detection circuit. Figure 49 and Figure
50 show the current and voltage channel datapaths preceding
The CFxSEL bits in the CFMODE register select which type of zero-crossing detection.
energy to output on the CFx pins. The TERMSELx bits in the
COMPMODE register select which phase energies to include in the Use the ZX_SRC_SEL bit in the CONFIG0 register to select data
CFx output. before the high-pass filter or after phase compensation to configure
the inputs to zero-crossing detection. ZX_SRC_SEL is zero by
For example, with CF1SEL = 000 and TERMSEL1 = 111, CF1 default after reset.
indicates the total active power output of Phase A, Phase B, and
Phase C. To provide protection from noise, voltage channel zero-crossing
events (ZXVA, ZXVB, and ZXVC) do not generate if the absolute
See the ADE9430 Technical Reference Manual for additional infor- value of the LPF1 output voltage is smaller than the threshold,
mation. ZXTHRSH. The current channel zero-crossing detection outputs
(ZXIA, ZXIB, and ZXIC) are active for all input signals levels.
Configuring the CFx Pulse Width
Calculate the zero-crossing threshold, ZXTHRSH, from the follow-
The value of the CFx_LT and the CF_LTMR bits in the CF_LCFG ing equation:
register determines the pulse width.
ZXTHRSH =
The maximum CFx with threshold (xTHR) = 0x00100000 and
CFxDEN = 2 is 78.9 kHz. It is recommended to have xTHR = V_PCF at Full Scale × LPF1 Attenuation
(10)
0x00100000. x × 32 × 28

See the ADE9430 Technical Reference Manual for additional infor- where:
mation. V_PCF at Full Scale is ±74,532,013 decimal.
LPF1 Attenuation is 0.86 at 50 Hz and 0.81 at 60 Hz.
CFx Pulse Sign x is the dynamic range below which the voltage channel zero-cross-
ing must be blocked.
The SUMxSIGN bits in the PHSIGN register indicate whether the
sum of the energy that went into the last CFx pulse is positive or The ADE9430 can calculate the combined zero crossings for all
negative. The REVPSUMx bits in the STATUS0 register and the three phases as (VA + VB − VC)/2 by configuring the ZX_SEL bits
EVENT_STATUS register indicate if the CFx polarity changed sign. in the ZX_LP_SEL register. If VCONSEL is not equal to 0, the VB
This feature generates an interrupt on IRQ0. component in the combined zero-crossing circuit is set to zero.
See the ADE9430 Technical Reference Manual for additional infor- The zero-crossing detection circuits have two different output rates:
mation. 8 kSPS and 1024 kSPS. The 8 kSPS zero-crossing signal calcu-
lates the line period, updates the ZXx bits in the STATUS1 register,
Clearing the CFx Accumulator and monitors the zero-crossing timeout, phase sequence error de-
tection, resampling, and energy accumulation functions. The 1024
To clear the accumulation in the digital to frequency converter and kSPS zero-crossing signal calculates the angle and updates the
CFDEN counter, write 1 to the CF_ACC_CLR bit in the CONFIG1 zero-crossing output on the CF3/ZX pin.
register. The CF_ACC_CLR bit automatically clears itself. See the
ADE9430 Technical Reference Manual for additional information. See the ADE9430 Technical Reference Manual for additional infor-
mation.
POWER QUALITY MEASUREMENTS

Zero-Crossing Detection
The ADE9430 offers zero-crossing detection on the VA, VB, VC,
IA, IB, and IC input signals. The neutral current channel, IN, does

Figure 49. Voltage Channel Signal Chain Preceding Zero-Crossing Detection

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Data Sheet ADE9430
THEORY OF OPERATION

Figure 50. Current Channel Signal Chain Preceding Zero-Crossing Detection

CF3/ZX Angle Measurement

The CF3/ZX pin can output zero crossings using the CF3_CFG bit The ADE9430 provides nine angle measurements. ANGL_IA_IB,
in the CONFIG1 register. To configure the source for zero crossing, ANGL_IB_IC, and ANGL_IA_IC provide phase angle between cur-
use the ZX_SEL bits in ZX_LP_SEL register. The CF3/ZX output rents. ANGL_VA_VB, ANGL_VB_VC, and ANGL_VA_VC provide
pin goes from low to high when a negative to positive transition is phase angle between voltages. ANGL_VA_IA, ANGL_VB_IB, and
detected and from high to low when a positive to negative transition ANGL_VC_IC provide phase angle between voltage and currents.
occurs. To convert angle register reading to degrees, use the following
equations.
See the ADE9430 Technical Reference Manual for additional infor-
mation. For a 50 Hz system,

Zero-Crossing Timeout Angle (Degrees) = ANGL_x_y × 0.017578125

If a zero crossing is not received after (ZXTOUT + 1)/8000 sec, For a 60 Hz system,
the corresponding ZXTOx bit in the STATUS1 register is set and Angle (Degrees) = ANGL_x_y × 0.02109375
generates an interrupt on the IRQ1 pin.
See the ADE9430 Technical Reference Manual for additional infor-
See the ADE9430 Technical Reference Manual for additional infor- mation.
mation.
Phase Sequence Error Detection
Line Period Calculation
The ADE9430 monitors phase sequences and sets the SEQERR
The ADE9430 calculates the line period for the Phase A, Phase B, bit in the STATUS1 register if a sequence error occurs or a phase
and Phase C voltages and the combined voltage signal, and the drops below ZXTHRSH. SEQ_CYC determines the number of
results are available in the APERIOD, BPERIOD, CPERIOD, and cycles to monitor to generate the sequence error. To generate an
COM_PERIOD registers, respectively. interrupt on IRQ1, set the SEQERR bit in the MASK1 register.
Calculate the line period, tL, from the xPERIOD register, according See the ADE9430 Technical Reference Manual for additional infor-
to the following equation: mation.
xPERIOD + 1
tL = (sec) (11)
8000 × 216 One-Cycle RMS Measurement
If the calculated period value is outside the 40 Hz to 70 Hz range, One-cycle rms is an rms measurement performed over one line
or if zero crossings for that phase are not detected, the xPERIOD cycle, updated every period not synchronized to zero crossings.
register is coerced to correspond to 50 Hz or 60 Hz, depending on This measurement is provided for voltage and current on all phases
SELFREQ bit in the ACCMODE register. plus the neutral current. All the one cycle rms measurements are
performed over the same time interval and update at the same
See the ADE9430 Technical Reference Manual for additional infor- time, as indicated by the RMSONERDY bit in the STATUS0 regis-
mation. ter. The results are stored in the AIRMSONE, BIRMSONE, CIRM-
SONE, NIRMSONE, AVRMSONE, BVRMSONE, and CVRMSONE
registers. The xRMSONE register reading with full-scale inputs is
52,702,092d.
It is recommended to select the data before the high-pass filter for
the one cycle measurement by setting the RMS_SRC_SEL bit in
the CONFIG0 register.
Figure 51. Line Period Selection for Resampling

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Data Sheet ADE9430
THEORY OF OPERATION

The LP_SEL bits in the ZX_LP_SEL register select which line peri- The signal chain is shown in Figure 52.
od measurement sets the number of samples used in the one cycle
rms measurement. Alternatively, set the UPERIOD_SEL bit in the See the ADE9430 Technical Reference Manual for additional infor-
CONFIG2 register to set the desired period in the USER_PERIOD mation.
register for line period measurement. An offset correction register
is available for improved performance with small input signal levels,
xRMSONEOS.

Figure 52. One Cycle RMS, 10 Cycle RMS, and 12 Cycle RMS Measurements

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Data Sheet ADE9430
THEORY OF OPERATION

10 Cycle RMS/12 Cycle RMS the total or fundamental reactive energy and the sign of the xPF or
xWATT value, as indicated in Figure 53.
The 10 cycle rms/12 cycle rms measurement is performed over
10 cycles on a 50 Hz network or 12 cycles on a 60 Hz network. See the ADE9430 Technical Reference Manual for additional infor-
The SELFREQ bit in the ACCMODE register selects whether the mation.
network is 50 Hz or 60 Hz. Then, the UPERIOD_SEL bit in the
CONFIG2 register selects whether to use a measured line period
or a user configured value in the USER_PERIOD register to set the
number of samples used in the calculation.
An offset correction register is available for improved performance
with small input signal levels, xRMS1012OS. The xRMS1012 regis-
ter reading with full-scale inputs is 52,702,092d.
The signal chain is shown in Figure 52. See the ADE9430 Technical
Reference Manual for additional information.

Overcurrent Indication
The ADE9430 monitors the one cycle value on current channels to Figure 53. Active Power and VAR Sign for Capacitive and Inductive Loads
determine overcurrent events. If a one cycle rms current is greater
than the user configured threshold in the OILVL register, the OI bit The power factor result is stored in 5.27 format. The highest power
in the STATUS1 register is set. The overcurrent event generates an factor value is 0x07FF FFFF, which corresponds to a power factor
interrupt on the IRQ1 pin. of 1. A power factor of −1 is stored as 0xF800 0000. To determine
the power factor from the xPF register value, use the following
The OC_EN bits in the CONFIG3 register select which phases to equation:
monitor for overcurrent events. The OIPHASE bits in the OISTATUS
register indicate which current channels exceeded the threshold. Power Factor = xPF × 2−27
The overcurrent value is stored in the corresponding OIA, OIB, or
OIC registers. Total Harmonic Distortion (THD)
See the ADE9430 Technical Reference Manual for additional infor- A THD calculation is available on the IA, IB, IC, VA, VB, and VC
mation. channels in the ADSW-PQ-CLS Power Quality Library. To request
access to the ADSW-PQ-CLS, fill out the software request form at:
Peak Detection Software Request Form | Analog Devices, where the target technol-
ogy must be power quality monitoring and the processor/system on
The ADE9430 records the peak value measured on the current and chip (SoC) is the ADE9430.
voltage channels from the xI_PCF and xV_PCF waveforms. The
PEAKSEL bits in the CONFIG3 register allow the user to select Resampling
which phases to monitor.
The ADE9430 resamples the input data to provide 1024 points
The IPEAK register stores the peak current value in the IPEAKVAL for 10/12 cycles, selected by SELFREQ. The resampled data is
bits and indicates which phase currents reached the value in the available for all current channels and voltage channels in the
IPPHASE bits. IPEAKVAL is equal to xI_PCF/25. waveform buffer. Each resampled waveform sample is stored as
Similarly, VPEAK stores the peak voltage value in the VPEAKVAL a 16-bit signed integer in the waveform buffer. See the ADE9430
bits. VPEAKVAL is equal to xV_PCF/25. After a read, the VPEAK Technical Reference Manual for additional information.
and IPEAK registers reset.
Temperature
See the ADE9430 Technical Reference Manual for additional infor-
mation. The temperature reading is available in the TEMP_RSLT register.
To convert the temperature range into Celsius, use the following
Power Factor equation:
The power factor calculation, one for each channel (APF, BPF, and Temperature (°C) = TEMP_RSLT × (−TEMP_GAIN/65536) +
CPF), is updated every 1.024 sec. (TEMP_OFFSET/32)
The sign of the APF calculation follows the sign of AWATT. To During manufacturing of each device, the TEMP_GAIN and
determine if power factor is leading or lagging, refer to the sign of TEMP_OFFSET bits of Register TEMP_TRIM are programed. To

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Data Sheet ADE9430
THEORY OF OPERATION

configure the temperature sensor, program the TEMP_CFG regis-

ter. See the ADE9430 Technical Reference Manual for additional
information.

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Data Sheet ADE9430
APPLICATIONS INFORMATION

The ADE9430 SPI port calculates a 16-bit cyclic redundancy check

WAVEFORM BUFFER (CRC-16) of the data sent out on its MOSI pin so that the integrity
The ADE9430 has a waveform buffer comprised of 2048, 32-bit of the data received by the main can be checked. The CRC of
memory locations. the data sent out on the MOSI pin during the last register read is
offered in a 16-bit register, CRC_SPI, and can be appended to the
Continuous resampled waveforms with 1024 points per 10 or 12 SPI read data as part of the SPI transaction.
line cycles processed by the DSP. The data rate varies with the
line period. The waveform buffer holds approximately 100 ms of Additional Communication Verification
waveform data per channel. Registers
Use the SPI burst read mode to read the waveform buffer contents. The ADE9430 includes three registers that allow SPI operation
The default value bursts out all the channels in the waveform buffer. verification. The LAST_CMD (Address 0x4AE), LAST_DATA_16
The waveform buffer generates an interrupt on IRQ0 after half the (Address 0x4AC), and LAST_DATA_32 (Address 0x423) registers
buffer is full and the last address is filled. The DSP must be on to record the received CMD_HDR and the last read or transmitted
use the waveform buffer. data. See the ADE9430 Technical Reference Manual for additional
information.
See the ADE9430 Technical Reference Manual for additional infor-
mation. CRC of Configuration Registers
INTERRUPTS AND EVENTS The configuration register CRC feature in the ADE9430 monitors
The ADE9430 has three pins (IRQ0, IRQ1, and CF4/EVENT/ certain externally and internally accessible register values. It also
DREADY) that can be used as interrupts to the host processor. The optionally includes 15 registers that are individually selectable in
IRQ0 and IRQ1 pins go low when an enabled interrupt occurs and the CRC_OPTEN register. The result is stored in the CRC_RSLT
stay low until the event is acknowledged by setting the correspond- register. The ADE9430 generates an interrupt on IRQ1 if any of the
ing status bit in the STATUS0 and STATUS1 registers, respectively. monitored registers change the value of the CRC_RSLT register.
The bits in the MASK0 and MASK1 registers configure respective See the ADE9430 Technical Reference Manual for additional infor-
interrupts. The EVENT function, which can multiplex with the CF4 mation.
and DREADY options, tracks the state of the enabled signals and
goes low and high with these internal signals. The CF4_CFG bits in Configuration Lock
CONFIG1 register set the CF4/EVENT/DREADY pin functionality.
The configuration lock feature prevents changes to the ADE9430
See the ADE9430 Technical Reference Manual for additional infor- configuration. To enable this feature, write 0x3C64 to the
mation. WR_LOCK register. To disable the feature, write 0x4AD1 to the
ACCESSING ON-CHIP DATA WR_LOCK register.
To determine whether this feature is active, read the WR_LOCK
SPI Protocol Overview register, which reads as 1 if the protection is enabled and 0 if it is
The ADE9430 has an SPI-compatible interface, consisting of four disabled.
pins: SCLK, MOSI, MISO, and SS. The ADE9430 is always an When this feature is enabled, it prevents writing to addresses from
SPI subordinate; it never initiates SPI communication. The SPI Address 0x000 to Address 0x073 and Address 0x400 to Address
is compatible with 16-bit and 32-bit read and write operations. 0x4FE. See the ADE9430 Technical Reference Manual for addition-
The maximum serial clock frequency supported by this interface is al information.
20 MHz.
The ADE9430 provides SPI burst read functionality on certain
registers and the waveform buffer that allows multiple registers to
be read after sending one CMD_HDR.
See the ADE9430 Technical Reference Manual for additional infor-
mation.

Figure 54. Command Header, CMD_HDR

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Data Sheet ADE9430
OUTLINE DIMENSIONS

Figure 55. 40-Lead Lead Frame Chip Scale Package [LFCSP]

6 mm × 6 mm Body and 0.75 mm Package Height
(CP-40-7)
Dimensions shown in millimeters

Updated: May 16, 2022

ORDERING GUIDE
Package
Model1 Temperature Range Package Description Packing Quantity Option
ADE9430ACPZ −40°C to +85°C 40-Lead LFCSP (6 mm × 6 mm with EPAD) Tray, 490 CP-40-7
ADE9430ACPZ-RL −40°C to +85°C 40-Lead LFCSP (6 mm × 6 mm with EPAD) Reel, 2500 CP-40-7
1 Z = RoHS Compliant Part.

EVALUATION BOARDS
Model1 Description
EVAL-ADE9430ARDZ Evaluation Board
1 Z = RoHS Compliant Part.

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registered trademarks are the property of their respective owners.
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