Misr University for Science and Technology

Faculty of Engineering
Electronics and communications Department

Electronics II
(ECE 202)

Lecture (7)
DC JFET Biasing
• Just as we learned that the BJT must be biased for
proper operation, the JFET also must be biased for
operation point (ID, VGS, VDS)
• In most cases the ideal Q-point will be at the middle
of the transfer characteristic curve, which is about
half of the IDSS.
• 3 types of DC JFET biasing configurations :
• Fixed-bias
• Self-bias
• Voltage-Divider Bias
Fixed-bias
+ VDD • Use two voltage
sources: VGG, VDD
RD • VGG is reverse-
C2
biased at the Gate
+
– Source (G-S)
C1 + terminal, thus no
current flows
VDS
_

RG
+
+ VGS
_ Vout through RG (IG = 0).
Vin
_ VGG _

Fixed-bias
Fixed-bias..
• DC analysis
• All capacitors replaced with open-circuit
VDD

RD

+
VDS
_
+ VGS
RG _

Loop 1
VGG
Fixed-bias…
1. Input Loop
• By using KVL at loop 1:
VGG + VGS = 0
VGS = - VGG

• For graphical solution, use VGS = - VGG to draw the load line
• For mathematical solution, replace VGS = -VGG in Shockley’s Eq. ,therefore:

2 2
𝑉𝐺𝑆 𝑉𝐺𝐺
𝐼𝐷 = 𝐼𝐷𝑆𝑆 1 − = 𝐼𝐷𝑆𝑆 1 +
𝑉𝐺𝑆 (𝑜𝑓𝑓) 𝑉𝐺𝑆 (𝑜𝑓𝑓)

2. Output loop
- VDD + IDRD + VDS = 0
VDS = VDD – IDRD
Example : Fixed-bias

Determine the following Network, given

IDSS=10mA & Vp=8V

1. VGSQ
2. IDQ
3. VD
4. VG
5. VS
Mathematical Solutions
VGSQ = −VGG = −2

VDS = VDD − ID R D = 16 − 5.625mA 2kΩ

= 16V − 11.25V = 4.75V
Graphical solution for the network
Draw load line for:

VGSQ = −VGG = −2

VDS = 4.75V

VD = 4.75V
VG = −2V
VS = 0V
Self-bias
• Using only one voltage source
DC analysis of the self-bias configuration.

Since IG ≈ 0A,
thus VRG = 0𝐕,

Q point for VGS

Graphical Solutions:
Sketching the self-bias line.

IDSS
ID =
2

VGS = −ID R S
IDSS R S
=−
2

VDS = VDD − ID R S + R D

VS = ID R S
Mathematical Solutions:

• Replace in the Shockley’s Equation:

2
𝑉𝐺𝑆
𝐼𝐷 = 𝐼𝐷𝑆𝑆 1 −
𝑉𝐺𝑆(𝑜𝑓𝑓)
𝑡ℎ𝑒𝑟𝑒𝑓𝑜𝑟𝑒;
2
(−𝐼𝐷 𝑅𝑆 )
𝐼𝐷 = 𝐼𝐷𝑆𝑆 1−
𝑉𝐺𝑆(𝑜𝑓𝑓)
• By using, quadratic equation and formula, choose value of ID that relevant within the
range (0 to IDSS): nearly to IDSS/2

• Find VGS by using ;also choose VGS that within the range (0 to VGS(off))
Example : Self-bias configuration

Determine the following for the network,

given IDSS=8mA & Vp=6V

1. VGSQ
2. IDQ
3. VD
4. VG
5. Vs
Graphical Solution:

𝑾𝒉𝒆𝒏 𝑰𝑫 = 𝟎𝒎𝑨, 𝑽𝑮𝑺 = 𝟎𝑽

Sketching the self-bias line

− When ID = 0mA, VGS = 0V

- When ID = 4mA, VGS = −4V
Graphical Solutions: Determining the Q-point

IDQ=2.6mA
VGSQ=-2.6mV

Q-point
Mathematical Solution: 𝑉𝐺𝑆
2
𝐼𝐷 = 𝐼𝐷𝑆𝑆 1 − 𝑟𝑒𝑐𝑎𝑙𝑙 𝑉𝐺𝑆 = −𝐼𝐷 𝑅𝑆
𝑉𝐺𝑠(𝑜𝑓𝑓)
2
(−𝐼𝐷 𝑅𝑆 )
= 𝐼𝐷𝑆𝑆 1 −
𝑉𝐺𝑆(𝑜𝑓𝑓)
2 2
𝐼𝐷 (1𝑘) −6 + 𝐼𝐷 (1000)
𝐼𝐷 = 0.008 1 + = 0.008
−6 −6
0.008
= 36 − 12000 𝐼𝐷 + 1000000 𝐼𝐷 2
36
36𝐼𝐷 = 0.288 − 96𝐼𝐷 + 8000 𝐼𝐷 2
8000 𝐼𝐷 2 − 132𝐼𝐷 + 0.288 = 0
𝐼𝐷1 = 13.9𝑚𝐴 & 𝐼𝐷21 = 2.588𝑚𝐴
𝑉𝐺𝑆 = −𝐼𝐷 𝑅𝑆 = −13.9𝑚𝐴 1𝑘 = −13.9𝑉
𝑜𝑟 𝑉𝐺𝑆 = −𝐼𝐷 𝑅𝑆 = −2.588𝑚𝐴(1𝑘) = −2.6𝑉

𝑡ℎ𝑒𝑟𝑒𝑓𝑜𝑟𝑒; 𝑐ℎ𝑜𝑜𝑠𝑒𝐼𝐷 = 2.588 𝑚𝐴 & 𝑉𝐺𝑆 = −2.6𝑉

 VGSQ = −2.6V
Solution IDQ = 2.6mA

ID=IS
VDS = VDD − ID R D + R S
= 20V − 2.6mA 4.3kΩ
= 8.82V
Voltage-divider bias

IG=0A

A
Redrawn network

R2
VG = V
R1 + R 2 DD

Apply KVL:
−VG + VGS + VRS = 0
VGS = VG − VRS
VGS = VG − ID R S
 Sketching the network equation for the voltage-divider
configuration.

VGS = VG ቚ
I D =0mA
−VG + VGS + VRS = 0 VG
VGS = VG − VRS ID = ቤ
RS V
VGS = VG − ID R S GS =0V
Effect of RS on the resulting
Q-point.
Example : Voltage-divider bias
Determine the following for the network, given
IDSS=8mA & Vp=4V

1. IDQ andVGSQ
2. VD
3. VS
4. VDS
5. VDG
Solutions VG =
R2
V
R1 + R 2 DD
270kΩ 16V
= V
2.1MΩ + 0.27MΩ2 DD
= 1.82V

VGS = VG − ID R S
= 1.82V − ID 1.5kΩ c

When ID = 0mA, VGS = +1.82V

+1.82V
When VGS = 0V, ID =
1.5kΩ
 Determining the Q-point for the network

VGS = 1.82V − ID 1.5kΩ

IDQ=2.4mA
VDS = VDD + VSS − ID R S + R D
VGSQ=-1.8V
= VDS + VS = 8.82V + 2.6V
= 11.42V
Mathematical solution:
• How to get IDS, VGS and VDS for voltage-divider bias configuration by
using mathematical solution?

VGS = VG − ID R S
= 1.82V − ID 1.5kΩ

2
𝑉𝐺𝑆 1.82−1500 ID 2
𝐼𝐷 = 𝐼𝐷𝑆𝑆 1 − 𝑉 = 0.008 1 + =0.0005 5.82 − 1500 𝐼𝐷 2
𝐺𝑆 (𝑜𝑓𝑓) 4
1125 𝐼𝐷2 - 9.73 𝐼𝐷 +0.01694=0
𝐼𝐷1 = 2.359 mA OR 𝐼𝐷2 =6.29 mA
𝑉𝐺𝑆1 = -1.7185 V OR 𝑉𝐺𝑆2 = -7.615 V
𝑉𝐺𝑆2 is rejected since it is larger than 𝑉𝐺𝑆(𝑜𝑓𝑓)

𝐼𝐷 = 2.359 mA & 𝑉𝐺𝑆 = -1.7185 V

Exercise 3: Determine the following for the network, given IDSS=9 mA & Vp=3V

1. IDQ andVGSQ
2. VDS
3. VD
4. VS
Drawing the self bias line

VGS + ID R S − 10V = 0

VGS = 10V − ID 1.5kΩ

When ID = 0mA, VGS = 10V

10V
When VGS = 0V, ID = = 6.67mA
1.5kΩ
Determining the Q-point IDQ=6.9mA
VGSQ=-0.35V

VDS = VDD − VSS − ID R S + R D

= 20 + 10 − (6.9mA)(1.8kΩ + 1.5kΩ)
= 7.23V

VD = VDD − ID R D = 7.58V

VS = VD − VDS
= 7.58V − 7.23V = 0.35V
 Determine the required values of R D and R S, given IDSS=6 mA & Vp=3V
Example:

2
𝑉𝐺𝑆
𝐼𝐷 = 𝐼𝐷𝑆𝑆 1 −
𝑉𝐺𝑆 (𝑜𝑓𝑓)
2
2.5 𝑉𝐺𝑠
= 1+
6 3
2.5
3( − 1)= 𝑉𝐺𝑠 =-1.0635 V
6

𝑉𝐺𝑠 =-1.0635 V=-ID RS

Rs=1.0635/2.5= 425.4 Ω

VRD VDD − VDQ 20V − 12V

RD = = =
IDQ IDQ 2.5mA
= 3.2kΩ
 The MOSFET
The metal oxide semiconductor field effect transistor (MOSFET) is the second category of FETs. The main
difference is that there no actual pn junction as the p and n materials are insulated from each other.
MOSFETs are static sensitive devices and must be handled by appropriate means.
There are depletion MOSFETs (D-MOSFET) and enhancement MOSFETs (E-MOSFET). Note the
difference in construction. The E-MOSFET has no structural channel.

Representation of the basic E-MOSFET

Representation of the basic structure of D-MOSFETs.
construction and operation (n-channel).
 The MOSFET – Depletion MOSFET
The D-MOSFET can be operated in either of two modes – the depletion mode or
enhancement mode – and is sometimes called a depletion/enhancement MOSFET. Since
the gate is insulated from the channel, either positive or a negative gate voltage can be
applied. The n-channel MOSFET operates in the depletion mode when a negative gate-to-
source voltage is applied and in the enhancement mode when a positive gate-to-source
voltage is applied. These devices are generally operated in the depletion mode.
 The MOSFET – Depletion MOSFET
Depletion Mode With a negative gate voltage, the negative charges on the gate repel
conduction electrons from the channel, leaving positive ions in their place. Thereby, the n
channel is depleted of some of its electrons, thus decreasing the channel conductivity. The
greater the negative voltage on the gate, the greater the depletion of n-channel electrons. At
sufficiently negative gate-to-source voltage, VGS(off), the channel is totally depleted and drain
current is zero.

Enhancement Mode With a

positive gate voltage, more
conduction electrons are attracted
into the channel, thus increasing
(enhancing) the channel
conductivity.
Source

D-MOSFET schematic symbols.

The MOSFET – Enhancement MOSFET (E-MOSFET)
The E-MOSFET operates only in the enhancement mode and has no depletion mode. It differs in
construction from the D-MOSFET in that it has no structural channel. Notice in Figure (a) that the
substrate extends completely to the SiO2 layer. For n-channel device, a positive gate voltage above
threshold value induces a channel by creating a thin layer of negative charges in the substrate
region adjacent to the SiO2 layer, as shown in Figure (b).

Representation of the basic E-

MOSFET construction and
operation (n-channel).
 D-MOSFET Transfer Characteristic
As previously discussed, the D-MOSFET can operate with either positive or negative gate
voltages. This is indicated on the general transfer characteristic curves in Figure for both
n-channel and p-channel MOSFETs. The point on the curves where VGS = 0 corresponds
to IDSS. The point where ID = 0 corresponds to VGS(off). As with the JFET, VGS(off) = -VP.

D-MOSFET general transfer

characteristic curves.
 Ex. For a certain D-MOSFET, IDSS = 10 mA and VGS(off) = - 8 V.
(a) Is this an n-channel or a p-channel?
(b) Calculate ID at VGS = - 3 V
(c) Calculate ID at VGS = + 3 V.

(a) The device has a negative VGS(off);

therefore, it is a n-channel MOSFET.

2
 
2

 V   − 3V 
(b) I D = I DSS 1 − GS
= (10 mA)1 −  = 3.91 mA
 V   − 8V 
 GS ( off ) 

2
 + 3V 
(c) I D = (10 mA)1 −  = 18.9 mA
 − 8V 
 E-MOSFET Transfer Characteristic
The E-MOSFET for all practical purposes does not conduct until VGS reaches the threshold
voltage (VGS(th)). ID when it is when conducting can be determined by the formulas below. The
constant K must first be determined. ID(on) is a data sheet given value.
K = ID(on) /(VGS - VGS(th))2
ID = K(VGS - VGS(th))2

An n-channel device requires

a positive gate-to-source
voltage, and a p-channel
device requires a negative
gate-to-source voltage.

E-MOSFET general transfer

characteristic curves.
Ex.The data sheet for a 2N7008 E-MOSFET gives ID(o n)= 500 mA (minimum) at VGS = 10 V and
VGS(th) = 1 V. Determine the drain current for VGS = 5 V.

First, solve for K using Equation,

I D ( on ) 500 mA 500 mA
K= = = = 6.17 mA / V 2

(VGS − VGS (th ) ) 2 (10V − 1V )2 81V 2

Next, using the value of K, calculate ID for VGS = 5 V.

I D = K (VGS − VGS ( th ) ) 2 = (6.17 mA / V 2 )(5V − 1V ) 2 = 98.7 mA

 MOSFET Biasing – D-MOSFET Bias
The three ways to bias a MOSFET are zero-bias, voltage-divider bias, and drain-feedback bias.
For D-MOSFET zero biasing as the name implies has no applied bias voltage to the gate. The
input voltage swings it into depletion and enhancement mode.

Since VGS = 0, ID = IDSS

as indicated.

VDS = VDD - IDSSRD

Ex. Determine the drain-to-source voltage in the circuit of Figure. The MOSFET data sheet
gives VGS(off) = - 8 V and IDSS = 12 mA.

Since ID = IDSS = 12 mA,

the drain-to-source voltage is

560 Ω
VDS = VDD – IDSSRD
= 18 V – (12 mA)(560Ω)
= 11.28 V
_

MΩ
MOSFET Biasing- voltage divider
bias
For E-MOSFETs zero biasing cannot be used.
Voltage-divider bias must be used to set the VGS
greater than the threshold voltage (VGS(th)). ID
can be determined as follows. To determine VGS,
normal voltage divider methods can be used.
The following formula can be applied.
VGS = (R2 / (R1+R2))VDD
VDS = VDD - IDRD
K = ID(on)/(VGS - VGS(th))2
ID = K(VGS -VGS(th))2
VDS can be determined by application of Ohm’s law
and Kirchhoff’s voltage law to the drain circuit.
41
MOSFET Biasing- drain feedback
bias

With drain-feedback bias there is

no voltage drop across RG making
VGS = VDS. With VGS given
determining ID can be
accomplished by the formula
below.
ID = (VDD – VDS)/RD

42