OVERVIEW

 Introduction of Field Effect Transistor (FET)

• JFET
• MOSFET

Junction Field Effect Transistor (JFET)

 Operation of JFET
 Characteristic of JFET
 Parameter of JFET
 Analyzed How JFETs are Biased
N channel P channel
Metal Oxide Semi conductor Field Effect Transistor (MOSFET)
 Operation of MOSFET
 Characteristic of MOSFET E
 Parameter of MOSFET
 Analyzed How MOSFETs are Biased

D
1
OVERVIEW Transistor

Bi-Polar Junction Field Effect

Transistor Transistor
( BJT) (FET)

Junction Field Effect Metal Oxide Semiconductor

Transistor Field Effect Transistor
(JFET) (MOSFET)

D-MOSFET E-MOSFET
n channel p channel • n channel • n channel
• p channel • p channel
 Introduction to
Metal-Oxide-Semiconductor
Field Effect Transistors
(MOSFETs)
 Structure: n-channel MOSFET
(NMOS)
gate: metal or heavily doped poly-Si
G
body source drain
(bulk or IG=0
B S D
substrate)
ID=IS
y IS

metal
oxide

n+ n+
p
x
W
L
 Circuit Symbol (NMOS)
enhancement-type: no channel at zero gate voltage

D
ID= IS

G B (IB=0, should be reverse biased)

IG= 0

IS G-Gate
D-Drain
S S-Source
B-Substrate or Body
Flatbands! For this choice of materials, VGS<0
n+pn+ structure  ID ~ 0
gate
G
body source drain
B S - + D
VD=Vs

n++
oxide

n+ n+
p

W
L
Flatbands < VGS < VT (Includes VGS=0 here).
n+-depletion-n+ structure  ID ~ 0
gate
G
body source drain
B S - + D
VD=Vs
+++
n++
oxide

n+ n+
p

W
L
 VGS > VT
n+-n-n+ structure  inversion
gate
G
body source drain
B S - + D
VD=Vs
+++
+++
+++
n++
oxide
-----
n+ n+
p

W
L
 Triode Region
A voltage-controlled resistor @small VDS

B S D
- +
ID
+++ VGS1>Vt
+++
increasing
metal
- oxide
- - -
VGS
n+ n+
p

B S -+ D

+++ VGS2>VGS1
+++
+++
metal G
- -oxide
- - --
n+ n+
p
cut-off VDS
B S -+ D
0.1 v
+++ VGS3>VGS2
+++
+++ +++ Increasing VGS puts more
metal

n+
- - -oxide
------
n+ charge in the channel, allowing
p
more drain current to flow
 Saturation Region
occurs at large VDS
As the drain voltage increases, the difference in
voltage between the drain and the gate becomes
smaller. At some point, the difference is too small
to maintain the channel near the drain  pinch-off
gate
G
body source drain
B S - + D
VDS large
+++
+++
+++
metal
oxide

n+ n+
p
 Saturation Region
occurs at large VDS
The saturation region is when the MOSFET
experiences pinch-off.
Pinch-off occurs when VG - VD is less than VT.
gate
G
body source drain
B S - + D
VDS large
+++
+++
+++
metal
oxide

n+ n+
p
 Saturation Region
occurs at large VDS
VGS - VDS < VT or VGD < VT
VDS > VGS - VT

gate
G
body source drain
B S - + D
VD>>Vs
+++
+++
+++
metal
oxide

n+ n+
p
 Saturation Region
once pinch-off occurs, there is no further increase in drain
current

ID saturation
triode
VDS>VGS-VT
increasing
VDS<VGS-VT
VGS

VDS
0.1 v
 Simplified MOSFET I-V Equations
Cut-off: VGS< VT
ID = IS = 0
Triode: VGS>VT and VDS < VGS-VT
ID = kn’(W/L)[(VGS-VT)VDS - 1/2VDS2]
Saturation: VGS>VT and VDS > VGS-VT
ID = 1/2kn’(W/L)(VGS-VT)2

where kn’= (electron mobility)x(gate capacitance)

= mn(eox/tox) …electron velocity = mnE
and VT depends on the doping concentration and gate
material used (…more details later)
• The MOSFET has only one current, ID
• Operation of MOSFET
– NMOS and PMOS
– For NMOS,
• VGS > VTN
• VDS sat = VGS – VTN

– For PMOS
• VSG > |VTP|
• VSD sat = VSG + VTP
• ID versus VDS (NMOS) or ID versus VSD (PMOS)
• NMOS • PMOS
o VTN is POSITIVE o VTP is NEGATIVE
o VGS > VTN to turn on o VSG > |VTP| to turn on
o Triode/non-saturation o Triode/non-saturation
region region

o Saturation region o Saturation region

o VDSsat = VGS - VTN o VSDsat = VSG + VTP

DC analysis of FET
MOSFET DC Circuit Analysis - NMOS

 The source terminal is

at ground and common
to both input and output
portions of the circuit.
 The CC acts as an open
circuit to dc but it allows
the signal voltage to the
gate of the MOSFET.

 In the DC equivalent circuit, the gate current into the transistor is

zero, the voltage at the gate is given by a voltage divider principle:
VG = VTH = R2 VDD
R1 + R2
Use KVL at GS loop:
VGS –VTH + 0 = 0
VGS = VTH
MOSFET DC Circuit Analysis - NMOS
1. Calculate the value of VGS

2. Assume the transistor is biased in the saturation

region, the drain current:

3. Use KVL at DS loop

IDRD + VDS – VDD = 0

4. Calculate VDSsat = VGS - VTN

5. Confirm your assumption:

If VDS > VDS(sat) = VGS – VTN, then the transistor is biased in the
saturation region. If VDS < VDS(sat), then the transistor is biased in the
non-saturation region.
EXAMPLE:
Calculate the drain current and drain to source voltage of a common source
circuit with an n-channel enhancement mode MOSFET. Assume that R1 =
30 k, R2 = 20 k, RD = 20 k, VDD = 5V, VTN = 1V and Kn = 0.1 mA/V2

VTH = 20 5 = 2V hence VGS = VTH = 2V

30 + 20

VDSsat = VGS – VTN = 2 – 1 = 1V, so, VDS > VDSsat, our assumption
that the transistor is in saturation region is correct
 EXAMPLE
VDD = 10V
• The transistor has parameters
VTN = 2V and Kn = 0.25mA/V2.
R1 = 280k RD =
• Find ID and VDS 10k

R2 = 160k
 Solution
1. VTH = 160 10 = 3.636 V
160 + 280
KVL at GS loop: VGS – VTH + 0 = 0  VGS = VTH
2. Assume in saturation mode:
ID = Kn(VGS - VTN)2

So, ID = 0.669 mA

3. KVL at DS loop: VDS = VDD – IDRD = 10 – 0.669 (10) = 3.31 V

4. VDS sat = VGS – VTN = 3.636 – 2 = 1.636 V

So, VDS > VDSsat , therefore, assumption is correct!

Answer: ID = 0.669 mA and VDS = 3.31 V

MOSFET DC Circuit Analysis - PMOS

Different notation:
VSG and VSD
Threshold Voltage = VTP

VG = VTH = R2 VDD
R1 + R2

Use KVL at GS loop:

VSG + 0 + VTH – VDD = 0
VSG = VDD - VTH
 MOSFET DC Circuit Analysis - PMOS

 Assume the transistor is biased in the saturation

region, the drain current:
ID = Kp (VSG + VTP)2
 Calculate VSD:
Use KVL at DS loop:
VSD + IDRD - VDD = 0

VSD = VDD - IDRD

 If VSD > VSD(sat) = VSG + VTP, then the transistor is biased in the
saturation region.
 If VSD < VSD(sat), then the transistor is biased in the non-saturation
region.
Calculate the drain current and source to drain voltage of a common
source circuit with an p-channel enhancement mode MOSFET.
Also find the power dissipation.
Assume that, VTP = -1.1V and Kp = 0.3 mA/V2
5V
Use KVL at SG loop:
VSG + 0 +2.5 – 5 = 0
VSG = 5 – 2.5 = 2.5 V
50 k
VSG > |VTP |
Assume biased in saturation mode:

50 k
7.5 k
Hence, ID = 0.3 ( 2.5 – 1.1)2 = 0.5888mA
Calculate VSD

Use KVL at SD loop:

VSD + IDRD – 5 = 0
VSD = 5 - IDRD
VSD = 5 – 0.5888 ( 7.5) = 0.584 V
VSD sat = VSG + VTP = 2.5 – 1.1 = 1.4V
Hence, VSD < VSD sat. Therefore assumption is incorrect. The transistor is
in non-saturation mode!

ID = 0.3 2 ( 2.5 – 1.1) (5 – IDRD) – (5 – IDRD)2

ID = 0.3 2.8 (5 – 7.5ID) – (5-7.5ID)2

ID = 0.3 14 – 21ID – (25 – 75ID + 56.25ID2)

ID = 0.3 14 – 21ID -25 +75ID – 56.25ID2

ID = 0.536 mA

56.25 ID2 – 50.67 ID + 11 = 0

ID = 0.365 mA
 ID = 0.536 mA ID = 0.365 mA

VSD = 5 – IDRD = 0.98 V VSD = 5 – IDRD = 2.26 V

VSD sat = VSG + VTP = 2.5 – 1.1 = 1.4V

0.98V < 1.4V 2.26V > 1.4V

Smaller than VSD sat : OK! Bigger than VSD sat : not OK

Answer: ID = 0.536 mA and VSD = 0.98V

Power dissipation = ID x VSD = 0.525 mW
 LOAD LINE
• Common source configuration i.e source is
grounded.
• It is the linear equation of ID versus VDS
• Use KVL
• VDS = VDD – IDRD
• ID = -VDS + VDD

RD RD
 ID (mA)

y-intercept

Q-POINTS
ID VGS

VDS (V)
VDS x-intercept
 • DC Analysis where source is NOT GROUNDED
For the NMOS transistor in the circuit below, the parameters are VTN = 1V and
Kn = 0.5 mA/V2.

+5V

RD = 2 k

RG = 24 k
-1V

RS = 1 k

-5V
 +5V

1. Get an expression for VGS in terms of ID ID

RD = 2 k

use KVL: RG = 24 k
-1V
0 + VGS+ 1(ID) -5 +1 = 0
VGS = 4 - ID
RS = 1 k
ID
2. Assume in saturation
-5V

ID = 0.5 ( 4 - ID – 1)2 = 0.5 ( 3 – ID) 2

2ID = 9 – 6ID + ID2
ID = 1.354 mA
ID2 – 8ID + 9 = 0 Replace in VGS = 2.646 V
VGS equation
ID = 6.646 mA VGS = 4 - ID VGS= -2. 646 V

Why choose VGS = 2.646 V ?

Because it is bigger than VTN
3. Get VDS equation and use the value of ID from step 2

Use KVL:
+5V
IDRD + VDS + IDRS – 5 – 5 = 0
1.354 (2) + VDS + 1.354 – 10 = 0
VDS = 10 – 1.354 – 2.708 = 5.938 V
ID
RD = 2 k
4. Calculate VDS sat
RG = 24 k
-1V
VDS sat = VGS – VTN = 2.646 – 1 = 1.646 V

RS = 1 k
5. Confirm your assumption ID
VDS > VDS sat  CONFIRMED
-5V