chapter 1

Introduction

1.1 FAULTS IN logic CIRCUITS

A failure is said to have occurred in a logic circuit or system if it deviates from its specified behavior
[1]. A fault, on the other hand, refers to a physical defect in a circuit. For example, a short between
two signal lines in the circuit or a break in a signal line is a physical defect. An error is usually the
manifestation of a fault in the circuit; thus a fault may change the value of a signal in a circuit from 0
(correct) to 1 (erroneous) or vice versa. However, a fault does not always cause an error; in that case,
the fault is considered to be latent.
A fault is characterized by its nature, value, extent, and duration [2]. The nature of a fault
can be classified as logical or nonlogical. A logical fault causes the logic value at a point in a circuit
to become opposite to the specified value. Nonlogical faults include the rest of the faults such as
the malfunction of the clock signal, power failure, etc. The value of a logical fault at a point in the
circuit indicates whether the fault creates fixed or varying erroneous logical values. The extent of
a fault specifies whether the effect of the fault is localized or distributed. A local fault affects only
a single variable, whereas a distributed fault affects more than one. A logical fault, for example, is a
local fault, whereas the malfunction of the clock is a distributed fault. The duration of a fault refers
to whether the fault is permanent or temporary.

1.1.1 Stuck-At Fault

The most common model used for logical faults is the single stuck-at fault. It assumes that a fault in a
logic gate results in one of its inputs or the output is fixed at either a logic 0 (stuck-at-0) or at logic 1
(stuck-at-1). Stuck-at-0 and stuck-at-l faults are often abbreviated to s-a-0 and s-a-1, respectively.
Let us assume that in Figure 1.1 the A input of the NAND gate is s-a-1. The NAND gate
per­ceives the A input as a logic 1 irrespective of the logic value placed on the input. For example, the
out­put of the NAND gate is 0 for the input pattern A=0 and B=1, when input A is s-a-1 in. In the
absence of the fault, the output will be 1. Thus, AB=01 can be con­sidered as the test for the A input
s-a-l, since there is a difference between the output of the fault-free and faulty gate.
The single stuck-at fault model is often referred to as the classical fault model and offers a
good representation for the most common types of defects [e.g., shorts and opens in complementary
  An Introduction to Logic Circuit Testing

Figure 1.1: Two-input NAND gate.

metal oxide semiconductor (CMOS) technology]. Figure 1.2 illustrates the CMOS realization of
the two-input NAND:
The number 1 in the figure indicates an open, whereas the numbers 2 and 3 identify the short
between the output node and the ground and the short between the output node and the VDD,
respectively. A short in a CMOS results if not enough metal is removed by the photolithography,
whereas over-removal of metal results in an open circuit [3]. Fault 1 in Figure 1.2 will disconnect
input A from the gate of transistors T1 and T3. It has been shown that in such a situation one tran-
sistor may conduct and the other remain nonconducting [4]. Thus, the fault can be represented by a
stuck at value of A; if A is s-a-0, T1 will be ON and T3 OFF, and if A is s-a-l, T1 will be OFF and
T3 ON. Fault 2 forces the output node to be shorted to VDD, that is, the fault can be considered as
an s-a-l fault. Similarly, fault 3 forces the output node to be s-a-0.
The stuck-at model is also used to represent multiple faults in circuits. In a multiple stuck-at
fault, it is assumed that more than one signal line in the circuit are stuck at logic 1 or logic 0; in other

Figure 1.2: Two-input NAND gate in CMOS gate.

 Introduction  

words, a group of stuck-at faults exist in the circuit at the same time. A variation of the multiple
fault is the unidirectional fault. A multiple fault is unidirectional if all of its constituent faults are
either s-a-0 or s-a-l but not both simultaneously. The stuck-at model has gained wide acceptance
in the past mainly because of its relative success with small scale integration. However, it is not very
effective in accounting for all faults in present day very large scale integrated (VLSI), circuits which
mainly uses CMOS technology. Faults in CMOS circuits do not necessarily produce logical faults
that can be described as stuck-at faults [5, 6, 7]. For example, in Figure 1.2, faults 3 and 4 create
stuck-on transistors faults. As a further example, we consider Figure 1.3, which represents CMOS
implementation of the Boolean function:

Z = (A + B)(C + D) · EF .

Two possible shorts numbered 1 and 2 and two possible opens numbered 3 and 4 are indi-
cated in the diagram. Short number 1 can be modeled by s-a-1 of input E; open number 3 can be
modeled by s-a-0 of input E, input F, or both. On the other hand, short number 2 and open number

Figure 1.3: CMOS implementation of Z = (A + B)(C + D) ⋅ EF.

  An Introduction to Logic Circuit Testing

Figure 1.4: CMOS implementation of Z1 = AB and Z2 = CD.

4 cannot be modeled by any stuck-at fault because they involve a modification of the network func-
tion. For example, in the presence of short number 2, the network function will change to:

Z = (A + C)(B + D) · EF ,

and open number 4 will change the function to:

Z = (AC) + (BD) · EF .

For this reason, a perfect short between the output of the two gates (Figure 1.4) cannot be
modeled by a stuck-at fault. Without a short, the outputs of gates Z1 and Z2 are:

Zl = AB and Z2 = CD ,

whereas with the short,

Zl = Z2 = AB + CD .

1.1.2 Bridging Faults

Bridging faults form an important class of permanent faults that cannot be modeled as stuck-at
faults. A bridging fault is said to have occurred when two or more signal lines in a circuit are ac-
 Introduction  

cidentally connected together. Earlier study of bridging faults concentrated only on the shorting of
signal lines in gate-level circuits. It was shown that the shorting of lines resulted in wired logic at
the connection.
Bridging faults at the gate level has been classified into two types: input bridging and feedback
bridging. An input bridging fault corresponds to the shorting of a certain number of primary input
lines. A feedback bridging fault results if there is a short between an output and input line. A feed-
back bridging fault may cause a circuit to oscillate, or it may convert it into a sequential circuit.
Bridging faults in a transistor-level circuit may occur between the terminals of a transistor
or between two or more signal lines. Figure 1.5 shows the CMOS logic realization of the Boolean
function:

Zl = Z2 = AB + CD

A short between two lines, as indicated by the dotted line in the diagram will change the function
of the circuit.
The effect of bridging among the terminals of transistors is technology-dependent. For ex-
ample, in CMOS circuits, such faults manifest as either stuck-at or stuck-open faults, depending on
the physical location and the value of the bridging resistance.

—−
— + CD
Figure 1.5: CMOS implementation of Z (A, B, C, D) = AB
 An Introduction to Logic Circuit Testing

1.1.3 Delay Faults

As mentioned previously, not all manufacturing defects in VLSI circuits can be represented by the
stuck-at fault model. The size of a defect determines whether the defect will affect the logic func-
tion of a circuit. Smaller defects, which are likely to cause partial open or short in a circuit, have a
higher probability of occurrence due to the statistical variations in the manufacturing process [8].
These defects result in the failure of a circuit to meet its timing specifications without any alteration
of the logic function of the circuit. A small defect may delay the transition of a signal on a line either
from 0 to 1, or vice versa. This type of malfunction is modeled by a delay fault.
Two types of delay faults have been proposed in literature: gate delay fault and path delay fault.
Gate delay faults have been used to model defects that cause the actual propagation delay of a faulty
gate to exceed its specified worst case value. For example, if the specified worst case propagation
delay of a gate is x units and the actual delay is x+∆x units, then the gate is said to have a delay fault
of size ∆x. The main deficiency of the gate delay fault model is that it can only be used to model
isolated defects, not distributed defects, for example, several small delay defects. The path delay
fault model can be used to model isolated as well as distributed defects. In this model, a fault is as-
sumed to have occurred if the propagation delay along a path in the circuit under test exceeds the
specified limit.

1.2 BREAKS AND TRANSISTORS STUCK-OPEN AND

STUCK-ON OR STUCK-OPEN FAULTS IN CMOS
As discussed previously, not all defects in CMOS VLSI can be represented by using the stuck-at
fault model. It has been shown that breaks and transistor stuck-ons are two other types of defects
that, like bridging, may remain undetected if testing is performed based on the stuck-at fault as-
sumption. These defects have been found to constitute a significant percentage of defects occurring
in CMOS circuits [2]. In the following two subsections, we discuss the effects of these defects on
CMOS circuits.

1.2.1 Breaks
Breaks or opens in CMOS circuits are caused either by missing conducting material or extra insu-
lating material. Breaks can be either of the following two types [3]:

1. Intragate breaks;
2. Signal line breaks.
 Introduction  

An intragate break occurs internal to a gate. Such a break can disconnect the source, the drain, or
the gate from a transistor, identified by b1, b2, and b3, respectively, in Figure 1.6. The presence of b3,
will have no logical effect on the operation of a circuit, but it will increase the propagation delay;
that is, the break will result in a delay fault. Similarly, the break at b1 will also produce a delay fault
without changing the function of the circuit. However, the break at b2 will make the p-transistor
nonconducting; that is, the transistor can be assumed to be stuck-open.
An intragate break can also disconnect the p-network, the n-network, or both networks (b4,
b5, and b6 in Figure 1.6) from the circuit. The presence of b4 or b5 will have the same effect as the
output node getting stuck-at-0 or stuck-at-1, respectively. In the presence of b6, the output voltage
may have an intermittent stuck-at-1 or stuck-at-0 value; thus, if the output node simultaneously
drives a p-transistor and an n-transistor, then one of the transistors will be ON for some unpredict-
able period of time. Signal line breaks can force the gates of transistors in static CMOS circuits to
float.
As shown in Figure 1.6, such a break can make the gate of only a p-transistor and an n-
transistor to float. It is also possible, depending on the position of a break, that the gates of
both transistors may float, in which case one transistor may conduct and the other remain in a

Figure 1.6: Two-input CMOS NAND gate showing occurrence of breaks.

 An Introduction to Logic Circuit Testing

nonconducting state [9]. In general, this type of break can be modeled as a stuck-at fault. On the
other hand, if two transistors with floating gates are permanently conducting, one of them can be
considered as stuck-on. If a transistor with a floating gate remains in a nonconducting state due to a
signal line break, the circuit will behave in a similar fashion as it does in the presence of the intragate
break b2.

1.2.2 Stuck-On and Stuck-Open Faults

A stuck-on transistor fault implies the permanent closing of the path between the source and the
drain of the transistor. Although the stuck-on transistor, in practice, behaves in a similar way as a
stuck-closed transistor, there is a subtle difference. A stuck-on transistor has the same drain-source
resistance as the on resistance of a fault-free transistor, whereas a stuck-closed transistor exhibits a
drain-source resistance that is significantly lower than the normal on-resistance. In other words, in
the case of stuck-closed transistor, the short between the drain and the source is almost perfect, and
this is not true for a stuck-on transistor. A transistor stuck-on (stuck-closed) fault may be modeled
as a bridging fault from the source to the drain of a transistor.
A stuck-open transistor implies the permanent opening of the connection between the source
and the drain of a transistor. The drain-source resistance of a stuck-open transistor is significantly
higher than the off-resistance of a nonfaulty transistor. If the drain-source resistance of a faulty
transistor is approximately equal to that of a fault-free transistor, then the transistor is considered
to be stuck-off. For all practical purposes, transistor stuck-off and stuck-open faults are functionally
equivalent.

Figure 1.7: A two-input CMOS NOR gate.

 Introduction  

Table 1.1: Truth table of two-input CMOS NOR gate with and without stuck-open fault

A B Z Z (As-op) Z (Bs-op) Z (VDDs-op)

0 0 1 1 1 Zt

0 1 0 0 Zt 0

1 0 0 Zt 0 0

1 1 0 0 0 0

A stuck-open transistor fault like a feedback bridging fault can turn a combinational circuit
into a sequential circuit [10]. Figure 1.7 shows a two-input CMOS NOR gate. A stuck-open fault
causes the output to be connected neither to GND nor to VDD. If, for example, transistor T2 is
open-circuited, then for input AB=00, the pull-up circuit will not be active and there will be no
change in the output voltage. In fact, the output retains its previous logic state; however, the length
of time the state is retained is determined by the leakage current at the output node.
Table 1.1 shows the truth table for the two-input CMOS NOR gate. The fault-free output
is shown in column Z; the three columns to the right represent the outputs in presence of the three
stuck-open (s-op) faults. The first, As-op, is caused by any input, drain, or source missing connec-
tion to the pull-down FET T3. The second, Bs-op, is caused by any input, drain, or source missing
connection to the pull-down FET T4. The third, VDDs-op, is caused by an open anywhere in the
series, p-channel pull-up connection to VDD. The symbol Zt is used to indicate that the output
state retains the previous logic value.

1.3 BASIC CONCEPTS OF FAULT DETECTION

Fault detection in a logic circuit is carried out by applying a sequence of tests and observing the
resulting outputs. A test is an input combination that specifies the expected response that a fault-free
circuit should produce. If the observed response is different from the expected response, a fault is

Figure 1.8: A NAND gate with a stuck-at-1 fault.

10 An Introduction to Logic Circuit Testing

Table 1.2: Output response of the NAND gate

IInput Output

a b c (Fault-Free) c (Fault-Present)

0 0 1 1

0 1 1 0

1 0 1 1

1 1 0 0

present in the circuit. The aim of testing at the gate level is to verify that each logic gate in the circuit
is functioning properly and the interconnections are good. Henceforth, we will deal with stuck-at
faults only unless mentioned otherwise. If only a single stuck-at fault is assumed to be present in
the circuit under test, then the problem is to construct a test set that will detect the fault by utilizing
only the inputs and the outputs of the circuit.
As indicated above, a test detects a fault in a circuit if and only if the output produced by the
circuit in the presence of the fault is different from the observed output when the fault is not pres-
ent. To illustrate, let us assume that input a of the NAND gate shown in Figure 1.8 is stuck-at-1.
The output responses of the gate to all input combinations for both fault-free and fault-present
conditions are shown in Table 1.2.
It can be seen in Table 1.2 that only for input combination ab = 0, the output is different in
the presence of the fault a s-a-1 and when the gate is fault-free.
In order to detect a fault in a circuit, the fault must first be excited; that is, a certain input
combination must be applied to the circuit so that the logic value appearing at the fault location is
opposite to the fault value. Next, the fault must be sensitized; that is, the effect of the fault is propa-

Figure 1.9: Circuit with a single s-a-1 fault.

 Introduction  11

gated through the circuit to an observable output. For example, in Figure 1.9, the input combination
abc=111 must be applied for the excitation of the fault, and d=1 for sensitizing the fault to output Z.
Thus, the test for the s-a-1 fault is abcd=1111. This input combination is also a test for other faults
(e.g., gate 1 s-a-0, gate 3 s-a-1, and input a s-a-0, etc.).

1.3.1 Controllability and Observability

As indicated above, in order to generate a test a for a stuck-at fault on a signal line, it must first be
forced to a value that is opposite to the stuck-at value on the line. This ability to apply input patterns
to the primary inputs of a circuit to set up appropriate logic value at desired locations of a circuit
is known as controllability. For example, in the presence of a stuck-at-0 fault, the location of the
fault must be set to logic 1 via the primary inputs; this is known as 1-controllability. Similarly, for a
stuck-at-1 fault, the location of the fault must be set to logic 0 to excite the fault; this is known as
0-controllability.
The sensitization part of the test generation process requires application of appropriate in-
put values at the primary inputs so the effect of the fault is observable at the primary outputs. For
example, in Figure 1.9, the effect of the stuck-at-1 fault can observed at output Z if input d is set
at 1; if d is set to 0, the output will be 0 and the effect of the fault will be masked (i.e., the fault will
not be detected). The ability to observe the response of a fault on an internal node via the primary
outputs of a circuit is denoted as observability.

1.3.2 Undetectable Faults

A fault is considered to be undetectable if it is not possible to activate the fault or to sensitize its
effect to primary outputs. In other words, a test for detecting the fault does not exist. To illustrate,
let us consider the α s-a-0 fault shown in Figure 1.10. It is not possible to set the node α to logic
1. Therefore, the fault cannot be excited and thus undetectable. The fault β s-a-0 can be excited
by making ab=10, but no sensitized path is available for propagating the effect of the fault to the

Figure 1.10: Circuit with a stuck-at-0 faults.

12 An Introduction to Logic Circuit Testing

output; hence, the fault is undetectable. A combinational circuit is denoted as redundant if it has an
undetectable fault.
A test set for a circuit is derived based on the assumption that only a single fault is present in
the circuit when the tests are applied. Thus, the simultaneous presence of an undetectable fault and
a detectable fault violates this assumption. Furthermore, the presence of an undetectable fault may
prevent the detection of a detectable fault.

1.3.3 Equivalent Faults

A test, in general, can detect more than one fault in a circuit, and many tests in a set detect the same
faults. In other words, the subsets of faults detected by each test from a test set are not disjoint.
Thus, a major objective in test generation is to reduce the total number of faults to be considered by
grouping equivalent faults in subsets. It is then sufficient only to test one fault from each equivalent
set to cover all faults in the set, thus avoiding redundancy in the test generation process.
In an m-input gate, there can be 2(m+1) stuck-at faults. Thus, the total number of single
stuck-at faults in a two-input NOR gate shown in Figure 1.11a is 6 (=2×3), e.g,. a s-a-0, b s-a-0, a
s-a-1, b s-a-1, c s-a-0 and c s-a-1. However, a stuck-at fault on an input may be indistinguishable
from a stuck-at fault at the output. For example, in a NOR gate (Figure 1.11a), any input s-a-1 fault
is indistinguishable from the output s-a-0; similarly, in a NAND gate (Figure 1.11b), an input s-a-0
fault is indistinguishable from the output s-a-1.
Two faults are considered to be equivalent if every test for one fault also detects the other.
In the two-input NOR gate shown in Figure 1.11, a stuck-at-1 fault on one of the inputs a or b is
equivalent to output c stuck-at-0, thus all three faults belong to the same equivalence set. A test for
any of these three faults will also detect the presence of the other two. The equivalence sets for the
NOR gate are:

{a s-a-1, b s-a-1, c s-a-0},

{a s-a-0, c s-a-1},
{b s-a-0, c s-a-1},

Figure 1.11: (a) NOR gate. (b) NAND gate.

 Introduction  13

and the equivalence sets for the NAND gate are:

{a s-a-0, b s-a-0, c s-a-1},

{a s-a-1, c s-a-0},
{b s-a-1, c s-a-0}.

Because there are three equivalence fault sets for both NOR and NAND gates, it is sufficient
to derive tests for three faults only in each case, i.e., one fault from each set. In general, an m-input
gate can have a total of (m+2) logically dis­tinct faults; however, only m+1 equivalent sets of faults
need to be considered.

1.3.4 Temporary Faults

As stated earlier, an error is a manifestation of a fault. A temporary fault can result in an intermit-
tent or a transient error. Transient errors are the major source of failures in VLSI chips. They are
nonrecurring and are not repairable because there is no physical damage to the hardware. Very deep
submicron technology has enabled the packing of millions of transistors on a VLSI chip by reduc-
ing the transistor dimensions. However, the reduction of transistor sizes also reduces their noise
margins. As a result, they become more vulnerable to noise, cross-talk, etc., which in turn result in
transient errors. In addition, small transistors are affected by terrestrial radiation and suffer tempo-
rary malfunction, thereby increasing the rate of transient errors.
Intermittent faults are recurring faults that reappear on a regular basis. Such faults can occur
due to loose connections, partially defective components, or poor designs. Intermittent faults oc-
curring due to deteriorating or aging components may eventually become permanent. Some inter-
mittent faults also occur due to environmental conditions such as temperature, humidity, vibration,
etc. The likelihood of such intermittent faults depends on how well the system is protected from
its physical environment through shielding, filtering, cooling, etc. An intermittent fault in a circuit
causes a malfunction of the circuit only if it is active; if it is inactive, the circuit operates correctly.
A circuit is said to be in a fault active state if a fault present in the circuit is active, and it is said to
be in the fault-not-active state if a fault is present but inactive [11]. Because intermittent faults are
random, they can be modeled only by using probabilistic methods.

References
[1] Anderson, T., and P. Lee, Fault-Tolerance: Principles and Practice, Prentice-Hall International
(1981).
[2] Avizienis, A., “Fault-tolerant systems,” IEEE Trans. Comput., 1304−11 (December 1976).
[3] Shoji, M., CMOS Digital Circuit Technology, Prentice-Hall (1988).
14 An Introduction to Logic Circuit Testing

[4] Maly, W., P. Nag, and P. Nigh, “Testing oriented analysis of CMOS ICs with opens,” Proc.
Intl. Conf. CAD, 344−7 (1988). doi:10.1109/ICCAD.1988.122525
[5] Ferguson, I. and J. Shen, “A CMOS fault extractor for inductive fault analysis,” IEEE Trans.
CAD, 1181−94 (November 1988). doi:10.1109/43.9188
[6] David, M. W., “An optimized delay testing technique for LSSD-based VLSI logic circuits,”
IEEE VLSI Test Symp., 239−46 (1991).
[7] Wadsack, R. L., “Fault modelling and logic simulation of CMOS and MOS integrated cir-
cuits,” Bell Syst. Technol. Jour., 1149−75 (May−June 1978).
[8] Ferguson. J., M. Taylor, and T. Lamabee, “Testing for parametric faults in static CMOS cir-
cuits,” Proc. Intl. Test Conf., 436−42 (1990). doi:10.1109/TEST.1990.114052
[9] Maly, W., “Realistic fault modeling for VUI testing,” Proc. 24th ACMI IEEE Design Auzom-
atlon Conf., 173−80 (1987).
[10] Ferguson, J., and J. Shen, “Extraction and simulation of realistic CMOS faults using induc-
tive fault analysis,” Proc. Intl. Test Conf., 475−84 (1988). doi:10.1109/TEST.1988.207759
[11] Malaiya, Y. K., and S. Y. H. Su, “A survey of methods for intermittent fault analysis,” Proc.
Nut Comput Conf., 577−84 (1979).

• • • •