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    Field Effect Transistors

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    Ratan
    This document provides information on field effect transistors (FETs), specifically junction field effect transistors (JFETs) and metal-oxide-semiconductor field effect transistors (MOSFETs). It describes FETs as three-terminal devices where the gate voltage controls current flow between the source and drain. JFETs use a reverse-biased p-n junction as the gate, while MOSFETs use a metal-oxide-semiconductor structure with the gate separated from the channel by an insulating layer. The document discusses the operation, characteristics and applications of n-channel and p-channel JFETs and enhancement and depletion mode MOSFETs. It also includes examples of calculating current, voltage and other parameters for

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    Field Effect Transistors

    Uploaded by

    Ratan
    161 views40 pages
    This document provides information on field effect transistors (FETs), specifically junction field effect transistors (JFETs) and metal-oxide-semiconductor field effect transistors (MOSFETs). It describes FETs as three-terminal devices where the gate voltage controls current flow between the source and drain. JFETs use a reverse-biased p-n junction as the gate, while MOSFETs use a metal-oxide-semiconductor structure with the gate separated from the channel by an insulating layer. The document discusses the operation, characteristics and applications of n-channel and p-channel JFETs and enhancement and depletion mode MOSFETs. It also includes examples of calculating current, voltage and other parameters for

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    Transistors explained

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    This document provides information on field effect transistors (FETs), specifically junction field effect transistors (JFETs) and metal-oxide-semiconductor field effect transistors (MOSFETs). It describes FETs as three-terminal devices where the gate voltage controls current flow between the source and drain. JFETs use a reverse-biased p-n junction as the gate, while MOSFETs use a metal-oxide-semiconductor structure with the gate separated from the channel by an insulating layer. The document discusses the operation, characteristics and applications of n-channel and p-channel JFETs and enhancement and depletion mode MOSFETs. It also includes examples of calculating current, voltage and other parameters for

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    161 views40 pages

    Field Effect Transistors

    Uploaded by

    Ratan
    This document provides information on field effect transistors (FETs), specifically junction field effect transistors (JFETs) and metal-oxide-semiconductor field effect transistors (MOSFETs). It describes FETs as three-terminal devices where the gate voltage controls current flow between the source and drain. JFETs use a reverse-biased p-n junction as the gate, while MOSFETs use a metal-oxide-semiconductor structure with the gate separated from the channel by an insulating layer. The document discusses the operation, characteristics and applications of n-channel and p-channel JFETs and enhancement and depletion mode MOSFETs. It also includes examples of calculating current, voltage and other parameters for

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    FIELD EFFECT

    TRANSISTORS
    JFET AND MOSFET

    FIELD EFFECT TRANSISTORS


    Unipolar devices; current is carried only by majority carriers
    Three terminal device: Gate, Source, Drain
    Voltage controlled devices; gate (G) controls current flow between source (S) and
    drain (D)

    FET can be modelled as a resistance between source and drain, controlled by gate
    terminal
    Why field effect?

    Difference between BJT and FET


    Bipolar Junction Transistor

    Field Effect transistor

    Bipolar

    Unipolar

    Current controlled

    Voltage Controlled

    Lower input impedance

    High input impedance (implies no gate current)

    TYPES OF FETS
    1. Junction Field Effect Transistor (JFET)
    2. Metal-Oxide Semiconductor Field effect Transistor (MOSFET)

    JUNCTION FIELD EFFECT TRANSISTORS


    (JFETs)
    JFET is a type of field effect transistor that uses a reverse biased p-n junction (as
    gate) to control current in channel

    JUNCTION FIELD EFFECT TRANSISTORS


    (JFETs)
    JFETs can be of two types: n-channel and p-channel

    N-CHANNEL JFET OPERATION


    Case I: VD = VS = 0V
    We vary the reverse bias gate voltage as VG = 0 V, VG = -1 V; VG = -2 V

    When reverse bias is large enough so that entire n-channel becomes depleted, the
    corresponding voltage is called pinch-off voltage

    N-CHANNEL JFET OPERATION


    Case II: VG = constant and VDS > 0 V
    We vary the reverse bias gate voltage as VG = 0 V, VG = -0.05 V; VG = -1 V

    N-CHANNEL JFET OPERATION


    Now, voltage in the channel varies as a function of distance from source (x),
    depletion width becomes
    0.5
    2 ()
    =

    Hence, depletion region is wider at the drain

    PINCH-OFF VOLTAGE
    VP = VG at h=0 or W=a
    For p+-n junction,
    2

    =
    potential

    0.5

    , where Vbi is the built-in

    For pinch-off, W = a
    => =

    2
    2

    PINCH-OFF VOLTAGE
    http://www.learnabout-electronics.org/Downloads/Fig3116_new.swf
    Animation for explaining pinch off.

    N-CHANNEL JFET OPERATION


    Saturation current
    decreases as gate
    voltage is increased,
    that is, as the
    depletion region
    widens

    TRANSFER CHARACTERISTICS
    The relationship between ID and VG is defined by Shockley equation:
    = 1

    PROBLEMS
    1. The device parameters for an n-Channel JFET are: Maximum current IDSS = 10mA, Pinch off
    voltage,
    VP = - 4V
    Calculate the drain current for
    (a) VGS = 0
    (b) VGS = - 1V
    (c) VGS = - 2V
    (d) VGS = -4V

    Solution:
    = 1
    (a) For VGS = 0,

    ID = IDSS = 10mA
    (b) for VGS = -1 V,
    ID = IDSS*(1-0.25) = 7.5mA
    (c) for VGS = -2 V,
    ID = IDSS*(1-0.5) = 5mA
    (d) for VGS = -1 V,
    ID = IDSS*(1-1) = 0mA

    PROBLEMS
    Q 2. For the JFET in Fig. 19.15, VP = 4V and IDSS = 12 mA. Determine the minimum value of VDD
    required to put the device in the saturation
    region of operation.

    Solution:
    The minimum value of VDS for the JFET to be in saturation region is VDS = VP = 4V
    In the saturation region with VGS = 0V, ID = IDSS = 12 mA, applying Kirchhoffs voltage law around
    the drain circuit, we have,
    VDD = VDS + VRD = VDS + ID RD
    = 4V + (12 mA) (560)
    = 4V + 6.72V = 10.72V
    This is the value of VDD to make VDS = VP and put the device in the constant-current region

    3. The reverse gate voltage of JFET when changes from 4.4V to 4.2V, the drain current changes
    from 2.2 mA to 2.6 mA. Find out the value of transconductance of the transistor

    Solution:
    Transconductance (gm) =

    Where ID is the change is drain current and VGS is the change in gate voltage
    => =

    2.62.2
    4.44.2

    = 0.002

    4. Calculate the value of source resistance RS required to self bias a n-JFET such that VGSQ = - 3V.
    The n-JFET has maximum drain-source current IDSS = 12 mA, and pinch-off voltage, VP = - 6V.

    Solution:
    The drain current ID in a JFET in the saturation region is,

    = 1

    We have IDSS = 12mA, VGS = -3V, VP = 6V


    => ID = 9 mA
    Since voltage VGS is generated across source resistor RS, we have,
    RS =

    = 333

    METAL-OXIDE SEMICONDUCTOR FIELD


    EFFECT TRANSISTOR (MOSFET)
    Four terminal device: Gate (G), Body (B), Source (S) and Drain (D)
    The MOS structure forms a parallelplate
    plate capacitor with gate oxide layer
    between gate and channel
    Two pn junctions (SB and DB) are
    connected as back to back diodes
    There are two types of MOSFETs:
    n-channel and p-channel

    MOSFET WORKING
    Positive charges accumulate in gate as a positive voltage applies to gate electrode
    Electric field forms a depletion region by
    pushing holes in ptype substrate away
    from the surface
    Electrons accumulate on the substrate
    surface as gate voltage exceeds a threshold
    voltage Vt
    The induced n region thus forms a channel
    for current flow from drain to source

    ENHANCEMENT MOSFET

    Consider a p-channel MOSFET


    When substrate is grounded and negative voltage is applied at gate, holes are generated
    in p-channel

    Thus, p-channel gets enhanced

    DEPLETION MOSFET
    Same types of impurity ions in channel as in source and drain
    Consider an n-channel MOSFET
    If negative voltage is applied at the gate
    (while grounding substrate), holes are generated
    in the n-channel
    Thus the n-channel gets depleted

    TRANSFER CHARACTERISTICS

    CIRCUIT SYMBOLS

    ENHANCEMENT MODE TERMINAL


    CHARACTERISTICS
    Enhancement mode devices have no built in channel (i.e., the device is normally off)
    A threshold voltage, determined by physical and fabrication parameters, exists for the MOSFET
    (VT > 0 for NMOS, VT < 0 for PMOS)
    Generally, the source is grounded and is common to both gate and drain
    An active channel is created between drain and source (the transistor is turned on) through the
    application of a gate voltage of appropriate polarity and magnitude (VGS VT > 0 for NMOS,
    VGS - VT < 0 for PMOS)
    Current flow between the drain and source is a function of both VGS and VDS

    ENHANCEMENT MODE TERMINAL


    CHARACTERISTICS
    For n-channel MOSFET:
    If VDS < VGS VT , the transistor is
    operating in the triode region

    1 2
    =
    [ ]
    2

    If VDS > VGS VT , the transistor is


    operating in the saturation region
    =

    Output resistance : =

    1 + ; =
    1

    ENHANCEMENT MODE TERMINAL


    CHARACTERISTICS
    Similarly for p-channel MOSFET:
    If VSD < VSG |VT| , the transistor is
    operating in the triode region

    1 2
    =
    [ | | ]
    2

    If VSD > VSG |VT| , the transistor is


    operating in the saturation region
    =


    | |
    2

    Output resistance : =

    1 + ; =
    1

    DEPLETION MODE TERMINAL


    CHARACTERISTICS
    Depletion mode devices have a built in channel (i.e., the device is normally on)
    A threshold voltage, determined by physical and fabrication parameters, exists for the MOSFET
    (VT < 0 for NMOS, VT > 0 for PMOS)
    Generally, the source is grounded and is common to both gate and drain
    The active channel is depleted between drain and source (the transistor is turned off) through
    the application of a gate voltage of appropriate polarity and magnitude (VGS VT < 0 for NMOS,
    VGS - VT > 0 for PMOS)
    Current flow between the drain and source is a function of both VGS and VDS. However, in the
    depletion mode, current can flow for both positive and negative values of VGS for both NMOS
    and PMOS devices until the cutoff condition is reached

    DEPLETION MODE TERMINAL


    CHARACTERISTICS
    For n-channel MOSFET:
    Equations similar to enhancement mode for triode and saturation regions, except that
    VT is negative
    For VGS = 0 and VDS> 0, there is a non-zero current defines as zero-gate drain current or IDSS
    For VGS> 0, ID > IDSS

    DEPLETION MODE TERMINAL


    CHARACTERISTICS
    For p-channel MOSFET:

    PROBLEMS
    1. For DMOSFET in figure 1, device parameters are: VGS(off) = -8V, IDSS = 10mA. Determine VDS
    Solution:
    Since RG is grounded, there is no gate current => VGS= 0 V
    When VGS= 0, ID= IDSS (maximum drain current)
    Using KVL, we have,
    IDSS.RD + VDS = VDD
    => VDS = 18 10 103 680
    => VDS = 11.2 V

    Figure 1

    PROBLEMS
    2. Datasheet on EMOSFET specifies following parameters: ID(on) = 50mA at VGS = 6 V and
    threshold voltage VT= 2V. Determine drain current at VGS = 3V
    Solution:
    At VGS = 6V,
    50*10-3= k(6-2)2
    => k = 3.12mA/V2
    At VGS = 3V,
    IDS = 3.12*10-3*(3-2)2
    => IDS = 3.12 mA

    PROBLEMS
    3. Find the drain-source voltage, VDS for the NMOS transistor circuit shown in figure 2. The
    device parameters are: conductance parameter, k = 600A/V2 and
    VT = 2V
    Solution:
    The gate current, IG is zero in a MOSFET. Then, from voltage
    divider network,
    =

    2
    1 +2

    => VGS = 5V

    Now, =

    = 600 106 32
    = 5.4

    Applying KVL in output loop, = +


    = 15 5.4 2 = 4.2

    Figure 2

    PROBLEMS
    5. For the below circuit find (k2/k1) so that the output voltage is 0.3 V when the input voltage is
    high. Use VT = 1V. (k= Cox (W/L)) .

    PROBLEMS
    Solution:
    Let the lower NMOS be Q1 and upper NMOS be Q2
    Output voltage Vo = 0.3V
    For Q2, VDS2 = 4.7 V and VGs2 VT = 4.7-1 = 3.7V
    => VDS2 > VGS2 VT => Q2 will always be in saturation
    If input is high, Vi = VGS1 = 5V and VDS1 = 0.3V
    => VDs1< VGS1 VT => Q1 is in linear regime when input is high
    Now, ID1=ID2
    => k1*[(VGS1 - VT)*VDS1 0.5*VDS12] = (k2/2)*(VGS2 VT)2
    => k1*[1.2 0.045] = k2*6.845
    => k2/k1 = 0.169

    References
    Electronic devices and circuit theory, 7th Edition, Robert Boylestad and Louis Nashelky
    Microelectronics, 2nd Edition, Jacob Millman and Arvin Garbel
    Analog and digital circuits and systems, Jacob Millman and Christos C Halki

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