Automotive FET Driver For 3 Phase BLDC Motor: Features
Automotive FET Driver For 3 Phase BLDC Motor: Features
Automotive FET Driver For 3 Phase BLDC Motor: Features
Contents
2 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1 Power supply VB, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2 Voltage regulator VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.3 EN1 and EN2 pins (ENABLE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4 Boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
2.4.1 BstDis (boost disable) function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.5 MOSFET drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.1 GCR pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.2 Shoot through protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.5.3 Drain source monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.6 Current Sense Amplifier (CSA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.7 System clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.8 General SPI usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.9 Device and FET fault handling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.9.1 SPI and PWM faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.1 Maximum operating ranges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.3 ESD protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.4 Temperature ranges and thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5.1 Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5.2 Voltage regulator VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5.3 Logic input pins (PWM_H1 to 3, PWM_L1 to 3, SCK, CS, SDI, BST_DIS,
EN1 and EN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5.4 Logic output pins (FS_FLAG, SDO, TO3) . . . . . . . . . . . . . . . . . . . . . . . 22
3.5.5 Boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5.6 MOSFET drivers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4 SPI operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
4.1 SPI bits mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4.1.1 SDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.1 12 V/24 V system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
5.2 48 V system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
5.3 Bill of materials . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
6.1 TQFP64 (10x10x1 mm exp. pad down) package mechanical data . . . . . 45
6.1.1 TQFP64 exposed pad dimensions for L9907 . . . . . . . . . . . . . . . . . . . . 47
7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
List of tables
List of figures
Vcc
(5V or 3.3V) VC BST_C BST_L
VB
3.3V Boost
VDH
Vdd Vreg regulator
(3.3V)
BGND
CBS1
PWM H1
PWM L1
GHS1
PWM H2
PWM L2
Logic SHS1
PWM H3
PWM L3
EN1
GLS1
EN2
BST_DIS
SLS1
Half bridge driver 1
CBS2
FS FLAG GHS2
H bridge driver 2
Half SHS2
GLS2
SDI SLS2
CBS3
CS SPI
GHS3
SCK Half bridge driver 3 SHS3
GLS3
SDO SLS3
Gat charge current set
Gate
GCR
TM 100 / 75 / 50 / 25%
IB1 IS2+
IB2 IS2-
BST_DI
BST_C
BST_L
DGND
BGND
VCAP
GCR
VDH
VDD
VCC
NC
NC
NC
NC
NC
VB
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
NC 1 48 SGND1
GLS_3 2 47 PWM_L3
SLS_3 3 46 PWM_L2
NC 4 45 PWM_L1
GLS_2 5 44 EN1
SLS_2 6 43 EN2
NC 7 42 TO3
GLS_1 8 41 SDO
SLS_1 9 40 SDI
AGND 10 39 SCK
IS1+ 11 38 CS
IS1- 12 37 FS_FLAG
NC 13 36 PWM_H3
IB1 14 35 PWM_H2
IB2 15 34 PWM_H1
SGND2 16 33 TM
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
17 IS2-
IS2+
NC
CBS_3
GHS_3
SHS_3
NC
CBS_2
GHS_2
SHS_2
NC
CBS_1
GHS_1
SHS_1
NC
NC GAPGPS00834
1 NC NC -
2 GLS_3 Gate connection for low-side MOSFET, phase 3 O
3 SLS_3 Source connection for low-side MOSFET, phase 3 I
4 NC NC -
5 GLS_2 Gate connection for low-side MOSFET, phase 2 O
6 SLS_2 Source connection for low-side MOSFET, phase 2 I
7 NC NC -
8 GLS_1 Gate connection for low-side MOSFET, phase 1 O
9 SLS_1 Source connection for low-side MOSFET, phase 1 I
10 AGND Analog ground GND
11 IS1+ Positive input for current sense amplifier 1 I
12 IS1- Negative input for current sense amplifier 1 I
13 NC NC -
14 IB1 Output for current sense amplifier 1 (Test mode digital output #1) O
15 IB2 Output for current sense amplifier 2 (Test mode digital output #2) O
16 SGND2 Substrate (and ESD_GND) connection 2 GND
2 Functional description
CBS1
V-reg V-reg
GHS1
SHS1
HS-Gate-Driver 1
GLS1
SLS1
LS-Gate-Driver 1
CBS2
V-reg
GHS2
SHS2
HS-Gate-Driver 2
GLS2
SLS2
LS-Gate-Driver 2
CBS3
V-reg
GHS3
SHS3
HS-Gate-Driver 3
GLS3
SLS3
LS-Gate-Driver 3
GAPGPS00835
In case Boost converter is disabled, but voltage at BST_C pin is present, Current Sense
Amplifiers are active but with degraded performances at least in common mode dynamic
range. In order to improve EMC behaviour an external RC series snubber can be added
between BST_L and BGND pins. RC~1/(6.28*fSW_BST).
BOOST CLK
21*TCK MAX =
5*TCK filter +
1BOOST period GAPGPS00836
BOOST CLK
T_BOOST_OFF_MAX =
96*TCK = 6 BOOST periods
GAPGPS00837
When BST_DIS_EN bit of CMD2 SPI frame is set to 1 (refer to SPI mapping, Table 23),
BST_DIS becomes a full-time control of the boost operation: the boost will be disabled as
long as the BST_DIS pin is high. This implements a boost permanent disabler that can be
used for different reasons, e.g. to allow more precise and less noisy measurements, to
decrease power dissipation or current load on battery in all conditions when the boost is not
strictly necessary.
In order to unlatch also FS_FLAG status a SPI communication with diagnostic frame must
be performed.
50*R SG3
G
30*RG SG2
10*RG SG1
RG
ISx-
IBx
VIsx+-VIsx-
ISx+
RG
VCC
10*RG 30*RG 50*RG 100*RG
ROFS
SOFS1 SOFS2
0.25*ROFS ROFS
Each CSA can be used for phase (bidirectional) or ground (unidirectional) current
monitoring by properly selecting the output zero-current offset via dedicated bits in the SPI
register CMD0; Off1 for CSA1 and Off2 for CSA2.
The gain of each CSA can be independently configured selecting between four different
values via dedicated bits in the SPI register CMD0; G10, G11 for CSA1 and G20, G21 for
CSA2.
Current Sense Amplifier is active if IC is active (VCC and VDD present and within spec
range), despite the EN status. In case Boost converter is disabled, but voltage at BST_C pin
is present, Current Sense Amplifiers work but with degraded performances at least in
common mode dynamic range.
3 Electrical specifications
HBM according to MIL 883C, Method 3015.7 or EIA/JESD22-A114_A. HBM with all
unzapped pins grounded.
3.5.1 Supply
The device is operated in the specified operating range, unless otherwise specified
(VCC = 3.20 V to 5.25 V, VB = 4.2 V to 54 V, Tj = -40 °C to 150 °C).
AGNDloss AGND loss threshold Ramp AGND starting from 0 V 150 220 290 mV
3.5.3 Logic input pins (PWM_H1 to 3, PWM_L1 to 3, SCK, CS, SDI, BST_DIS,
EN1 and EN2)
The device is operated in the specified operating range, unless otherwise specified
(VCC = 3.20 V to 5.25 V, VB = 4.2 V to 54 V, Tj = -40 °C to 150 °C).
Table 15. Logic output pins (FS_FLAG, SDO, TO3) electrical characteristics
Symbol Parameter Test condition Min Max Unit
Turn-on/off current with GCR = 1 IG_1,IG_0 = 10 75% Imax 337 450 563 mA
IGxx_1
kΩ (1) IG_1,IG_0 = 01 50% Imax 225 300 375 mA
IG_1,IG_0 = 00 25% Imax 112 150 188 mA
IG_1,IG_0 = 11 100% Imax 75 100 125 mA
SC_LS1, SC_LS0 = 00
0.4 0.5 0.6 V
(default)
Short circuit detection threshold low-
VSC_LS side (adjustable in 4 steps via 2 bits SC_LS1, SC_LS0 = 01 0.7 0.8 0.9 V
SPI register) SC_LS1, SC_LS0 = 10 0.9 1 1.1 V
SC_LS1, SC_LS0 = 11 1.17 1.3 1.43 V
SC_HS1, SC_HS0 = 00
0.4 0.5 0.6 V
(default)
Short Circuit detection threshold high-
VSC_HS side (adjustable in 4 steps via 2 bits SC_HS1, SC_HS0 = 01 0.7 0.8 0.9 V
SPI register) SC_HS1, SC_HS0 = 10 0.9 1 1.1 V
SC_HS1, SC_HS0 = 11 1.17 1.3 1.43 V
Table 20. Phase current sense amplifier (SPI select: Offx=1, where x=1,2)
Symbol Parameter Test condition Min Typ Max Unit
Table 20. Phase current sense amplifier (SPI select: Offx=1, where x=1,2) (continued)
Symbol Parameter Test condition Min Typ Max Unit
Note: Table 21 is referred to current sense amplifier configuration for unidirectional current
measurement (shunt resistors to ground). SPI select: Offx=0 (Power up default), where
x=1,2 in CMD0 command frame.
3. Guaranteed by design.
0.8 V CC
- + I trim HI --------------------------------------------
2 + 3 Phase - + 10A
4. I SxHI = – ----------------------------------
2000 Gnom 8
0.8 V CC
- + I trim LO 2
I SxLO = – ---------------------------------- --- + 10A + I rail
2000 Gnom 8
Where:
ISxHI is current flowing out from ISxHI pin
ISxLO is current flowing out from ISxLO pin
Vcc = reference supply [5 V or 3.3 V]
Gnom = nominal programmed gain [10, 30, 50, 100]
I(trim,HI/LO) = offset trimming current (w.c. ± 8 µA see expression below)
Phase = programmed phase configuration [1 if selected, otherwise 0]
I(rail) = current from auxiliary rail (used for floating OpAmp) [typ ~145 µA±35% T+Models]
weight
trimming bit -------------------
Vbg 2 2 + 3 Phase
I trim HI = ----------- ---------------------------------------------------------------------- ---------------------------------------------
15 10300 5 + 3 Ground 8
weight
trimming bit -------------------
Vbg 2 2
I trim LO = ----------- ---------------------------------------------------------------------- ---
15 10300 5 + 3 Ground 8
Where:
Vbg = band gap reference (1.2371 V nominal)
Ground = programmed ground configuration [1 if selected, otherwise 0]
Trimming bit weight= how many mV offset trimming are programmed.
The ± depends on offset trim direction (+: bit7=1, -: bit7=0)
5. A 350 kHz, 100 mVpp, ripple at the boost regulator output, generates 1 mVpp noise at the amplifier input. It represents a 2
App current noise on a 0.5 m current sense resistor.
4 SPI operation
The L9907 SPI is a standard 16-bit, four wire interface. By means of the SPI most device
parameters can be internally set and the fault diagnostic can be read.
The timing diagram for the SPI operation is reported in Figure 7 below. The IC reads the
input data at SDI pin on the falling edge of the SPI clock (SCK). The IC outputs the SPI data
at SDO pin on the rising edge of the SPI clock (SCK).
8
CS
10
2 1
3
SCK
1a 1b
11 4
7
5 6
The SPI protocol integrates an internal check to add robustness to the communication: a
writing attempt of a not allowed register, an incorrect parity frame or a wrong number of bits
(different than 16) results in a "SPI error bit", that is available at SDO immediately after
asserting CS the next time and before starting the SCK toggling.
If the current SPI cycle is affected by a communication error, the current SDI command is
rejected and a SPI error message (0xB001) is presented as SDO response at the following
SPI cycle.
Cload < 60 pF
9 SDO rise/fall time (tSDO-rise, tSDO-fall) - 35 - ns
@ fSCK =8 MHz
CS
tCS-select 8 50 ns
10 - -
tCS-access 9 3.58 µs
tCS-negated 10 640 ns
11 SDO Access Time (ta) 11 - - 80 ns
BST_DIS_EN(1) EN_VBov
EN_VBuv
SC_HS0
SC_LS1
SC_LS0
VccOV2
VccOV1
VBOV2
VBOV1
SC_HS
CMD1 0 0 1 Par WE 0
GCR_INT_I(1)
SHT_PH(1)
ShortPH(1)
VOVTST
VSCTST
CMD2 0 1 0 Par WE - - - - - -
REGOFF_EN DIS_BSTov(1)
TRIM24
TRIM23
TRIM22
TRIM21
TRIM20
TRIM14
TRIM13
TRIM12
TRIM10
TRIM11
CMD3 0 1 1 Par WE -
EN_VSCHS1
EN_VSCHS2
EN_VSCHS3
EN_VSCLS1
EN_VSCLS2
EN_VSCLS3
EN_UV_HS
EN_UV_LS
EN_Vccov
EN_Vccuv
CMD4 1 0 0 Par WE 0
DIAG 1 1 0 - Par - - - - - - - - - - - -
DIAG2 1 1 1 - Par - - - - - - - - - - - -
B(15:13) SDI command selection bits, used to select the SPI operation to be implemented
B(9:0) the SDI setting bits to be internally stored for device operation in case of writing SPI cycle
100-200ns 0 0
300-500 ns 0 1
700-1000 ns 1 0
1000-1500 ns 1 1
b) IG_1 and IG_0 (B7,B6) are used to select turn on/off current value: ('00' default
condition at Power-On Reset)
25% 0 0
50% 0 1
75% 1 0
100% 1 1
c) G21 and G20 (B5,B4) are used to select current sense amplifier 2 gain: ('00'
default condition at power on reset)
10 0 0
30 0 1
50 1 0
100 1 1
d) Off2 (B3) is used to select current sense amplifier 2 offset (for ground or phase
connection): '0' (default value) means ground, '1' means phase.
e) G11 and G10 (B2,B1) are used to select Current sense amplifier 1 Gain:('00'
default condition at Power-On Reset)
10 0 0
30 0 1
50 1 0
100 1 1
f) Off1 (B0) is used to select current sense amplifier 1 offset (for ground or phase
connection): '0' (default value) means ground, '1' means phase.
Table 29. Short circuit detection threshold for low-side external MOSFET
VSC_LS B7 = SC_LS1 B6 = SC_LS0
0.4 – 0.6 V 0 0
0.7 – 0.9 V 0 1
0.9 – 1.1 V 1 0
1.17 – 1.43 V 1 1
Note: The accuracy in ranges in Table 29 is valid for VB > 6 V. For VB < 6 V the accuracy is 22.5%
for each configuration.
b) SC_HS1 and SC_HS0 (B5-B4) are used to select short circuit detection threshold
for high-side external MOSFET ('00' default condition at Power Up):
Table 30. Short circuit detection threshold for low-side external MOSFET
VSC_HS B5 = SC_HS1 B4 = SC_HS0
0.4 – 0.6 V 0 0
0.7 – 0.9 V 0 1
0.9 – 1.1 V 1 0
1.17 – 1.43 V 1 1
Note: The accuracy in ranges in Table 30 is valid for VB > 6 V. For VB < 6 V the accuracy is 22.5%
for each configuration.
c) VBOV2 and VBOV1 (B3-B2) are used to select over voltage threshold for single or
double battery application
Table 31. VB over voltage threshold for single or double battery application
VBOV B3 = VBOV2 B2 = VBOV1 (1)
27.5 – 34.5 V 1 0
36 – 42 V (Default) 0 1
Not Allowed 0 0
Not Allowed 1 1
1. For power supply configuration in 48 V domain, please refer to AN5124.
The power-up default value for this parameter is "01", corresponding to double battery
applications.
A SPI command attempting to set a not allowed VBOV configuration does not return any SPI
error, and the VBOV configuration register retains its previous value.
d) EN_THSD, EN_VBOV EN_VBUV (B12,B9,B8) are used to enable/disable effect
of Thermal Shut Down, VB overvoltage, VB Under Voltage faults respectively.
Default value is '1' for all of them, that means "fault effect is enabled".
B12 EN_THSD It enables Thermal shut down fault effect in case of THSD fault detection
B9 EN_VBOV It enables VBOV fault effect in case of VBOV fault detection
B8 EN_VBUV It enables VBUV fault effect in case of VBUV fault detection
e) VCCOV2 and VCCOV1 (B1-B0) are used to select the VCC over voltage thresholds:
3.3 V (default) 1 0
5.0 V 0 1
Not Allowed 0 0
Not Allowed 1 1
The Power Up default value for this parameter is "10", corresponding to Vcc = 3.3 V
applications.
A SPI command attempting to set a not allowed VCCOV configuration does not return any
SPI error, and the VCCOV configuration register retains its previous value.
-15 mV 0 1111
-14 mV 0 1110
-13 mV 0 1101
... 0 ...
-3 mV 0 0011
-2 mV 0 0010
-1 mV 0 0001
0 mV 0 0000
0 mV 1 0000 (0000 = Default)
+1 mV 1 0001
+2 mV 1 0010
+2 mV 1 0011
... 1 ...
+13 mV 1 1101
+14 mV 1 1110
+15 mV 1 1111
If EN1 and EN2 are both asserted while a SPI cycle CMD4 or CMD1 with WE=1 is ongoing,
then a SPI communication error is generated and the corresponding SPI command is
ignored.
The effect of any fault (except Shoot Through) can be selectively masked from Micro
Controller setting at '0' proper register. FS_FLAG status and SDO report are not affected
since fault detection always acts in the same way. Default value for these bits is '1' (fault
effect enabled). Once the fault effect is re-enabled with SPI communication the IC reacts to
fault as described in the specific paragraph if the fault is still present.
7. REG_OFF procedure (active only if CMD4 B12 is set; refer also to Section 2.3)
Lowering EN1 external pin triggers the procedure to switch off regulators that supply
the HS and LS FET drivers: filter time, active only on the falling edge of the EN1 signal,
is implemented: 8*tosc TFILT 16*tosc.
Once the procedure has been triggered, the device behaves as follows:
REG_OFF = '1', EN_PWM = "000", FS_FLAG = '0', DIAG2 bit B6 set
In order to re-engage, the correct procedure is to toggle AND(EN1,EN2) then read the
DIAG2 SPI register (to verify that bit B6 is set).
Toggling of AND(EN1,EN2) will re-engage the output commands (EN_PWM = "111")
while subsequent reading of DIAG2 register will re-engage HS/LS drivers supply
(REG_OFF = '0') and release FS_FLAG.
In order to avoid activating output commands while regulators that supply the HS and
LS FET drivers are in power-up phase (this could generate current shape distortion)
4.1.1 SDO
BST_DIS_EN EN_VBOV
EN_VBUV
EN_THSD
SC_HS1
SC_HS0
SC_LS1
SC_LS0
VccOV2
VccOV1
VBOV2
VBOV1
CMD1 0 0 1 - -
GCR_INT_I
Undefined
Undefined
Undefined
Undefined
VOVTST
SHT_PH
VSCTST
ShortPH
CMD2 0 1 0 - - -
REGOFF_EN DIS_BSTov
TRIM24
TRIM23
TRIM22
TRIM21
TRIM20
TRIM14
TRIM13
TRIM12
TRIM10
TRIM11
CMD3 0 1 1 - -
VSCHS1 EN_VSCHS1
VSCHS2 EN_VSCHS2
VSCHS3 EN_VSCHS3
VSCLS1 EN_VSCLS1
VSCLS2 EN_VSCLS2
VSCLS3 EN_VSCLS3
EN_UV_HS
EN_UV_LS
EN_VccOV
EN_VccUV
CMD4 1 0 0 - -
AND(EN1_EN2)_RB UV_HS
UV_LS
THSD
REGOFF_RB
BST_C_OV
GCR_STG
GCR_OL
EN1_RB
1. SDO CMD1 to CMD4 registers - Response to SDI commands: B(15:13)=000 till 100
SDO responds in the current SPI cycle with the content of the command register CMDn
(n=1 to 4) that is being addressed in the previous SPI cycle. In such a way the controller
may verify the command data being stored in the proper register (WE=1 in the previous SPI
cycle), or simply verify the correct IC data retention of initially programmed commands
(WE=0).
Effects described in the following sections take into account that the corresponding Fault
Enable bit is set to '1'.
drivers are restarted by cycling EN signal (internal AND of EN1 and EN2 pins)
from high to low to high. A SPI diagnostic read cycle clears the SPI diagnostic flag
and releases the FS_FLAG pin to high.
5 Application circuit
RRB1 C
RB1 R
RB3
Keep this loop D2
RRB2 TRB2
area small
D1 CBST2
D3
C LBST TRB1
BST1
D4
C
IN
BST_C BGND BST_L
_ D5
VB BATTERY
Power
VCC
VDH
C CHB
VCC
Supply
CBS1 T THS2 T
HS1 HS3
CBS1
R RGHS12 R
GHS11 GHS13
VDD GHS1
SHS1 RGHS21 RGHS22 RGHS23
CVDD
CBS2
CBS2
PWM H1
GHS2 RSHUNT1 BLDC
SHS2
PWM L1
PWM H2 CBS3
RSHUNT2 Motor
L9907
CBS3
PWM L2
PWM H3
GHS3
PWM L3
SHS3
TLS1 T TLS3
LS2
EN1
MCU
R RGLS12 R
EN2 GLS11 GLS13
GLS1
BST_DIS
SLS1
RGLS21 RGLS22 RGLS23
FS FLAG
SDI
GLS2
CS SLS2
SCK
GLS3
SDO
SLS3
VCAP
TM CLSD
TO3 IS1+
R
IB1 IS1-
IB1
RIB2
IB2 IS2+
RGCR
5.2 48 V system
Figure 9. Application circuit, 48 V system
Reverse battery protection
RRB1 C
R RB1 RRB3
BP1
Keep this loop CBP D
2 R T
area small RB2 RB2
D CBST2
1 CIN R D
CBST1 L T BP2 3
BST BP T
RB1
Power
VCC
VDH
CVCC C
HB
Supply
CBS1 THS1 T THS3
HS2
C
BS1
RGHS11 RGHS12 RGHS13
VDD GHS1
SHS1
C RGHS21 RGHS22 RGHS23
VDD
CBS2
CBS2
PWM H1
GHS2 RSHUNT1 BLDC
SHS2
PWM L1
PWM H2 CBS3
R
SHUNT2
Motor
L9907
C
PWM L2 BS3
PWM H3
GHS3
PWM L3
SHS3
TLS1 T T
LS2 LS3
EN1
MCU
R RGLS12 R
EN2 GLS11 GLS13
GLS1
BST_DIS
SLS1
RGLS21 RGLS22 RGLS23
FS FLAG
SDI
GLS2
CS SLS2
SCK
GLS3
SDO
SLS3
VCAP
TM CLSD
TO3 IS1+
R
IB1 IS1-
IB1
RIB2
IB2 IS2+
R
GCR
STL225N6F7
TRB1 STD105N10F7AG(1) -
AG(1)
TRB2 BCP56-16 -
TBP - BCP56-16 -
STL225N6F7
THSx STD105N10F7AG(1) X = 1, 2, 3
AG(1)
STL225N6F7
TLSx STD105N10F7AG(1) X = 1, 2, 3
AG(1)
1. Actual part number must be carefully selected according to the application current consumption estimation.
6 Package information
E2
D1/4
E1/4
4x N/4 TIPS
SECTION A-A
aaa C A-B D ș ș
bbb H A-B D 4x
(N-4) x e
R1
C
A H R2
A2 A1 b ccc C
ddd M A D
ņ 0.05 GAUGE PLANE
0.25
D S ș
D1 L
ș
D (L1)
SECTION B-B
1
E1/4 (b)
2
3
WITH PLATING
A B
D1/4 c c1
E1 E
b1 BASE METAL
A A
(see SECTION A-A)
TOP VIEW
7278840_G_9I GAPGPS03451
Table 38. TQFP64 (10x10x1 mm exp. pad down) package mechanical data
Dimensions
Ө 0° 3.5° 6° 0° 3.5° 6°
Ө1 0° - - 0° - -
Ө2 11° 12° 13° 11° 12° 13°
Ө3 11° 12° 13° 11° 12° 13°
A - - 1.20 - - 0.0472
A1 0.05 - 0.15 0.002 - 0.0059
A2 0.95 1.0 1.05 0.0374 0.0394 0.0413
b 0.17 0.22 0.27 0.0067 0.0079 0.0091
b1 0.17 0.20 0.23 0.0067 0.0079 0.0091
c 0.9 - 0.20 0.0354 - 0.0079
c1 0.9 - 0.16 0.0354 - 0.0063
D - 12.00 BSC - - 0.4724 BSC -
(2)
D1 - 10.00 BSC - - 0.3937 BSC -
D2 VARIATION
e - 0.50 BSC - - 0.0197 BSC -
E - 12.00 BSC - - 0.4724 BSC -
(2)
E1 - 10.00 BSC - - 0.3937 BSC -
E2 VARIATION
L 0.45 0.60 0.75 0.0177 0.0236 0.0295
L1 - 1.00 REF - - 0.0394 REF -
N - 64.00 - - 2.5197 -
R1 0.08 - - 0.0031 - -
R2 0.08 - 0.20 0.0031 - 0.0079
S 0.20 - - 0.0079 - -
TOLERANCE OF FORM AND POSITION
aaa - 0.20 - - 0.0079 -
bbb - 0.20 - - 0.0079 -
ccc - 0.08 - - 0.0031 -
ddd - 0.07 - - 0.0028 -
VARIATIONS
Option A
D2 - 4.50 - - 0.1772 -
Table 38. TQFP64 (10x10x1 mm exp. pad down) package mechanical data (continued)
Dimensions
E2 - 4.50 - - 0.1772 -
Option B
D2 - 6.0 - - 0.2362 -
E2 - 6.0 - - 0.2362 -
1. Values in mm are converted into inches and rounded to 4 decimal digits.
2. Dimensions D1 and E1 do not include mold flash or protrusions.
Allowable mold flash or protrusion is “0.25 mm” per side.
7 Revision history
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