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Vnd5e025ay e

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VND5E025AY-E

Double channel high-side driver with analog current sense


for automotive applications
Datasheet − production data

Features
Max transient supply voltage VCC 41V
Operating voltage range VCC 4.5 V to 28 V
Typ on-state resistance (per ch.) RON 25 mΩ PowerSSO-36

Current limitation (typ) ILIMH 47 A – Inrush current active management by


power limitation
Off state supply current IS 2 µA(1)
1. Typical value with all loads connected.
Applications
■ All types of resistive, inductive and capacitive
■ General loads
– Very low standby current
– 3 V CMOS compatible inputs
Description
– Optimized electromagnetic emissions
– Very low electromagnetic susceptibility The VND5E025AY-E is a double-channel
– Compliance with European directive high-side driver manufactured using
2002/95/EC STMicroelectronics® proprietary VIPower®
M0-5 technology and housed in PowerSSO-36
– Very low current sense leakage
package. The VND5E025AY-E is designed to
■ Diagnostic functions drive 12 V automotive grounded loads, and to
– Proportional load current sense provide protection and diagnostics. It also
– OFF-state open-load detection implements a 3 V and 5 V CMOS-compatible
– Current sense disable interface for use with any microcontroller.
– Thermal shutdown indication The device integrates advanced protective
– Output short to VCC detection functions such as load current limitation, inrush
– Over load and short to ground (power and overload active management by power
limitation) indication limitation, overtemperature shut-off with auto-
restart and overvoltage active clamp.
■ Protection
– Undervoltage shutdown A dedicated analog current sense pin is
associated with every output channel providing
– Over voltage clamp
enhanced diagnostic functions including fast
– Load current limitation detection of overload and short-circuit to ground
– Self limiting of fast thermal transients through power limitation indication,
– Protection against loss of ground and loss overtemperature indication, short-circuit to VCC
of VCC diagnosis.
– Over temperature shutdown with The current sensing and diagnostic feedback of
autorestart (thermal shutdown) the whole device can be disabled by pulling the
– Reverse battery protection with self switch CS_DIS pin high to share the external sense
on of the Power MOSFET resistor with similar devices.
– Electrostatic discharge protection

September 2013 Doc ID 17703 Rev 4 1/37


This is information on a product in full production. www.st.com 1
Contents VND5E025AY-E

Contents

1 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.4 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.5 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.1 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.2 MCU I/Os protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.3 Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.1 Short to VCC and off-state open-load detection . . . . . . . . . . . . . . . . . . . 26
3.4 Maximum demagnetization energy (VCC = 13.5 V) . . . . . . . . . . . . . . . . . 28

4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29


4.1 PowerSSO-36 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.1 ECOPACK® . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

5.2 PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32


5.3 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

6 Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

7 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

2/37 Doc ID 17703 Rev 4


VND5E025AY-E List of tables

List of tables

Table 1. Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5


Table 2. Suggested connections for unused and not connected pins . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 4. Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 6. Switching (VCC = 13 V; Tj = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. Current sense (8 V < VCC < 18 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 8. Open-load detection (8 V < VCC < 18 V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 9. Protections and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 10. Logic inputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 11. Truth table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 12. Electrical transient requirements (part 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 13. Electrical transient requirements (part 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 14. Electrical transient requirements (part 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Table 15. Thermal parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table 16. PowerSSO-36 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Table 17. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table 18. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Doc ID 17703 Rev 4 3/37


List of figures VND5E025AY-E

List of figures

Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5


Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 5. Open-load off-state delay timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 6. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure 7. Delay response time between rising edge of output current and rising edge of current sense
(CS enabled)14
Figure 8. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 9. IOUT/ISENSE vs IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 10. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 11. Normal operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. Overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 13. Intermittent overload . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 14. Short to VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 15. TJ evolution in overload or short to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 16. Off-state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 17. High-level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 18. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 19. High-level input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 20. Low-level input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 21. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 22. On-state resistance vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 23. On-state resistance vs VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 24. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 25. ILIMH vs Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 26. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 27. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 28. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 29. Low-level CS_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 30. High-level CS_DIS voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 31. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 32. Current sense and diagnostic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 33. Maximum turn off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 34. PowerSSO-36 PC board. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 35. Rthj-amb vs PCB copper area in open box free air condition (one channel on) . . . . . . . . . . 30
Figure 36. PowerSSO-36 thermal impedance junction ambient single pulse (one channel on) . . . . . 30
Figure 37. Thermal fitting model of a double-channel HSD in PowerSSO-36 . . . . . . . . . . . . . . . . . . 31
Figure 38. PowerSSO-36 package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 39. PowerSSO-36 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 40. PowerSSO-36 tape and reel shipment (suffix “TR”) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

4/37 Doc ID 17703 Rev 4


VND5E025AY-E Block diagram and pin description

1 Block diagram and pin description

Figure 1. Block diagram


VCC

Signal Clamp Reverse


Battery
Protection
Control & Diagnostic 2
Undervoltage
Control & Diagnostic 1 Power
Clamp

IN1 DRIVER

IN2 VON CH 1
Limitation

Over Current
temp. Limitation

CS_
DIS VSENSEH

CS1 Current
Sense CH 2
OUT2
CS2
Fault
OUT1
OVERLOAD PROTECTION
LOGIC (ACTIVE POWER LIMITATION)

GND

Table 1. Pin function


Name Function

VCC Battery connection

OUT1,2 Power output

GND Ground connection

Voltage controlled input pins with hysteresis, CMOS compatible. They controls
IN1,2
output switch state

CS1,2 Analog current sense pins, they deliver a current proportional to the load current

CS_DIS Active high CMOS compatible pin, to disable the current sense pin

Doc ID 17703 Rev 4 5/37


Block diagram and pin description VND5E025AY-E

Figure 2. Configuration diagram (top view)

/$ /$
/$ /$
065 065
065 065
065 065
065 065
065 065
065 065
065 065
/$ /$
/$ /$
/$ /$
*/ */
/$ /$
$4 $4
/$ /$
/$ /$
(/% $4@%*4

5"#7 $$

("1($'5

Table 2. Suggested connections for unused and not connected pins


Connection /
Current sense N.C. Output Input CS_DIS
pin

Floating Not allowed X(1) X X X


Through 1 KΩ Through 10 KΩ Through 10 KΩ
To ground X Not allowed
resistor resistor resistor
1. X: do not care.

6/37 Doc ID 17703 Rev 4


VND5E025AY-E Electrical specifications

2 Electrical specifications

Figure 3. Current and voltage conventions


IS
VCC
VFn VCC
IOUT1
ICSD
CS_DIS OUT1
VCSD ISENSE1 VOUT1
IIN1
CS1
IN1
VIN1 IOUT2 VSENSE1
IIN2
OUT2
IN2
ISENSE2 VOUT2
VIN2
CS2
GND
VSENSE2
IGND

2.1 Absolute maximum ratings


Stressing the device above the rating listed in the Table 3 may cause permanent damage to
the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the operating sections of this specification is not implied.
Exposure to the conditions in table below for extended periods may affect device reliability.

Table 3. Absolute maximum ratings


Symbol Parameter Value Unit

VCC DC supply voltage 41 V


-VCC Reverse DC supply voltage 16 V
Maximum supply voltage for full protection to short-circuit
VCC_LSC 18 V
(AEC-Q100-012)
IOUT DC output current Internally limited A
-IOUT Reverse DC output current 35 A
IIN DC input current -1 to 10 mA
ICSD DC current sense disable input current -1 to 10 mA
VCC - 41 V
VCSENSE Current sense maximum voltage
+VCC V
Maximum switching energy (single pulse)
EMAX (L = 0.26 mH; RL = 0 Ω; VBAT = 13.5 V; Tjstart = 150°C; 29 mJ
IOUT = IlimL(Typ.))

Doc ID 17703 Rev 4 7/37


Electrical specifications VND5E025AY-E

Table 3. Absolute maximum ratings (continued)


Symbol Parameter Value Unit

Electrostatic discharge
(human body model: R = 1.5 KΩ; C = 100 pF)
– IN 4000
VESD – CS 2000 V
– CS_DIS 4000
– OUT 5000
– VCC 5000
VESD Charge device model (CDM-AEC-Q100-011) 750 V
Tj Junction operating temperature -40 to 150 °C
Tstg Storage temperature -55 to 150 °C

2.2 Thermal data


Table 4. Thermal data
Symbol Parameter Maximum value Unit

Rthj-case Thermal resistance junction-case (with one channel on) 1.4 °C/W
See Figure 35 in the
Rthj-amb Thermal resistance junction-ambient (MAX) °C/W
thermal section

8/37 Doc ID 17703 Rev 4


VND5E025AY-E Electrical specifications

2.3 Electrical characteristics


Values specified in this section are for 8 V < VCC < 28 V; -40°C < Tj < 150°C, unless
otherwise specified.

Table 5. Power section


Symbol Parameter Test conditions Min. Typ. Max. Unit

VCC Operating supply voltage 4.5 13 28 V


VUSD Undervoltage shutdown 3.5 4.5 V
Undervoltage shutdown
VUSDhyst 0.5 V
hysteresis
IOUT = 3 A; Tj = 25°C 25
RON ON-state resistance IOUT = 3 A; Tj = 150°C 50 mΩ
IOUT = 3 A; VCC = 5 V; Tj = 25°C 35
Reverse battery VCC = -13 V; IOUT = -3 A;
RON REV 25 mΩ
ON-state resistance Tj = 25°C
Vclamp Clamp voltage IS = 20 mA 41 46 52 V
Off-state: VCC = 13 V;Tj = 25°C;
2(1) 5(1) µA
VIN = VOUT = VSENSE = VCSD = 0 V
IS Supply current
On-state: VCC = 13 V; VIN = 5 V;
3.5 6.5 mA
IOUT = 0 A
VIN = VOUT = 0 V; VCC = 13 V;
0 0.01 3
OFF-state Tj = 25°C
IL(off) µA
output current (2) VIN = VOUT = 0 V; VCC = 13 V;
0 5
Tj = 125°C
1. PowerMOS leakage included.
2. For each channel.

Table 6. Switching (VCC = 13 V; Tj = 25 °C)


a

Symbol Parameter Test conditions Min. Typ. Max. Unit

td(on) Turn-on delay time RL = 4.3 Ω (see Figure 6) — 20 — µs


td(off) Turn-off delay time RL = 4.3 Ω (see Figure 6) — 20 — µs
Turn-on voltage See
(dVOUT/dt)on RL = 4.3 Ω — — V/µs
slope Figure 26
Turn-off voltage See
(dVOUT/dt)off RL = 4.3 Ω — — V/µs
slope Figure 27
Switching energy
WON RL = 4.3 Ω (see Figure 6) — 0.25 — mJ
losses during twon
Switching energy
WOFF RL = 4.3 Ω (see Figure 6) — 0.3 — mJ
losses during twoff

Doc ID 17703 Rev 4 9/37


Electrical specifications VND5E025AY-E

Table 7. Current sense (8 V < VCC < 18 V)


)

Symbol Parameter Test conditions Min. Typ. Max. Unit

IOUT = 0.5 A; VSENSE = 0.5 V


K0 IOUT/ISENSE 1000 2900 5000
Tj = -40°C to 150°C
IOUT = 2 A; VSENSE = 0.5 V
K1 IOUT/ISENSE Tj = -40°C to 150°C 1900 3000 3810
Tj = 25°C to 150°C 2240 3000 3520
IOUT = 2 A; VSENSE = 0.5 V;
dK1/K1(1) Current sense ratio drift VCSD = 0 V; -9 9 %
Tj = -40°C to 150°C
IOUT = 3 A; VSENSE = 4 V
K2 IOUT/ISENSE Tj = -40 °C to 150 °C 2230 3000 3550
Tj = 25 °C to 150 °C 2460 3000 3350
IOUT = 3 A; VSENSE = 4 V;
dK2/K2(1) Current sense ratio drift VCSD = 0 V; -6 6 %
Tj = -40°C to 150°C
IOUT = 10 A; VSENSE = 4 V
K3 IOUT/ISENSE Tj = -40°C to 150°C 2710 2900 3150
Tj = 25°C to 150°C 2780 2900 3080
IOUT = 10 A; VSENSE = 4 V;
dK3/K3(1) Current sense ratio drift VCSD = 0 V; -3 3 %
Tj = -40°C to 150°C
IOUT = 0 A; VSENSE = 0 V;
VCSD = 5 V; VIN = 0 V; 0 1
Tj = -40°C to 150°C
Analog sense leakage IOUT = 0 A; VSENSE = 0 V;
ISENSE0 µA
current VCSD = 0 V; VIN = 5 V; 0 2
Tj = -40°C to 150°C
IOUT = 3 A; VSENSE = 0 V;
0 1
VCSD = VIN = 5 V;
Max analog sense output
VSENSE IOUT = 15 A; VCSD = 0 V 5 V
voltage
Analog sense output
VSENSEH VCC = 13 V; RSENSE = 10 KΩ 8 V
voltage in fault condition(2)
Analog sense output
ISENSEH VCC = 13 V; VSENSE = 5 V 9 mA
current in fault condition(2)
VSENSE < 4 V;
Delay response time from 0.5 A < IOUT < 10 A;
tDSENSE1H 20 100 µs
falling edge of CS_DIS pin ISENSE = 90% of ISENSE max
(see Figure 4)
VSENSE < 4 V;
Delay response time from 0.5 A < IOUT < 10 A;
tDSENSE1L 5 20 µs
rising edge of CS_DIS pin ISENSE = 10 % of ISENSE max
(see Figure 4)

10/37 Doc ID 17703 Rev 4


VND5E025AY-E Electrical specifications

Table 7. Current sense (8 V < VCC < 18 V) (continued)


Symbol Parameter Test conditions Min. Typ. Max. Unit

VSENSE < 4 V;
Delay response time from
0.5 A < IOUT < 10 A;
tDSENSE2H rising edge of 70 300 µs
ISENSE = 90 % of ISENSE max
IN pin
(see Figure 4)

Delay response time VSENSE < 4V;


between rising edge of ISENSE = 90 % of ISENSEMAX,
ΔtDSENSE2H 100 µs
output current and rising IOUT = 90 % of IOUTMAX
edge of current sense IOUTMAX = 3 A (see Figure 7)
VSENSE < 4 V;
Delay response time from
0.5 A < IOUT < 10 A;
tDSENSE2L falling edge of 5 50 µs
ISENSE = 10 % of ISENSE max
IN pin
(see Figure 4)
1. Parameter guaranteed by design; it is not tested.
2. Fault condition includes: power limitation, overtemperature and open-load OFF-state detection.

Table 8. Open-load detection (8 V < VCC < 18 V)


Symbol Parameter Test conditions Min. Typ. Max. Unit

Open-load off-state voltage


VOL VIN = 0 V; 8 V < VCC < 18 V 2 — 4 V
detection threshold
VIN = 5 V;
Open-load on-state current
IOL 8 V < VCC < 18 V; — 45 mA
detection threshold
ISENSE = 5 µA
Output short circuit to Vcc
tDSTKON See Figure 5 180 — 1200 µs
detection delay at turn off
Delay response from output
VIN = 0 V; VOUT = 4 V;
td_vol rising edge to VSENSE rising — 20 µs
VSENSE = 90 % of VSENSEH
edge in open-load
ILOFF2 Off-state output current VOUT = 4 V -75 — 0 µA

Table 9. Protections and diagnostics(1)


Symbol Parameter Test conditions Min. Typ. Max. Unit

DC short-circuit VCC = 13 V 33 47 66 A
IlimH
current 5 V < VCC < 18 V 66
Short-circuit current
IlimL VCC = 13 V; TR < Tj < TTSD 12 A
during thermal cycling
Shutdown
TTSD 150 175 200 °C
temperature
TR Reset temperature TRS + 1 TRS + 5 °C
Thermal reset of
TRS 135 °C
status

Doc ID 17703 Rev 4 11/37


Electrical specifications VND5E025AY-E

Table 9. Protections and diagnostics(1) (continued)


Symbol Parameter Test conditions Min. Typ. Max. Unit

Thermal hysteresis
THYST 7 °C
(TTSD - TR)
IOUT = 2 A; VIN = 0 V;
VCC - 39 VCC - 46 VCC - 52 V
Turn-off output voltage L = 6 mH; Tj = -40°C
VDEMAG
clamp I = 2 A; V = 0;
OUT IN VCC - 41 VCC - 46 VCC - 52 V
L = 6 mH; 25°C < Tj < 150°C
IOUT = 0.1 A;
Output voltage drop
VON Tj = -40°C to150°C 25 mV
limitation (see Figure 8)
1. To ensure long term reliability under heavy overload or short-circuit conditions, protection and related
diagnostic signals must be used together with a proper software strategy. If the device is subjected to
abnormal conditions, this software must limit the duration and number of activation cycles.

Table 10. Logic inputs


Symbol Parameter Test conditions Min. Typ. Max. Unit

VIL Low-level input voltage 0.9 V


IIL Low-level input current VIN = 0.9 V 1 µA
VIH High-level input voltage 2.1 V
IIH High-level input current VIN = 2.1 V 10 µA
VI(hyst) Input hysteresis voltage 0.25 V
IIN = 1 mA 5.5 7
VICL Input clamp voltage V
IIN = -1 mA -0.7
VCSDL Low-level CS_DIS voltage 0.9 V
ICSDL Low-level CS_DIS current VCSD = 0.9 V 1 µA
VCSDH High-level CS_DIS voltage 2.1 V
ICSDH High-level CS_DIS current VCSD = 2.1 V 10 µA
VCSD(hyst) CS_DIS hysteresis voltage 0.25 V
ICSD = 1 mA 5.5 7
VCSCL CS_DIS clamp voltage V
ICSD = -1 mA -0.7

12/37 Doc ID 17703 Rev 4


VND5E025AY-E Electrical specifications

Figure 4. Current sense delay characteristics

INPUT
CS_DIS
LOAD CURRENT
CURRENT SENSE
tDSENSE2H tDSENSE1L tDSENSE1H tDSENSE2L

Figure 5. Open-load off-state delay timing

OUTPUT STUCK TO VCC

VIN
VOUT > VOL

VSENSEH

VCS

tDSTKON

Figure 6. Switching characteristics


VOUT
tWon tWoff

90%
80%

dVOUT/dt(on) dVOUT/dt(off)

tr 10% tf
t

INPUT
td(on) td(off)

Doc ID 17703 Rev 4 13/37


Electrical specifications VND5E025AY-E

Figure 7. Delay response time between rising edge of output current and rising
edge of current sense (CS enabled)

VIN

ΔtDSENSE2H

IOUT
IOUTMAX

90% IOUTMAX

ISENSE ISENSEMAX

90% ISENSEMAX

Figure 8. Output voltage drop limitation

Vcc-Vout

Tj=150oC Tj=25oC

Tj=-40oC

Von

Iout
Von/Ron(T)

14/37 Doc ID 17703 Rev 4


VND5E025AY-E Electrical specifications

Figure 9. IOUT/ISENSE vs IOUT


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Figure 10. Maximum current sense ratio drift vs load current


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1. Parameter guaranteed by design; it is not tested.

Doc ID 17703 Rev 4 15/37


Electrical specifications VND5E025AY-E

Table 11. Truth table


Conditions Input Output Sense (VCSD = 0 V)(1)

L L 0
Normal operation
H H Nominal
L L 0
Overtemperature
H L VSENSEH
L L 0
Undervoltage
H L 0
H X Nominal
(no power limitation)
Overload
H Cycling VSENSEH
(power limitation)
Short-circuit to GND L L 0
(Power limitation) H L VSENSEH
short-circuit to VCC
L H VSENSEH
(external pull up
H H < Nominal
disconnected)
Negative output voltage
L L 0
clamp
1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents
and external circuit.

16/37 Doc ID 17703 Rev 4


VND5E025AY-E Electrical specifications

Table 12. Electrical transient requirements (part 1)


ISO 7637-2: Test levels(1) Number of
2004(E) Burst cycle/pulse Delays and
pulses or
repetition time impedance
Test pulse III IV test times

5000
1 -75 V -100 V 0.5 s 5s 2 ms, 10 Ω
pulses
5000
2a +37 V +50 V 0.2 s 5s 50 µs, 2 Ω
pulses

3a -100 V -150 V 1h 90 ms 100 ms 0.1 µs, 50 Ω

3b +75 V +100 V 1h 90 ms 100 ms 0.1 µs, 50 Ω

4 -6 V -7 V 1 pulse 100 ms, 0.01 Ω

5b(2) +65 V +87 V 1 pulse 400 ms, 2 Ω

1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b
2. Valid in case of external load dump clamp: 40V maximum referred to ground.

Table 13. Electrical transient requirements (part 2)


ISO 7637-2: Test level results(1)
2004(E)
Test pulse III IV

1 C C
2a C C
3a C C
3b C C
4 C C
(2)(3)
5b C C
1. The above test levels must be considered referred to VCC = 13.5 V except for pulse 5b
2. Valid in case of external load dump clamp: 40 V maximum referred to ground.
3. Suppressed load dump (pulse 5b) is withstood with a minimum load connected as specified in
Table 3: Absolute maximum ratings.

Table 14. Electrical transient requirements (part 3)


Class Contents

C All functions of the device are performed as designed after exposure to disturbance.
One or more functions of the device are not performed as designed after exposure to
E
disturbance and cannot be returned to proper operation without replacing the device.

Doc ID 17703 Rev 4 17/37


Electrical specifications VND5E025AY-E

2.4 Waveforms
Figure 11. Normal operation
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Figure 12. Overload or short to GND

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18/37 Doc ID 17703 Rev 4


VND5E025AY-E Electrical specifications

Figure 13. Intermittent overload


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Figure 14. Short to VCC


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Doc ID 17703 Rev 4 19/37


Electrical specifications VND5E025AY-E

Figure 15. TJ evolution in overload or short to GND


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20/37 Doc ID 17703 Rev 4


VND5E025AY-E Electrical specifications

2.5 Electrical characteristics curves

Figure 16. Off-state output current Figure 17. High-level input current

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Figure 18. Input clamp voltage Figure 19. High-level input voltage

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Figure 20. Low-level input voltage Figure 21. Input hysteresis voltage

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Doc ID 17703 Rev 4 21/37


Electrical specifications VND5E025AY-E

Figure 22. On-state resistance vs Tcase Figure 23. On-state resistance vs VCC

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Figure 24. Undervoltage shutdown Figure 25. ILIMH vs Tcase

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Figure 26. Turn-on voltage slope Figure 27. Turn-off voltage slope

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22/37 Doc ID 17703 Rev 4


VND5E025AY-E Electrical specifications

Figure 28. CS_DIS clamp voltage Figure 29. Low-level CS_DIS voltage

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Figure 30. High-level CS_DIS voltage

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Doc ID 17703 Rev 4 23/37


Application information VND5E025AY-E

3 Application information

Figure 31. Application schematic

9

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1. Channel 2 has the same internal circuit as channel 1.

3.1 Load dump protection


Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the
VCCPK max rating. The same applies if the device is subject to transients on the VCC line
that are greater than the ones shown in the ISO 7637-2: 2004(E) table.

3.2 MCU I/Os protection


When negative transients are present on the VCC line, the control pins are pulled negative to
approximately -1.5 V.
ST suggests the insertion of resistors (Rprot) in the lines to prevent the microcontroller I/O
pins from latching up.
The values of these resistors provide a compromise between the leakage current of the
microcontroller, the current required by the HSD I/Os (input levels compatibility) and the
latch-up limit of the microcontroller I/Os.

24/37 Doc ID 17703 Rev 4


VND5E025AY-E Application information

Equation 1

-VCCpeak / Ilatchup ≤ Rprot ≤ (VOHµC - VIH) / IIHmax

Calculation example:
For VCCpeak = -1.5 V; Ilatchup ≥ 20 mA; VOHµC ≥ 4.5 V

75 Ω ≤ Rprot ≤ 240 kΩ.


Recommended values: Rprot =10 kΩ, CEXT = 10 nF

3.3 Current sense and diagnostic


The current sense pin performs a double function (see Figure 32: Current sense and
diagnostic):

● Current mirror of the load current in normal operation, delivering a current


proportional to the load one according to a known ratio KX.
The current ISENSE can be easily converted to a voltage VSENSE by means of an
external resistor RSENSE. Linearity between IOUT and VSENSE is ensured up to 5 V
minimum (see parameter VSENSE in Table 7: Current sense (8 V < VCC < 18 V)). The
current sense accuracy depends on the output current (refer to current sense electrical
characteristics Table 7: Current sense (8 V < VCC < 18 V)).

● Diagnostic flag in fault conditions, delivering a fixed voltage VSENSEH up to a


maximum current ISENSEH in case of the following fault conditions (refer to
Table 11: Truth table):

– Power limitation activation


– Over temperature
– Short to VCC in off-state
– Open-load in off-state with additional external components.

A logic level high on CS_DIS pin sets at the same time all the current sense pins of the
device in a high-impedance state, thus disabling the current monitoring and diagnostic
detection. This feature allows multiplexing of the microcontroller analog inputs by sharing of
sense resistance and ADC line among different devices.

Doc ID 17703 Rev 4 25/37


Application information VND5E025AY-E

Figure 32. Current sense and diagnostic


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3.3.1 Short to VCC and off-state open-load detection


Short to VCC
A short-circuit between VCC and output is indicated by the relevant current sense pin set to
VSENSEH during the device OFF-state. Small or no current is delivered by the current sense
during the ON-state depending on the nature of the short-circuit.
Off-state open-load with external circuitry
Detection of an open load in off mode requires an external pull-up resistor RPU connecting
the output to a positive supply voltage VPU.
It is preferable VPU to be switched off during the module standby mode in order to avoid the
overall standby current consumption to increase in normal conditions, i.e. when load is
connected.
An external pull-down resistor RPD connected between output and GND is mandatory to
avoid misdetection in case of floating outputs in off-state (see Figure 32: Current sense and
diagnostic).

26/37 Doc ID 17703 Rev 4


VND5E025AY-E Application information

RPD must be selected in order to ensure VOUT < VOLmin unless pulled-up by the external
circuitry:

Equation 2

V OUT = R PD ⋅ I L(off2)f < V OLmin = 2V


Pull-up_OFF

RPD ≤ 22 kΩ is recommended.
For proper open load detection in off-state, the external pull-up resistor must be selected
according to the following formula:

Equation 3

( R PD ⋅ V PU ) – ( R PU ⋅ R PD ⋅ I L(off2)r )
V OUT = ----------------------------------------------------------------------------------------------- > V OLmax = 4V
Pull-up_ON ( R PU + R PD )
For the values of VOLmin,VOLmax, IL(off2)r and IL(off2)f (see Table 8: Open-load detection
(8 V < VCC < 18 V)).

Doc ID 17703 Rev 4 27/37


Application information VND5E025AY-E

3.4 Maximum demagnetization energy (VCC = 13.5 V)


Figure 33. Maximum turn off current versus inductance

A: Tjstart = 150 °C single pulse


B: Tjstart = 100 °C repetitive pulse
C: Tjstart = 125 °C repetitive pulse

VIN, IL

Demagnetization Demagnetization Demagnetization

1. Values are generated with RL = 0 Ω.


In case of repetitive pulses, Tjstart (at the beginning of each demagnetization) of every pulse must not
exceed the temperature specified above for curves A and B.

28/37 Doc ID 17703 Rev 4


VND5E025AY-E Package and PCB thermal data

4 Package and PCB thermal data

4.1 PowerSSO-36 thermal data


Figure 34. PowerSSO-36 PC board

1. Layout condition of Rth and Zth measurements (Board finish thickness 1.6 mm +/- 10%; Board double
layer; Board dimension 129 mm x 60 mm; Board Material FR4; Cu thickness 0.070 mm; Thermal vias
separation 1.2 mm; Thermal via diameter 0.3 mm +/- 0.08 mm; Cu thickness on vias 0.025 mm; Footprint
dimension 4.1 mm x 6.5 mm).

Doc ID 17703 Rev 4 29/37


Package and PCB thermal data VND5E025AY-E

Figure 35. Rthj-amb vs PCB copper area in open box free air condition (one channel
on)

Figure 36. PowerSSO-36 thermal impedance junction ambient single pulse (one
channel on)

Equation 4: pulse calculation formula

Z THδ = R TH ⋅ δ + Z THtp ( 1 – δ )

where δ = tP/T

30/37 Doc ID 17703 Rev 4


VND5E025AY-E Package and PCB thermal data

Figure 37. Thermal fitting model of a double-channel HSD in PowerSSO-36

1. The fitting model is a simplified thermal tool and is valid for transient evolutions where the embedded
protections (power limitation or thermal cycling during thermal shutdown) are not triggered.

Table 15. Thermal parameters


Area/island (cm2) Footprint 2 8

R1 = R7 (°C/W) 0.3

R2 = R8 (°C/W) 0.9

R3 (°C/W) 5

R4 (°C/W) 8

R5 (°C/W) 18 10 10

R6 (°C/W) 27 23 14

C1 = C7 (W.s/°C) 0.001

C2 = C8 (W.s/°C) 0.005

C3 (W.s/°C) 0.04

C4 (W.s/°C) 0.5

C5 (W.s/°C) 1 2 2

C6 (W.s/°C) 3 6 9

Doc ID 17703 Rev 4 31/37


Package information VND5E025AY-E

5 Package information

5.1 ECOPACK®
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

5.2 PowerSSO-36 mechanical data


Figure 38. PowerSSO-36 package dimensions

32/37 Doc ID 17703 Rev 4


VND5E025AY-E Package information

Table 16. PowerSSO-36 mechanical data


l

millimeters
Symbol
Min Typ Max

A 2.15 - 2.45
A2 2.15 - 2.35
a1 0 - 0.1
b 0.18 - 0.36
c 0.23 - 0.32
D 10.10 - 10.50
E 7.4 - 7.6
e - 0.5 -
e3 - 8.5 -
F - 2.3 -
G - - 0.1
H 10.1 - 10.5
h - - 0.4
k 0° - 8°
L 0.55 - 0.85
M - 4.3 -
N - - 10°
O - 1.2
Q - 0.8 -
S - 2.9 -
T - 3.65 -
U - 1.0 -
X(1) 4.3 - 5.2
Y(1) 6.9 - 7.5
1. Corresponding to internal variation C.

Doc ID 17703 Rev 4 33/37


Package information VND5E025AY-E

5.3 Packing information


Figure 39. PowerSSO-36 tube shipment (no suffix)

Base q.ty 49
Bulk q.ty 1225
Tube length (± 0.5) 532
C A 3.5
B B 13.8
C (± 0.1) 0.6
All dimensions are in mm.

Figure 40. PowerSSO-36 tape and reel shipment (suffix “TR”)

REEL DIMENSIONS

Base q.ty 1000


Bulk q.ty 1000
A (max) 330
B (min) 1.5
C (± 0.2) 13
F 20.2
G (+ 2 / -0) 24.4
N (min) 100
T (max) 30.4

TAPE DIMENSIONS
According to Electronic Industries Association
(EIA) Standard 481 rev. A, Feb 1986
Tape width W 24
Tape hole spacing P0 (± 0.1) 4
Component spacing P 12
Hole diameter D (± 0.05) 1.55
Hole diameter D1 (min) 1.5
Hole position F (± 0.1) 11.5
Compartment depth K (max) 2.85
Hole spacing P1 (± 0.1) 2

All dimensions are in mm. End

Start

Top No components Components No components


cover
tape 500mm min
Empty components pockets 500mm min
saled with cover tape.

User direction of feed

34/37 Doc ID 17703 Rev 4


VND5E025AY-E Device summary

6 Device summary

Table 17. Device summary


Order codes
Package
Tube Tape and reel

PowerSSO-36 VND5E025AY-E VND5E025AYTR-E

Doc ID 17703 Rev 4 35/37


Revision history VND5E025AY-E

7 Revision history

Table 18. Document revision history


Date Revision Changes

29-Jul-2010 1 Initial release.


Updated following figures:
– Figure 35: Rthj-amb vs PCB copper area in open box free air
condition (one channel on)
05-Aug-2010 2
– Figure 36: PowerSSO-36 thermal impedance junction ambient
single pulse (one channel on)
Updated Table 15: Thermal parameters
Changed document status from “Preliminary data“ to “Production
19-Jul-2012 3
data“
19-Sep-2013 4 Updated Disclaimer

36/37 Doc ID 17703 Rev 4


VND5E025AY-E

Please Read Carefully:

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Doc ID 17703 Rev 4 37/37

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