VIPER17

Off-line high voltage converters

Features
■ 800 V avalanche rugged power section DIP-7
■ PWM operation with frequency jittering for low
EMI
■ Operating frequency:
– 60 kHz for L type Description
– 115 kHz for H type The device is an off-line converter with an 800 V
■ Standby power < 50 mW at 265 Vac rugged power section, a PWM control, two levels
of over current protection, over voltage and
■ Limiting current with adjustable set point
overload protections, hysteretic thermal
■ Adjustable and accurate over voltage protection, soft-start and safe auto-restart after
protection any fault condition removal. Burst mode operation
■ On-board soft-start and device very low consumption helps to meet
the standby energy saving regulations.
■ Safe auto-restart after a fault condition
■ Hysteretic thermal shutdown Advance frequency jittering reduces EMI filter
cost. Brown-out function is embedded into the
high voltage start-up.
Application
■ Adapters for PDA, camcorders, shavers, Figure 1. Typical topology
cellular phones, videogames
■ Auxiliary power supply for LCD/PDP TV,
monitors, Audio systems, computer, industrial
■ SMPS for set-top boxes, DVD players and
recorders, white goods.

Table 1. Device summary

Order codes Package Packaging

VIPER17LN
DIP-7 Tube
VIPER17HN

February 2008 Rev 2 1/31

www.st.com 31
Contents VIPER17

Contents

1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2 Typical power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

3 Pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 Connection diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

4 Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.2 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

5 Typical electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

6 Typical circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

7 Operation descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.1 Power section and gate driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.2 High voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
7.3 Power-up and soft-start up . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
7.4 Power down operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.5 Auto restart operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.6 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
7.7 Current mode conversion with adjustable current limit set point . . . . . . . 19
7.8 Over Voltage Protection (OVP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
7.9 About CONT pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
7.10 Feed-back and Over Load Protection (OLP) . . . . . . . . . . . . . . . . . . . . . . 21
7.11 Burst-mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 24
7.12 Brown-out protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7.13 2nd level over current protection and hiccup mode . . . . . . . . . . . . . . . . . 27

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VIPER17 Contents

8 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

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Block diagram VIPER17

1 Block diagram

Figure 2. Block diagram

BR VDD
Vcc DRAIN

-
Vin_OK Internal Supply bus
+ SUPPLY HV_ON Istart-up
& & UVLO
0.45V Ref erence Voltages
15uA THERMAL
SHUTDOWN
OSCILLATOR
UVLO
SOFT OTP
START OCP - OCP
BLOCK BURST TURN-ON
CONT LOGIC S
Q
+
.
OVP PWM
+ LEB R1
LOGIC R2
-

6uA
+
OVP 2nd OCP
- LOGIC
Ref
OLP OVP OTP

Rsense
BURST-MODE
BURST
LOGIC

FB GND

2 Typical power

Table 2. Typical power

230 VAC 85-265 VAC
Part number
Adapter(1) Open frame(2) Adapter(1) Open frame(2)

VIPER17 9W 12 W 5W 7W
1. Typical continuous power in non ventilated enclosed adapter measured at 50 °C ambient.
2. Maximum practical continuous power in an open frame design at 50 °C ambient, with adequate heat sinking.

4/31
VIPER17 Pin settings

3 Pin settings

3.1 Connection diagram

Figure 3. Connection diagram (top view)

GND DRAIN

VDD DRAIN

CONT

FB BR

3.2 Pin description

Table 3. Pin description

N. Name Function

1 GND This pin represents the device ground and the source of the power section.
Supply voltage of the control section. This pin also provides the charging
2 VDD
current of the external capacitor during start-up time.
Control pin. The following functions can be selected:
1. current limit set point adjustment. The internal set default value of the cycle-
by-cycle current limit can be reduced by connecting to ground an external
3 CONT resistor.
2. output voltage monitoring. A voltage exceeding 3V shuts the IC down
reducing the device consumption. This function is strobed and digitally filtered
for high noise immunity.
Control input for duty cycle control. Internal current generator provides bias
current for loop regulation. A voltage below 0.5 V activates the burst-mode
4 FB
operation. A level close to 3.3 V means that we are approaching the cycle-by-
cycle over-current set point.
Brownout protection input with hysteresis. A voltage below 0.45 V shuts down
(not latch) the device and lowers the power consumption. Device operation
5 BR
restarts as the voltage exceeds 0.45 V plus hysteresis voltage. It can be
connected to ground when not used.
High voltage drain pin. The built-in high voltage switched start-up bias current is
7,8 DRAIN
drawn from this pin too.

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Electrical data VIPER17

4 Electrical data

4.1 Maximum ratings

Table 4. Absolute maximum ratings

Symbol Pin Parameter Value Unit

VDRAIN 7, 8 Drain-to-source (ground) voltage 800 V

EAV 7, 8 Repetitive avalanche energy (limited by TJ = 150 °C) 2 mJ
IAR 7, 8 Repetitive avalanche current (limited by TJ = 150 °C ) 0.6 A
IDRAIN 7, 8 Pulse drain current 0.7 A
VCONT 3 Control input pin voltage (with ICONT = 1 mA) Self limited V
VFB 4 Feedback voltage -0.3 to 5.5 V
VBR 5 Brown-out input pin voltage 2 V
VDD 2 Supply voltage (IDD = 25 mA) Self limited V
PTOT Power dissipation at TA < 50 °C 1 W
TJ Operating junction temperature range -40 to 150 °C
TSTG Storage temperature -55 to 150 °C

4.2 Thermal data

Table 5. Thermal data

Symbol Parameter Max value Unit

RthJP Thermal resistance junction pin 40 °C/W

90 °C/W
RthJA Thermal resistance junction ambient
80 (1) °C/W
2
1. When mounted on a standard single side FR4 board whit 200 mm (0.31 sq in) Of Cu (35 m thick)

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VIPER17 Electrical data

4.3 Electrical characteristics

(TJ = -25 to 125 °C, VDD = 14 V; unless otherwise specified)

Table 6. Power section

Symbol Parameter Test condition Min Typ Max Unit

IDRAIN = 1 mA, VFB = GND

VBVDSS Break-down voltage 800 V
TJ = 25 °C
VDRAIN = max rating,
IOFF OFF state drain current 60 µA
VFB = GND
IDRAIN = 0.2 A, VFB = 3 V,
20 24 Ω
Drain-source on state VBR = GND, TJ = 25 °C
RDS(on)
resistance IDRAIN = 0.2 A, VFB = 3 V,
40 48 Ω
VBR = GND, TJ = 125 °C
Effective (energy related)
COSS VDRAIN = 0 to 640 V 10 pF
output capacitance

Table 7. Supply section

Symbol Parameter Test condition Min Typ Max Unit

Voltage

VDRAIN_START Drain-source start voltage 60 80 100 V

VDRAIN = 120 V,
VBR = GND, VFB = GND, -2 -3 -4 mA
VDD = 4 V
IDD_CH Start up charging current
VDRAIN = 120 V ,
VBR = GND, VFB = GND, -0.4 -0.6 -0.8 mA
VDD = 4 V after fault.
VDD Operating voltage range After turn-on 8.5 23.5 V
VDDclamp VDD clamp voltage IDD = 20 mA 23.5 V
VDDon VDD start up threshold 13 14 15 V
VDRAIN = 120 V,
VDD under voltage VBR = GND, VFB = GND
VDDoff 7.5 8 8.5 V
shutdown threshold
VDD restart voltage VDRAIN = 120 V,
VDD(RESTART) 4 4.5 5 V
threshold VBR = GND, VFB = GND
Current

Operating supply current, VFB = GND, FSW = 0 kHz,

IDD0 0.9 mA
not switching VBR = GND, VDD = 10 V
Operating supply current, VDRAIN = 120 V,
IDD1 1.8 mA
switching FSW = 60 kHz
VDRAIN = 120 V,
2 mA
FSW = 115 kHz
Operating supply current,
IDD_FAULT 400 uA
with protection tripping
Operating supply current
IDD_OFF VDD = 7 V 270 uA
with VDD < VDD_OFF

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Electrical data VIPER17

Table 8. Controller section

(TJ = -25 to 125 °C, VDD = 14 V; unless otherwise specified)
Symbol Parameter Test condition Min Typ Max Unit

Feedback pin

Over load shut down

VFB_olp 4.7 4.8 5.2 V
threshold
VFB_lin Linear dynamics upper limit 3.2 3.3 3.4 V
VFB_bm Burst mode threshold Voltage falling 0.5 V
VFB_bm_hys Burst mode hysteresis Voltage rising 50 mV
VFB = 0.3 V -150 -200 -280 uA
IFB Feedback sourced current
3.3 V < VFB < 4.8 V -3 uA
RFB(DYN) Dynamic resistance VFB < 3.3 V 14 19 kΩ
HFB ∆VFB / ∆ID 4 9 V/A

CONT pin

VCONT_l Low level clamp voltage ICONT = -100 uA 0.5 V

Current limitation

VFB = 4 V,
IDlim Max drain current limitation ICONT = -10 µA 0.38 0.4 0.42 A
TJ = 25 °C
tSS Soft-start time 8.5 ms
TON_MIN Minimum turn ON time 400 ns
td Propagation delay 150 ns
tLEB Leading edge blanking 300 ns
Peak drain current during
ID_BM VFB = 0.6 V 90 mA
burst mode

Oscillator section

VIPER17L VDD = operating 54 60 66 kHz

FOSC voltage range,
VIPER17H VFB = 1 V 103 115 127 kHz

VIPER17L ±4 kHz
FD Modulation depth
VIPER17H ±8 kHz
FM Modulation frequency 250 Hz
DMAX Maximum duty cycle 70 80 %

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VIPER17 Electrical data

Table 8. Controller section (continued)

(TJ = -25 to 125 °C, VDD = 14 V; unless otherwise specified)
Symbol Parameter Test condition Min Typ Max Unit

Over current protection ( 2nd OCP )

Second over current

IDMAX 0.6 A
threshold

Over voltage protection

Over voltage protection

VOVP 2.7 3 3.3 V
threshold
Over voltage protection
TSTROBE 2.2 us
strobe time

Brown out protection

VBRth Brown out threshold 0.41 0.45 0.49 V

Voltage hysteresis above
VBR Hyst 50 mV
VBRth Voltage falling
IBR Hyst Current hysteresis 7 10 uA
VBR Operating range 0.15 2 V
VDIS Brown out disable voltage 50 150 mV

Thermal shutdown

Thermal shutdown
TSD 150 170 °C
temperature
Thermal shutdown
THYST 30 °C
hysteresis

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Electrical data VIPER17

Figure 4. Minimum turn-on time test circuit

Figure 5. Brown out threshold test circuits

Figure 6. OVP threshold test circuits

(The OVP protection is triggered

after four consecutive oscillator cycles)

10/31
VIPER17 Typical electrical characteristics

5 Typical electrical characteristics

Figure 7. Current limit vs TJ Figure 8. Switching frequency vs TJ

Figure 9. Drain start voltage vs TJ Figure 10. HFB vs TJ

Figure 11. Brown out threshold vs TJ Figure 12. Brown out hysteresis vs TJ

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Typical electrical characteristics VIPER17

Figure 13. Brown out hysteresis current Figure 14. Operating supply current
vs TJ (no switching) vs TJ

Figure 15. Operating supply current Figure 16. current limit vs RLIM
(switching) vs TJ

Figure 17. Power MOSFET on-resistance Figure 18. Power MOSFET break down
vs TJ voltage vs TJ

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VIPER17 Typical electrical characteristics

Figure 19. Thermal shutdown

TJ

TSD

THYST

t
VDD

VDD ON

VDD OFF

VDD RESTART

t
VDS

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Typical circuit VIPER17

6 Typical circuit

Figure 20. Flyback application (basic)

D3 Vout

AC IN R1
C2
BR
C1 C5

AC IN
D1

GND

R2 D2
R3

OPTO
VVcc
DD DRAIN
R5
BR
CONTROL
C3 R4 C6
CONT
FB SOURCE
GND
U2

C4 R6

Figure 21. Flyback application

D3 Vout

AC IN Rh R1
C2
BR
C1 C5

AC IN Rl
D1

Rov p Daux GND

R2 D2

R3

OPTO
VVcc
DD DRAIN
R5
BR
CONTROL
C3 C6
R4
CONT
FB SOURCE
GND
U2

Rlim

C4 R6

14/31
VIPER17 Operation descriptions

7 Operation descriptions

VIPER17 is a high-performance low-voltage PWM controller chip with an 800 V, avalanche

rugged Power section.
The controller includes: the oscillator with jittering feature, the start up circuits with soft-start
feature, the PWM logic, the current limit circuit with adjustable set point, the second over
current circuit, the burst mode management, the brown-out circuit, the UVLO circuit, the
auto-restart circuit and the thermal protection circuit.
The current limit set-point is set by the CONT pin. The burst mode operation guaranties high
performance in the stand-by mode and helps in the energy saving norm accomplishment.
All the fault protections are built in Auto Restart Mode with very low repetition rate to prevent
IC's over heating.

7.1 Power section and gate driver

The Power section is implemented with an avalanche ruggedness N-channel MOSFET,
which guarantees safe operation within the specified energy rating as well as high dv/dt
capability. The Power section has a BVDSS of 800 V min. and a typical RDS(on) of 20 Ω
at 25 °C.
The integrated SenseFET structure allows a virtually loss-less current sensing.
The gate driver is designed to supply a controlled gate current during both turn-on and turn-
off in order to minimize common mode EMI. Under UVLO conditions an internal pull-down
circuit holds the gate low in order to ensure that the Power section cannot be turned on
accidentally.

7.2 High voltage startup generator

The HV current generator is supplied through the DRAIN pin and it is enabled only if the
input bulk capacitor voltage is higher than VDRAIN_START Threshold, 80 VDC typically. When
the HV current generator is ON, the IDD_ch current (3 mA typical value) is delivered to the
capacitor on the VDD pin. In case of Auto Restart mode after a fault event, the IDD_ch current
is reduced to 0.6 mA, typ. in order to have a slow duty cycle during the restart phase.

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Operation descriptions VIPER17

7.3 Power-up and soft-start up

If the input voltage rises up till the device start level (VDRAIN_START), the VDD voltage begins
to grow due to the IDD_ch current (see Table 6 on page 7) coming from the internal high
voltage start up circuit. If the VDD voltage reaches VDDon threshold (~14 V) the power
MOSFET starts switching and the HV current generator is turned OFF. See Figure 23 on
page 17.
The IC is powered by the energy stored in the capacitor on the VDD Pin, CVDD, until when
the self-supply circuit (typically an auxiliary winding of the transformer and a steering diode)
develops a voltage high enough to sustain the operation.
CVDD capacitor must be sized enough to avoid fast discharge and keep the needed voltage
value higher than VDDoff threshold. In fact, a too low capacitance value could terminate the
switching operation before the controller receives any energy from the auxiliary winding.
The following formula can be used for the VDD capacitor calculation:

Equation 1
I DDch × t SSaux
C VDD = ----------------------------------------
V DDon – V DDoff

The tSSaux is the time needed for the steady state of the auxiliary voltage. This time is
estimated by applicator according to the output stage configurations (transformer, output
capacitances, etc).
During the converter start up time, the drain current limitation is progressively increased to
the maximum value. In this way the stress on the secondary diode is considerably reduced.
It also helps to prevent transformer saturation. The soft-start time lasts 8.5 ms and the
feature is implemented for every attempt of start up converter or after a fault.

Figure 22. Start up IDD current

IDD
VDS = 120V

FSW = 0 kHz

AFTER FAULT
2 mA

1 mA IDD0

IDD_FAULT
IDD_OFF
VDDrestart VDDoff VDDon
IDS_CH_FAULT VDD
-1 mA

-2 mA

IDS_CH
-3 mA

-4 mA

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VIPER17 Operation descriptions

Figure 23. Timing diagram: normal power-up and power-down sequences

Vin

VStart

VVcc
DD regulation is lost here
t
VVcc
DD ON

VVcc
DD OFF

VVcc
DD restart

t
VDRAIN

IDD_CH
Icharge t
3 mA

Normal t
Power -on Power -off
operation

Figure 24. Soft-start: timing diagram

I DRAIN

tss

IDLIM

V FB

V FB OLP

V FB_lin

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Operation descriptions VIPER17

7.4 Power down operation

At converter power down, the system loses regulation as soon as the input voltage is so low
that the peak current limitation is reached. The VDD voltage drops and when it falls below
the VDDoff threshold (8 V typical) the power MOSFET is switched OFF, the energy transfers
to the IC interrupted and consequently the VDD voltages decreases, Figure 23 on page 17.
Later, if the VIN is lower than VDRAIN_START (80 V typical), the start up sequence is inhibited
and the power down completed. This feature is useful to prevent converter’s restart attempts
and ensures monotonic output voltage decay during the system power down.

7.5 Auto restart operation

If after a converter power down, the VIN is higher than VDRAIN_START, the start up sequence
is not inhibited and will be activated only when the VDD voltage drops down the VDDrestart
threshold (4.5 V typical). This means that the HV start up current generator restarts the VDD
capacitor charging only when the VDD voltage drops below VDDrestart. The scenario above
described is for instance a power down because of a fault condition. After a fault condition,
the charging current is 0.6 mA (typ.) instead of the 3 mA (typ.) of a normal start up converter
phase. This feature together with the low VDDrestart threshold (4.5 V) ensures that, after a
fault, the restart attempts of the IC has a very long repetition rate and the converter works
safely with extremely low power throughput. The Figure 25 shows the IC behavioral after a
short circuit event.

Figure 25. Timing diagram: behavior after short circuit

VDD Short circuit occurs here

VDDON

VDDOFF

VDDrest

VDS Trep t
< 0.03Trep

IDD_CH t
t
0.6 mA

FB Pin t
4.8 V
3.3 V

7.6 Oscillator
The switching frequency is internally fixed to 60 kHz or 115 kHz. In both case the switching
frequency is modulated by approximately ±4 kHz (60 kHz version) or ±8 kHz
(115 kHz version) at 250 Hz (typical) rate, so that the resulting spread-spectrum action
distributes the energy of each harmonic of the switching frequency over a number of side-
band harmonics having the same energy on the whole but smaller amplitudes.

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VIPER17 Operation descriptions

7.7 Current mode conversion with adjustable current limit set

point
The device is a current mode converter: the drain current is sensed and converted in voltage
that is applied to the non inverting pin of the PWM comparator. This voltage is compared
with the one on the feedback pin through a voltage divider on cycle by cycle basis.
The VIPER17 has a default current limit value, IDLIM, that the designer can adjust according
the electrical specification, by the RLIM resistor connected to the CONT see Figure 8 on
page 11.
The CONT pin has a minimum current sunk needed to activate the IDLIM adjustment: without
RLIM or with high RLIM (i.e. 100 KΩ) the current limit is fixed to the default value (see IDLIM,
Table 8 on page 8).

7.8 Over Voltage Protection (OVP)

The device can monitor the converter output voltage. This operation is done by CONT pin
during power MOSFET OFF-time, when the voltage generated by the auxiliary winding
tracks converter's output voltage, through turn ratio N AUX
-------------- See Figure 26.
N SEC

In order to perform the output voltage monitor, the CONT pin has to be connected to the aux
winding through a resistor divider made up by RLIM and ROVP
(see Figure 21 and Figure 27). If the voltage applied to the CONT pin exceeds the internal 3
V reference for four consecutive times the controller recognizes an over voltage condition.
This special feature uses an internal counter; that is to reduce sensitivity to noise and
prevent the latch from being erroneously activated. see Figure 26 on page 20. The counter
is reset every time the OVP signal is not triggered in one oscillator cycle.
Referring to the Figure 21, the resistors divider ratio kOVP will be given by:

Equation 2

V OVP
k OVP = --------------------------------------------------------------------------------------------------
-
N AUX
-------------- ⋅ ( V OUTOVP + V DSEC ) – V DAUX
N SEC

Equation 3

R LIM
k OVP = ---------------------------------
-
R LIM + R OVP

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Operation descriptions VIPER17

Where:
● VOVP is the OVP threshold (see Table 8 on page 8)
● VOUT OVP is the converter output voltage value to activate the OVP set by designer
● NAUX is the auxiliary winding turns
● NSEC is the secondary winding turns
● VDSEC is the secondary diode forward voltage
● VDAUX is the Auxiliary diode forward voltage
● ROVP together RLIM make the Output Voltage divider
Than, fixed RLIM, according to the desired IDLIM, the ROVP can be calculating by:

Equation 4

1 – k OVP
R OVP = R LIM × -----------------------
k OVP

The resistor values will be such that the current sourced and sunk by the CONT pin be
within the rated capability of the internal clamp.

Figure 26. OVP timing diagram

VDS

t
VAUX
0

CONT
(pin 4) t
3V

2 µs 0.5 µs
STROBE

t
OVP

t
COUNTER
RESET

COUNTER t
STATUS 0 0 0 0 →1 1 →2 2 →0 0 0 →1 1 →2 2 →3 3 →4

FAULT t

t
NORMAL OPERATION TEMPORARY DISTURBANCE FEEDBACK LOOP FAILURE

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VIPER17 Operation descriptions

7.9 About CONT pin

Referring to the Figure 27, through the CONT PIN, the below features can be implemented:
1. Current Limit set point
2. Over Voltage Protection on the converter output voltage
The Table 9 on page 21 referring to the Figure 27, lists the external resistance combinations
needed to activate one or plus of the CONT pin functions.

Figure 27. CONT pin configuration

SOFT Current Limit

OCP Comparator
Daux Rov p CONT START Curr. Lim.
BLOCK
-

+
To PWM Logic

Auxiliary
winding Rlim OVP DETECTION
LOGIC From SenseFET

To OVP Protection

Table 9. CONT pin configurations

Function / component RLIM (1) ROVP DAUX

IDlim reduction See Figure 8 No No

OVP ≥ 80 KΩ See Equation 4 Yes

IDlim reduction + OVP See Figure 8 See Equation 4 Yes

1. RLIM have to be fixed before RFF and ROVP

7.10 Feed-back and Over Load Protection (OLP)

The VIPER17 is a current mode converter: the feedback pin controls the PWM operation,
controls the burst mode and actives the overload protection of the device. Figure 28 on
page 23 and Figure 29 show the internal current mode structure.
With the feedback pin voltage between VFB_bm and VFB_lin, (respectively 0.5 V and 3.3 V,
typical values) the drain current is sensed and converted in voltage that is applied to the non
inverting pin of the PWM comparator.
This voltage is compared with the one on the feedback pin through a voltage divider on
cycle by cycle basis. When these two voltages are equal, the PWM logic orders the switch
off of the power MOSFET. The drain current is always limited to IDLIM value.
In case of overload the feedback pin increases in reaction to this event and when it goes
higher than VFB_lin the drain current is limited or to the default IDLIM value or the one

21/31
Operation descriptions VIPER17

imposed through a resistor at the CONT pin (using the RLIM, see Figure 8 on page 11); the
PWM comparator is disabled.
At the same time an internal current generator starts to charge the feedback capacitor
(CFB) and when the feedback voltage reaches the VFB_olp threshold, the converter is turned
off and the start up phase is activated with reduced value of Icharge to 0.6 mA.
During the first start up phase of the converter, after the soft-start up time (typical value is
8.5 ms) the output voltage could force the feedback pin voltage to rise up to the VFB_olp
threshold that switches off the converter itself.
To avoid this event, the appropriate feedback network has to be selected according to the
output load. More the network feedback fixes the compensation loop stability. The Figure 28
on page 23 and Figure 29 show the two different feedback networks.
The time from the over load detection (VFB = VFB_lin) to the device shutdown (VFB =
VFB_olp) can be calculating by CFB value (see Figure 28 on page 23 and Figure 29), using
the formula:

Equation 5
V FBolp – V FBlin
T OLP – delay = C FB × ----------------------------------------
3µA

In the Figure 28, the capacitor connected to FB pin (CFB) is used as part of the circuit to
compensate the feedback loop but also as element to delay the OLP shut down owing to the
time needed to charge the capacitor (see equation 5).
After the start up time, 8.5 ms typ value, during which the feedback voltage is fixed at
VFB_lin, the output capacitor could not be at its nominal value and the controller interpreter
this situation as an over load condition. In this case, the OLP delay helps to avoid an
incorrect device shut down during the start up.
Owing to the above considerations, the OLP delay time must be long enough to by-pass the
initial output voltage transient and check the over load condition only when the output
voltage is in steady state. The output transient time depends from the value of the output
capacitor and from the load.
When the value of the CFB capacitor calculated for the loop stability is too low and cannot
ensure enough OLP delay, an alternative compensation network can be used and it is
showed in Figure 29 on page 24.
Using this alternative compensation network, two poles (fPFB, fPFB1) and one zero (fZFB) are
introduced by the capacitors CFB and CFB1 and the resistor RFB1.
The capacitor CFB introduces a pole (fPFB) at higher frequency than fZB and fPFB1. This pole
is usually used to compensate the high frequency zero due to the ESR (Equivalent Series
Resistor) of the output capacitance of the fly-back converter.
The mathematical expressions of these poles and zero frequency, considering the scheme
in Figure 29 are reported by the equations below:

Equation 6

1
fZFB =
2 ⋅ π ⋅ CFB1 ⋅ RFB1

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VIPER17 Operation descriptions

Equation 7

RFB(DYN) + RFB1
fPFB =
(
2 ⋅ π ⋅ CFB ⋅ RFB(DYN) ⋅ RFB1 )

Equation 8

1
fPFB1 =
(
2 ⋅ π ⋅ CFB1 ⋅ RFB1 + RFB(DYN) )
The RFB(DYN) is the dynamic resistance seen by the FB pin and reported on Figure 4 on
page 10.
The CFB1 capacitor fixes the OLP delay and usually CFB1 results much higher than CFB.
The equation 5 can be still used to calculate the OLP delay time but CFB1 has to be
considered instead of CFB. Using the alternative compensation network, the designer can
satisfy, in all case, the loop stability and the enough OLP delay time alike.

Figure 28. FB pin configuration

From sense FET

PWM
To PWM Logic
+
PWM -
CONTROL

Cfb
BURST
BURST-MODE
BURST-MODE LOGIC
REFERENCES

OLP comparator
+ To disable logic

4.8V -

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Operation descriptions VIPER17

Figure 29. FB pin configuration

From sense FET

PWM
To PWM Logic
+
PWM -
CONTROL

Rfb1
Cfb
BURST
BURST-MODE
Cfb1 BURST-MODE LOGIC
REFERENCES

OLP comparator
+ To disable logic

4.8V -

7.11 Burst-mode operation at no load or very light load

When the voltage on feedback pin falls down 50 mV below the burst mode threshold, VFBbm,
power MOSFET is not more allowed to be switched on. It can be switched on again if the
voltage on feedback pin exceeds VFBbm. The voltage on PWM comparator non inverting
internal input, connected to feedback pin through a resistive voltage divider, is lower
clamped to a certain value leading to a minimum value, of 90 mA (typ.) for the drain peak
current.
When the load decrease the feedback loop reacts lowering the feedback pin voltage. As the
voltage goes 50mV below VFBbm MOSFET stops switching. After the MOSFET stops, as a
result of the feedback reaction to the energy delivery stop, the feedback pin voltage
increases and exceeding VFBbm threshold MOSFET the power device start switching again.
Figure 30 shows this behavior called burst mode. Systems alternates period of time where
power MOSFET is switching to period of time where power MOSFET is not switching. The
power delivered to output during switching periods exceeds the load power demands; the
excess of power is balanced from not switching period where no power is processed. The
advantage of burst mode operation is an average switching frequency much lower then the
normal operation working frequency, up to some hundred of hertz, minimizing all frequency
related losses.

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VIPER17 Operation descriptions

Figure 30. Burst mode timing diagram, light load management

FB

50 mV
100
hyster.
VFBBM

t
I DS

Normal -mode Burst-mode Normal -mode t

7.12 Brown-out protection

Brown-out protection is a not-latched shutdown function activated when a condition of mains
under voltage is detected.
The Brown-out comparator is internally referenced to VBRth,0.45 V typ value, and disables
the PWM if the voltage applied at the BR pin is below this internal reference. Under this
condition the power MOSFET is turned off. Until the Brown out condition is present, the VDD
voltage continuously oscillates between the VDDon and the UVLO thresholds, as shown in
the timing diagram of Figure 31 on page 26. A voltage hysteresis is present to improve the
noise immunity.
The switching operation is restarted as the voltage on the pin is above the reference plus the
before said voltage hysteresis. See Figure 31.
The Brown-out comparator is provided also with a current hysteresis, IBRhyst.With this
approach is possible to set the VINon threshold and VINoff thresholds separately, by properly
choosing the resistors of the divider connect to the BR pin.

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Operation descriptions VIPER17

Figure 31. Brown-out protection: BR external setting and timing diagram

HV Input bus
VinON
VinOFF

BR t

Vcc
VDD 0.45V

HV Input bus
t
VinOK
0.1V +
Rh t
-
AC_OK Disable IBR HYS
15 µA
BR -
VinOK VDD t
Vcc
0.45V
+
(pin 3)

Rl 15u
t
VDS

t
Vout

Fixed the VINon and the VINoff levels, with reference to Figure 31, the following relationships
can be established for the calculation of the resistors RH and RL:

Equation 9

VBRHYST VINon − VINoff − VBRHYST VBR

RL = − + ×
IBRHYST VINoff − VBR IBRHYST

Equation 10

VINon − VINoff − VBRHYST RL

RH = ×
IBRHYST V
R L + BRHYST
IBRHYST

For a proper operation of this function, VIN on must be less than the peak voltage at
minimum mains and VIN off less than the minimum voltage on the input bulk capacitor at
minimum mains and maximum load.
The BR pin is a high impedance input connected to high value resistors, thus it is prone to
pick up noise, which might alter the OFF threshold when the converter operates or gives
origin to undesired switch-off of the device during ESD tests.
It is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nF) to prevent
any malfunctioning of this kind.
If the Brown-out function is not used the pin has to be connected to GND.

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VIPER17 Operation descriptions

7.13 2nd level over current protection and hiccup mode

The VIPER17 is protected against short circuit of the secondary rectifier, short circuit on the
secondary winding or a hard-saturation of fly-back transformer. Such as anomalous
condition is invoked when the drain current exceed 0.6 A typical.
To distinguish a real malfunction from a disturbance (e.g. induced during ESD tests) a
“warning state” is entered after the first signal trip. If in the subsequent switching cycle the
signal is not tripped, a temporary disturbance is assumed and the protection logic will be
reset in its idle state; otherwise if the 2nd OCP threshold is exceeded for two consecutive
switching cycles a real malfunction is assumed and the power MOSFET is turned OFF.
The shutdown condition is latched as long as the device is supplied. While it is disabled, no
energy is transferred from the auxiliary winding; hence the voltage on the VDD capacitor
decays till the VDD under voltage threshold (VDDoff), which clears the latch.
The start up HV current generator is still off, until VDD voltage goes below its restart voltage,
VDDrest. After this condition the VDD capacitor is charged again by 600 mA current, and the
converter switching restart if the VDDon occurs. If the fault condition is not removed the
device enters in auto-restart mode. This behavioral, results in a low-frequency intermittent
operation (Hiccup-mode operation), with very low stress on the power circuit. See the timing
diagram of Figure 32.

Figure 32. Hiccup-mode OCP: timing diagram

VDD
Vcc Secondary diode is shorted here
VDDON
VDD OFF

VVcc
DDrest

IDRAIN t
IDmax

V DS t

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Package mechanical data VIPER17

8 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK®

packages. These packages have a lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.

Table 10. DIP-7 mechanical data

mm
Dim.
Typ Min Max

A 5,33
A1 0,38
A2 3,30 2,92 4,95
b 0,46 0,36 0,56
b2 1,52 1,14 1,78
c 0,25 0,20 0,36
D 9,27 9,02 10,16
E 7,87 7,62 8,26
E1 6,35 6,10 7,11
e 2,54
eA 7,62
eB 10,92
L 3,30 2,92 3,81
(6)(8)
M 2,508
N 0,50 0,40 0,60
N1 0,60
O (7)(8) 0,548

1- The leads size is comprehensive of the thickness of the leads finishing material.
2- Dimensions do not include mold protrusion, not to exceed 0,25 mm in total (both side).
3- Package outline exclusive of metal burrs dimensions.
4- Datum plane "H" coincident with the bottom of lead, where lead exits body.
5- Ref. POA MOTHER doc. 0037880
6- Creepage distance >800 V
7- Creepage distance 250 V
8- Creepage distance as shown in the 664-1 CEI / IEC standard.

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VIPER17 Package mechanical data

Figure 33. Package dimensions

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Revision history VIPER17

9 Revision history

Table 11. Document revision history

Date Revision Changes

14-Feb-2008 1 Initial release

19-Feb-2008 2 Updated: Figure 1 on page 1, Figure 3 on page 5

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VIPER17

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