Fets

Chapter 5
Field-Effect Transistors
5.1 INTRODUCTION
The field-effect transistor (FET) is a three-terminal device used for a
variety of applications that match, like the BJT transistor.
The primary difference between the two types of transistors is:
 BJT transistor is a current-controlled device as depicted in Fig.
5.1a,
 JFET transistor is a voltage-controlled device as shown in Fig.
5.1b.
In other words,
the current IC in Fig. 5.1a is a direct function of the level of IB.
For the FET the current I will be a function of the voltage VGS
applied to the input circuit as shown in Fig. 5.1b.
In each case the current of the output circuit is being controlled by
a parameter of the input circuit—in one case a current level and in
the other an applied voltage.
Figure 5.1
(a) Current-controlled
and
(b) voltage-controlled
amplifiers
As there are npn and pnp BJTs, there are n-channel and p-channel FETs.
BJT transistor is a bipolar device;
 bi-revealing that the conduction level is a function of two charge
carriers, electrons and holes.
The FET is a unipolar device;
 depending solely on either electron (n-channel) or hole (p-channel)
conduction.
For the FET an electric field is established by the charges present that
will control the conduction path of the output circuit without the need
for direct contact between the controlling and controlled quantities.
One of the most important characteristics of the FET is its high input
impedance.
In general
FETs are more temperature stable than BJTs
FETs are usually smaller in construction than BJTs,
making them particularly useful in integrated-circuit (IC) chips.
There are two types of FETs
the junction field-effect transistor (JFET) and
the metal-oxide-semiconductor field-effect transistor (MOSFET)
The MOSFET category is further broken down into depletion and
enhancement types.
The MOSFET transistor has become one of the most important
devices used in the design and construction of integrated circuits for
digital computers.
5.2 CONSTRUCTION AND CHARACTERISTICS OF JFETs
JFET is a three-terminal device with one terminal capable of
controlling the current between the other two.
The basic construction of the n-channel JFET is shown in Fig. 5.2.
Note that the major part of the structure is the n-type material that
forms the channel between the embedded layers of p-type material.
The top of the n-type channel is connected through an ohmic contact to
a terminal referred to as the drain (D), while the lower end of the same
material is connected through an ohmic contact to a terminal referred to
as the source (S).
The two p-type materials are connected together and to the gate (G)
terminal.
In essence, therefore, the drain and source are connected to the ends of
the n-type channel and the gate to the two layers of p-type material.
Figure 5.2 Figure 5.3

Junction field-effect Water analogy for
transistor (JFET). the JFET control
mechanism.
The source of water pressure can be likened to the applied voltage from
drain to source that will establish a flow of water (electrons) from the
spigot (source).
The “gate,” through an applied signal (potential), controls the flow of
water (charge) to the “drain.”
Case 1; 𝑉𝐺𝑆 = 0 𝑉, 𝑉𝐷𝑆 = 𝑉𝐷𝐷
In Fig. 5.4, a positive voltage VDS has been applied across the channel
and the gate has been connected directly to the source to establish the
condition 𝑉𝐺𝑆 = 0 𝑉. The result is a gate and source terminal at the
same potential and a depletion region in the low end of each p-material
similar to the distribution of the no-bias conditions of Fig. 5.2.
The instant the voltage 𝑉𝐷𝐷(= 𝑉𝐷𝑆) is applied, the electrons will be
drawn to the drain terminal, establishing the conventional current ID
with the defined direction of Fig. 5.4.
The path of charge flow clearly reveals that the drain and source
currents are equivalent (𝐼𝐷 = 𝐼𝑆).
Under the conditions appearing in Fig. 5.4, the flow of charge is
relatively uninhibited and limited solely by the resistance of the n-
channel between drain and source.
At the drain terminal, voltage VDS is some positive voltage greater than
zero.
But the source terminal is at ground 0V.
It clearly means that voltage drops several times across the length of the
n-channel from drain to source.
Figure 5.4 JFET in the
𝑉𝐺𝑆 = 0 𝑉 and 𝑉𝐷𝑆 > 0 𝑉.
It is important to note that the depletion

region is wider near the top of both p-
type materials.
The positive potential of VDS attracts electrons from the channel

towards the source.
The conventional current ID flows from the drain to the source.
Since the n-channel provides resistance to the flow of electrons, it can
be considered a network of resistances.
An equivalent resistive series network of four voltages explains voltage
drops across the length of the JFET n-channel.
Suppose VDS = 4V and a series network of four resistors across the
length of the channel. The value of each resistor is 1 ohm.
According to ohm’s law V = IR,
The voltage drop across each point is 3V, 2V, 1V, and eventually 0V at
the source ground.
The resistive network explains that the width of the depletion region
increases towards the drain terminal.
The depletion region towards the source terminal is narrower than the
above layers.
The gate-to-source terminal is at a lower potential compared to the
drain-to-source bias.
It implies that the PN junction at the gate terminal is reversed biased.
Pinch off voltage
VGS = 0, VDS = VP
As VDS increases, the depletion region starts to get bigger near the drain
terminal.
When drain-to-source voltage VDS reaches the pinch-off voltage VP, it
appears that both the depletion layers would adjoin.
However, the depletion regions never touch due to electrostatic
repulsion and allow current flow.
The current ID increases with increasing VDS until the pinch-off point.
The current ID reaches saturation to become constant and does not
increase with increasing VDS.
The drain current at the pinch-off point is termed IDSS. The JFET acts as a
constant current source beyond pinch-off voltage VP.
Case 2: VGS < 0, VDS > 0 and

VDS < Vdrain
When VGS is made more negative
and VDS is positive but lesser than the
previous case VDrain,
The saturation level can be achieved
with the much lesser value
of VDS because PN junctions become
more reverse biased. The value of
pinch-off voltage VP exponentially
drops.
JFET Symbol
JFET Biasing
Just as with the BJT, the purpose of biasing is to select the proper dc
gate to source voltage(VGS) to establish a desired value of drain
current(ID) and, thus, a proper Q-point.
Self Bias
Example Problems
1. Determine
The MOSFET
MOSFET Characteristics and Parameters
MOSFET Biasing

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Chapter 5

Figure 5.2 Figure 5.3

It is important to note that the depletion

The positive potential of VDS attracts electrons from the channel

Case 2: VGS < 0, VDS > 0 and

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