Summer 2019
Summer 2019
Summer 2019
com
Seat No.: ________ Enrolment No.___________
(c) Draw logic circuit of Full Adder and Full Subtractor with truth table. 07
OR
(c) Generate AND, OR, NOT, EXOR and EX-NOR gate using NAND as a 07
universal gate.
Q.3 (a) Obtain canonical Sum of Product form of following function: F=AB+ACD. 03
(b) Draw logic circuit of 2x4 Decoder. 04
(c) Simply Boolean function for F(W,X,Y,Z) = 𝛴 ( 0, 1, 2, 4 ,5 ,6 ,8, 9, 12, 13, 07
14)
OR
Q.3 (a) Explain working of Half Adder circuit with diagram. 03
(b) Draw logic circuit for 2-Bit Magnitude Comparator. 04
(c) Design 1-Bit Full Adder using 3x8 Decoder. 07
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Q.4 (a) How to generate 8x1 MUX using 4x1 MUX. 03
(b) Draw the circuit diagrams and Truth table of all the Flip flops (SR, D). 04
(c) Derive and draw logic circuit for BCD to Excess-3 Code converter. 07
OR
Q.4 (a) Draw logic diagram, graphical symbol and Characteristic table for clocked T 03
flip-flop.
(b) Explain 4-Bit serial in serial out shift register. 04
(c) Explain working of master-slave JK flip-flop with necessary logic diagram, 07
state equation and state diagram.
Q.5 (a) Give comparison of TTL and CMOS family. 03
(b) Draw and explain Ring counter. 04
(c) Design synchronous counter for sequence: 0134570 using T 07
flip-flop.
OR
Q.5 (a) What is race around condition in JK flip flop? 03
(b) Write short note on Programmable Logic Arrays. 04
(c) Explain the Fundamental Mode Model of Asynchronous State Machine with 07
suitable example.
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