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    Gujarat Technological University

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    Daily Game

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    © All Rights Reserved
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    Gujarat Technological University

    Uploaded by

    Daily Game
    9 views2 pages

    Original Title

    S23 3130907

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    9 views2 pages

    Gujarat Technological University

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    Daily Game

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    of 2

    Seat No.: ________ Enrolment No.

    ___________

    GUJARAT TECHNOLOGICAL UNIVERSITY


    BE - SEMESTER–III(NEW) EXAMINATION – SUMMER 2023
    Subject Code:3130907 Date:28-07-2023
    Subject Name:Analog & Digital Electronics
    Time:02:30 PM TO 05:00 PM Total Marks:70
    Instructions:
    1. Attempt all questions.
    2. Make suitable assumptions wherever necessary.
    3. Figures to the right indicate full marks.
    4. Simple and non-programmable scientific calculators are allowed.

    MARKS
    Q.1 (a) Define Slew Rate, CMRR, & Input Offset Voltage. 03
    (b) What is cross over distortion in power amplifier? 04
    (c) Sketch the block schematic of a typical operational amplifier and 07
    briefly explain the function of each block.

    Q.2 (a) List applications of instrumentation amplifier. 03


    (b) Design an R-C phase shift oscillator to produce a sinusoidal 04
    output at 1KHz, using capacitor value 0.1 μF.
    (c) Draw integrator circuit with example of input and output 07
    Waveforms. Derive expression for output voltage.
    OR
    (c) Draw & explain in detail the logic diagram & the truth table of 07
    clocked SR flip-flop.

    Q.3 (a) For an inverting amplifier, V1 = 1V, V2 = 3V, V3 = 2V with R1 03


    = R2 = R3 = 2KΩ and RF = 3KΩ. Determine the output voltage.
    (b) Implement the following function using 8:1 Multiplexer. 04
    F(A,B,C,D) =A̅BD̅ +ACD +B̅CD+A̅C̅D
    (c) Explain the circuit diagram of op-amp as a Peak detector. 07
    OR
    Q.3 (a) Simplify A̅BCD̅ +BCD̅ +BC̅D̅ +BC̅D. 03
    (b) Classify digital logic gates. Draw truth table and symbols of basic 04
    logic gates.
    (c) Prove that NAND and NOR gates are universal gates. 07

    Q.4 (a) Design D FF using SR FF. Write truth table of D FF. 03


    (b) Explain Master-Slave J-K flip-flop configuration. 04
    (c) Simplify the Boolean function F(A,B,C,D) = Σm 07
    (1,5,6,12,13,14), Σd=(2,4) using K-map method. Implement
    using basic logic gates.
    OR
    Q.4 (a) Design half subtractor logic circuit. 03
    (b) Write short note on Gray code. 04
    (c) Explain Half Adder circuit .Explain Full adder circuit with the 07
    help of two Half adder.

    Q.5 (a) Compare RC phase shift and Wien bridge oscillator. 03


    (b) Explain R-2R ladder DAC with necessary diagram. 04
    (c) Explain the working of Zero crossing Detector. 07
    1
    OR
    Q.5 (a) Define following 03
    a) Attenuation b) Pass Band c) Cut of frequency
    (b) Draw Schmitt trigger circuit. Plot input and output waveforms. 04
    (c) List out various commonly used A/D converters. Draw & explain 07
    Flash A/D converter with necessary decoding table. Also mention
    pros & cons of the same.

    *************

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