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IET Power Electronics

Special Issue: Flexible Operation and Control for Medium Voltage

Direct-Current (MVDC) Grid

General topology for asymmetrical multilevel ISSN 1755-4535

Received on 17th December 2016
Revised 12th June 2017
inverter with reduced number of switches Accepted on 8th July 2017
E-First on 31st August 2017
doi: 10.1049/iet-pel.2016.1011
www.ietdl.org

Kamaldeep Boora1 , Jagdish Kumar1

1Department of Electrical Engineering, PEC University of Technology, Chandigarh, India
E-mail: kdsboora@gmail.com

Abstract: The new emerging topologies in multilevel inverter field with reduced dc voltage sources and device counts, offer high
power capability with less commutation losses and less harmonics in output voltage. However, these topologies have some
disadvantages such as voltage balancing problem, increased number of electronic components, larger in size and complex
control techniques. This study proposes a new asymmetrical multilevel inverter topology which requires less number of
switching devices and driver circuits as compared to conventional multilevel inverter topologies. In the proposed topology, eight
switches are required for generation of 15-level single phase output voltage. The proposed topology is simple and can be
extended easily to get more number of levels in the output voltage. Therefore, there is a significant reduction in size, cost and
complexity for higher number of levels in output voltage. All positive and negative levels as well as performance parameter in
term of Total Harmonic Distortion in the output voltage generated by proposed MLI have been evaluated using simulation in
MATLAB environment. Various simulation and experimental results are presented to verify the operational accuracy of the
proposed topology for a single phase 15-level inverter.

1 Introduction number of power electronic switches to generate a particular level

in output voltage. Generally, these inverters are divided into two
In the modern set up of generation, transmission, distribution and groups: symmetric and asymmetric multilevel inverters. In
electric power utilisation, dc-to-ac power conversion is a very symmetric multilevel inverter topologies, the values of dc voltage
important technology. For the past decade, multilevel inverters are sources in H-bridges are equal, whereas in asymmetric multilevel
key technology and play crucial role in variable frequency drives, inverter, values of dc voltage sources are unequal. An asymmetric
wind power, marine propulsion, active filters, traction, renewable multilevel inverter can generate more level in output voltage with
energy sources and uninterruptible power supply with high-voltage less number of power electronic switches. There are two methods
capabilities, improved electromagnetic compatibility and output for determining the magnitude of dc voltage sources in CHB
voltage quality etc. [1–6]. Extensive use of multilevel inverters asymmetrical multilevel inverter, binary and trinary configurations.
(MLIs) in the industry makes it to be considered as a mature Trinary configuration can generate more level when compared with
technology. Conventional converters can produce two levels, +Vdc binary configuration. Simple control techniques, less number of
and −Vdc, in the output voltage. The two-level output voltage semiconductor switches, dc voltage sources and drivers circuit are
contain large number of harmonic components and makes use of the main factors in deciding the cost and size of the MLI.
filter inevitable to obtain a sinusoidal waveform. However, this In recent years, many topologies for symmetric and asymmetric
two-level inverter has some limitations when operated at high- configurations were presented with reduced number of switches. In
voltage/power application due to switching losses and need of high [5, 6, 11, 16–22], different topologies with symmetric
rating devices. In multilevel inverter, high-voltage can be obtained configuration have been presented. In [17], two different
with the help of low-voltage-rated power device [7–9]. Multilevel algorithms are presented for symmetric and asymmetric multilevel
inverter posses many advantages when compared with two-level inverter topology. However, a high number of insulated gate
inverter such as stress is shared proportionally among power bipolar transistor (IGBT) are used as this topology uses
electronic switches, less electromagnetic interference and reduction bidirectional switches which are the main drawback of this
in output voltage total harmonic distortion (THD) with increased structure. In [19], a symmetrical topology is presented where single
number of output voltage levels [5, 6, 10–13]. dc source is used with two switches as a basic unit. By connecting
The multilevel inverters synthesise a stepped output voltage this basic unit in cascading manner, level in output voltage can be
waveform by operating the power electronic switches in a increased. In [21], a basic unit for symmetrical topology is
predetermined sequence using several low dc voltage sources. presented which requires three dc voltage sources and five switches
These kinds of inverters are mainly categorised in neutral point- to generate three positive levels in output voltage. To obtain more
clamped inverter (NPC), flying capacitor multilevel inverter level in output voltage, basic unit is connected in cascading manner
(FCMLI) and cascaded H-bridge (CHB) multilevel inverter [14– and a full H-bridge is connected at output of this cascading
16]. In NPC multilevel inverter, the main drawback is unequal structure to generate negative level in output voltage. However, the
voltage sharing among the series connected capacitors and a high main drawback of symmetric topology is the high number of dc
number of clamping diodes are required as the number of levels in voltage sources, power switches, power diodes, insulated-gate
output voltage increased. In FCMLI topology, flying capacitors are bipolar transistors and driver circuits. These drawbacks increased
used as the clamping devices. It has some advantage over NPC in the topologies where bidirectional switches are used from
topology as redundant phase leg state that distributes the switching voltage point of view [17, 18]. A unidirectional switch consists of
stress equally among the semiconductor devices. However, a large an IGBT with an antiparallel diode, whereas a bidirectional power
number of storage capacitors are required as the step in output switch requires two IGBTs and two antiparallel diodes when
voltage increased. In CHB multilevel inverter, clamping diodes and common emitter configuration is used. A unidirectional switch can
flying capacitors are not used. This inverter uses simple control conduct current in both direction and can block voltage in one
technique, highly reliable, modularity in structure and requires less direction while a bidirectional switch can conduct current and

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S5, S6 should not be turned ‘ON’ simultaneously as it will lead to a
short circuit to voltage sources. Similarly, simultaneous turn ‘ON’
of S3 and S4 should be avoided.
Different switching operations to get the multilevel output
waveform for the structure shown in Fig. 1 are given in Table 1. In
Table 1, 1 and 0, respectively, imply the ‘ON’ and ‘OFF’ state of
the switches. It can be observed from Table 1 that number of levels
in output voltage will be more if the magnitudes of both voltage
sources are different from each other as in case of equal magnitude,
level in output voltage will be less. To achieve all possible voltage
levels (positive and negative) the values of dc voltage sources V 1
and V 2 should be in the ratio 1:2.
Fig. 1 Basic unit for proposed MLI To generate more levels in output voltage, more switches and dc
voltage sources are connected with basic unit. A 15-level MLI
Table 1 Output voltage levels for proposed seven-level topology is shown in Fig. 2 by connecting two switches and one
inverter more dc voltage source with basic unit. So using three voltage
State S1 S2 S3 S4 S5 S6 vo sources and eight power switches, 15-level in output can be
1 1 0 0 1 1 0 V1 + V2 generated. It can be seen from Fig. 2, switch combinations (S1, S2),
(S3, S4), (S5, S6) and (S7, S8) should not be turned ‘ON’
2 1 0 0 1 0 1 V2
simultaneously as it will lead to a short circuit of voltage sources.
3 0 1 0 1 1 0 V1 Different switching operations for 15-level inverter are shown in
4 0 1 0 1 0 1 0 Table 2. The magnitude of dc voltage sources V 1: V 2: V 3 should be
5 1 0 1 0 0 1 −V 1 in the ratio of 1:2:5 to generate all positive and negative levels in
6 0 1 1 0 1 0 −V 2 output voltage.
A 31-level inverter can be proposed by developing the 15-level
7 0 1 1 0 0 1 − V1 + V2
inverter as shown in Fig. 3a. It consists of four dc voltage sources
and ten power electronic switches. In the same manner, by
connecting more switches and dc voltage sources, more levels in
output voltage can be generated. So, a general topology can be
proposed as shown in Fig. 3b. General topology consists of 2n
unidirectional power switches and n number of dc voltage sources.
In general, for the topology presented in this article, the number
of dc voltage sources (Nsource), number of switches (Nswitch),
maximum output voltage (Vo,max) and number of output voltage
levels (Nstep) can be determined using relations

Nsource = n (1)

Nswitch = 2n + 2 (2)
Fig. 2 Proposed 15-level MLI
V o, max = V n + V n − 1 (3)
block voltage in both directions. To obtain high number of levels in
output voltage, different asymmetric topologies have been Nstep = 2n + 1 − 1 (4)
presented in [12, 17, 18, 23–28]. In [28], an asymmetrical topology
is presented where various dc sources are connected with where n is the number of dc voltage sources used in proposed
bidirectional switches and this basic unit can be connected in topology.
cascading manner to increase the number of level in output voltage.
However, this basic unit can generate only positive level and a full
3 Standing voltage and DC voltage sources
H-bridge is required at output of each basic unit to generate
negative voltage level which in turn increases the number of magnitude
switches in the inverter. However, the number of power electronic 3.1 Standing voltage
switches and dc voltage sources are high which in result increase
the cost and size of the inverter. Standing voltage of various switches is one of the most important
Here a new multilevel inverter topology is proposed using basic parameter for operating the MLI smoothly and also the deciding
unit which uses less number of power electronic switches and dc factor for cost of the MLI. The cost of MLI increases as the
voltage sources [13]. Then, by connecting various switches and dc standing voltage on switches increases. The magnitude of
voltage sources with basic unit to minimise the number of power maximum value of the voltage that a switch has to block in OFF
switches, driver circuits and to increase the level in output voltage state is considered as standing voltage on the switch.
waveform, a new topology is proposed as a generalised multilevel From Fig. 1, when switch S1 is in conduction state, switch S2
inverter. The proposed MLI topology is compared with several has to block voltage V 2 and when switch S2 is in conducting state,
existing MLI topologies to investigate its superiority. Finally, the switch S1 has to block voltage V 2. Similarly when switch S5 is in
performance of the proposed topology in generating all voltage conduction state, switch S6 has to block voltage V 1 and when
levels is confirmed by experimental result using 15-level proposed switch S6 is in conducting state, switch S5 has to block voltage V 1.
inverter. Therefore, standing voltage of individual switch in proposed seven-
level inverter can be calculated as
2 Proposed basic unit
In this paper, a new topology based on asymmetrical MLI is V S1 = V S2 = V 2 (5)
proposed. Basic unit for proposed MLI is shown in Fig. 1 [13]. It
consists of two voltage sources (V 1 and V 2) with different V S5 = V S6 = V 1 (6)
magnitude and six unidirectional switches (S1, S2, S3, S4, S5 and
S6). From Fig. 1, it is clear that the switch combinations S1, S2 and V S3 = V S4 = V 1 + V 2 (7)

IET Power Electron., 2017, Vol. 10 Iss. 15, pp. 2034-2041 2035
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Table 2 Output voltage of proposed 15-level inverter
State S1 S2 S3 S4 S5 S6 S7 S8 vo
1 1 0 0 1 1 0 1 0 V3 + V2
2 1 0 0 1 0 1 1 0 V3 + V2 − V1
3 0 1 0 1 1 0 1 0 V3
4 0 1 0 1 0 1 1 0 V3 − V1
5 1 0 0 1 1 0 0 1 V1 + V2
6 1 0 0 1 0 1 0 1 V2
7 0 1 0 1 1 0 0 1 V1
8 0 1 0 1 0 1 0 1 0
1 0 1 0 1 0 1 0
9 1 0 1 0 0 1 1 0 −V 1
10 0 1 1 0 1 0 1 0 −V 2
11 0 1 1 0 0 1 1 0 − V1 + V2
12 1 0 1 0 1 0 0 1 − V3 − V1
13 1 0 1 0 0 1 0 1 − V3
14 0 1 1 0 1 0 0 1 − V3 + V2 − V1
15 0 1 1 0 0 1 0 1 − V3 + V2

Fig. 3 Proposed topology

(a) Configuration for 31-level inverter, (b) General structure for proposed topology

Therefore, maximum standing voltage of all switches in structure 3.2 Magnitude of dc voltage sources
as shown in Fig. 1 can be determined as follows:
3.2.1 Proposed seven-level inverter: DC voltage sources
V standing, 2 = V S1 + V S2 + V S3 + V S4 + V S5 + V S6 magnitude for seven-level inverter as shown in Fig. 1 can be
(8) calculated as
= 4(V 1 + V 2)
V 1 = V dc (15)
Similarly, standing voltage of individual switch in proposed 15-
level inverter as shown in Fig. 2 can be calculated as V 2 = 2V dc (16)
V S1 = V S2 = V 2 (9) Using (15), (16) and Table 1, all the levels with values 0, ±V dc,
±2V dc and ±3V dc can be obtained.
V S3 = V S4 = V 2 + V 3 (10)

V S5 = V S6 = V 1 (11) 3.2.2 Proposed 15-level inverter: DC voltage sources magnitude

for 15-level inverter as shown in Fig. 2 can be calculated as
V S7 = V S8 = V 3 − V 1 (12)
V 1 = V dc (17)
Therefore, maximum standing voltage of all switches used in
structure as shown in Fig. 2 can be determined as follows: V 2 = 2V dc (18)

V standing, 3 = V S1 + V S2 + V S3 + V S4 + V S5 + V S6 + V S7 + V S8 V 3 = 5V dc (19)
(13)
= 4(V 2 + V 3)
Considering (17), (18) and (19) and Table 2, all the positive and
negative levels from 0 to 7V dc with voltage step V dc can be
Finally, maximum standing voltage of all the switches in general
topology, as shown in Fig. 3b, can be determined as follows: generated in output voltage.

V standing, n = 4(V n − 1 + V n) (14) 3.2.3 Proposed general multilevel inverter: Magnitude of dc

voltage sources for general topology can be determined as follows:

2036 IET Power Electron., 2017, Vol. 10 Iss. 15, pp. 2034-2041
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Fig. 4 Variation of NIGBT versus Nlevel Fig. 7 Variation of VTSV versus Nlevel

topology has been presented and indicated by T8. A symmetrical

topology using bidirectional switches has been presented in [17]
and indicated by T9. Another asymmetrical topology that has been
presented in [25] is indicated by T10. Asymmetrical topologies
using bidirectional switches have been presented in [26–28] are
indicated by T11–T13, respectively. Symmetrical topologies
presented in [21, 22] are considered by T14 and T15, respectively,
in this comparison.
Fig. 4 compares the number of IGBTs in the proposed
multilevel inverter topology and the conventional multilevel
inverter topologies. As it is obvious from Fig. 4, number of IGBTs
in proposed topology is less than other conventional topologies. As
the unidirectional switches are used in the proposed topology,
number of switches and power diodes is same as the number of
Fig. 5 Variation of Ndriver versus Nlevel IGBTs. This comparison shows that the required number of power
electronics switches for a particular level in the proposed topology
is lower than topologies with unidirectional as well as topologies
with bidirectional switches.
Fig. 5 indicates the comparison of number of driver circuits in
proposed topology with the other aforementioned topologies. As
each switch needs separate driver circuit, number of power
electronic switches is equal to the number of driver circuits.
Therefore this comparison also shows the required number of
power electronic switches in the proposed topology. As shown in
Fig. 5, proposed topology requires less number of driver circuits as
compared to other topologies.
Fig. 6 compares the required number of dc voltage sources in
proposed topology with other aforementioned topologies and
comes out to be very less. As a result, proposed topology has a
better feature from this point of view.
Fig. 7 compares the total standing voltage (TSV) of the
switches in the proposed multilevel inverter topology and the
Fig. 6 Variation of Nsource versus Nlevel
conventional multilevel inverter topologies. As it is obvious from
n+1
Fig. 7, TSV in the proposed topology is less than the other
−1
5 2 V dc, for odd n, n = 1, 3, 5… topologies. This parameter for topologies presented in [16, 18, 19,
Vn = n
(20) 23, 24] is less than the proposed topology. However, topologies
−1
2×5 2 V dc, for even n, n = 2, 4, 6… presented in [16, 18, 19, 23, 24] need more number of components
in comparison with the proposed topology. As the maximum
4 Comparison with conventional topologies voltage rating of individual switch is high and equal to the sum of
(V n − 1 + V n), this topology is suitable for medium-voltage
The main objective of proposing the new topology is to achieve applications such as D-STATCOM, hybrid electrical vehicle,
higher number of levels in output voltage by using less count of electrical machine and photovoltaic cell.
various components. Therefore, to investigate the performance of The cost of multilevel inverter depends upon the number of
the proposed multilevel inverter, several comparisons have been IGBTs (NIGBT), drivers (Ndriver), dc sources (Nsource), variety of the
done with conventional topologies in terms of number of dc
values of dc voltage sources (Nvariety), and standing voltage rating
voltage sources, IGBTs and driver circuits. In this comparison,
proposed topology as shown in Fig. 2 is represented by P. In [16], of the switches (V TSV). It can be formulate as [26]
conventional CHB inverter has been presented and denoted by T1
in this investigation. Two new algorithms for H-bridge multilevel CML = NIGBT + Ndriver + Nsource + Nvariety + αV TSV (21)
inverter have been presented in [23, 24] and denoted by T2 and T 3,
respectively. The other presented symmetrical topology in [19] is where α is the weight coefficient of TSV on switches against
indicated by T4. In [18], a cascaded multilevel inverter has been number of power switches. If the importance of TSV is higher,
then the value of α should be selected higher and vice versa. As
presented with two different algorithms, indicated by T5 and T6,
indicated in Figs. 4–7, the value of parameters NIGBT, Ndriver,
respectively. Another asymmetrical topology presented in [29], is
Nsource and V TSV are less in the proposed topology, it means that the
denoted by T7 in this comparison. In [20], an asymmetrical
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cost of switches is less in proposed topology than other topologies. V IGBT is the voltage across switch before turn-on or after turn-off
Variety of the magnitude of dc voltage sources play important role of the switch.
in deciding the cost of the multilevel inverter. Higher value of this If there are Non, number of turn-on and Noff , number of turn-off
parameter increases the cost if the number of dc voltage sources are of the switches during a fundamental cycle T, the switching power
equal in different topologies (considering equal Nlevel) and loss can be obtained as follows:
decreases the cost if the number of dc voltage sources is reduced
(considering equal Nlevel) as it will require less number of rectifiers 1
Psw = NonEon + Noff Eoff (26)
and transformers. This parameter for the proposed topology and T
topology presented in [18] is equal to the number of dc sources
(Nsource = Nvariety). As the number of dc voltage sources required in Therefore total loss (Ploss) of the multilevel inverter can be written
the proposed topology is less when compared with other topologies as:
as shown in Fig. 6, for equal number of level, this factor also lead
to lower cost of the proposed topology. Ploss = Pcond, IGBT + Pcond, D + Psw (27)
It is clear from the aforementioned different comparisons that
the proposed topology requires less number of IGBTs, power Finally the efficiency (η) of the inverter is calculated as follows:
electronic switches, driver circuits and dc voltage sources. Due to
these features, proposed topology needs less installation space and Pout Pout
reduction in cost of the inverter which are the remarkable η= = (28)
Pin Pout + Ploss
advantage of the proposed topology. As a result, proposed
multilevel inverter topology can be used to replace conventional where Pout and Pin denote the output and input power of the
inverter in many applications such as electric vehicle drive, HVDC
transmission system, control of electric machine. multilevel inverter.

5 Calculation of losses 6 Simulation and experimental results

Mainly, two kinds of losses, conduction and switching losses, are In this section, the ability of proposed multilevel inverter to
associated with switches in the presented topology. Conduction generate all positive and negative level in output voltage is verified
losses (Pcond) are the losses that occur due to flow of current in using simulation and experimental results. Simulation results are
obtained in MATLAB environment. In the simulation and
switches during on-state. Load current in a switch flows through experimental studies, RL load is used with value R = 50 Ω and L =
the IGBT and antiparallel diode in multilevel inverter. Therefore, 35 mH. Staircase or fundamental frequency control method is used
Pcond can be given as the sum of conduction losses in IGBT to operate the various switches in proposed multilevel inverter
(Pcond, IGBT) and anti-parallel diode (Pcond, D). Generally, Pcond, IGBT [30]. In staircase control method, transition of voltage from one
and Pcond, D are obtained as follows [22]: level to another level happens once in a fundamental cycle.
Frequency of output voltage is 50 Hz.
1 2π
Pcond, IGBT = nIGBT t . ∫ V I + RON, IGBT I β + 1d wt
2π 0 ON, IGBT 6.1 Simulation results
(22)
For simulation, values of dc voltage sources used V 1, V 2 and V 3 are
30, 60 and 150 V, respectively, using (20) and assuming
1 2π V dc = 30 V. So, peak amplitude of output phase voltage is 210 V.
Pcond, D = nD t . ∫ V I + RON, D I 2d wt (23)
2π 0 ON, D Output waveform of phase voltage for proposed 15-level inverter is
shown in Fig. 8a and it is confirmed that proposed inverter can
where nIGBT t and nD t are the number of on-state IGBTs and generate all positive and negative levels. Output phase current
antiparallel diodes in current path. V ON, IGBT and V ON, D are the on- waveform is shown in Fig. 8b and it is nearly ideal sinusoidal due
state voltage drop of the IGBT and antiparallel diode, respectively. to RL load which acts as a low-pass filter for load current. After
RON, IGBT and RON, D are the on-state resistance of the IGBT and comparing Figs. 8a and b, it is clear that there is some phase
antiparallel diode, respectively. β is a constant related to the displacement between voltage and current. This delay is due to the
specification of the IGBT. At high number of levels in output inductive nature of the load.
voltage, the output current can be assumed to be sinusoidal. THD analysis for output-phase voltage and phase current is
Switching losses consist of turn-on and turn-off switching shown in Figs. 9a and b, respectively. THD in output voltage is
losses. By considering approximation that during switching, 4.54% and in load current is 0.68% which is very less. Current
voltage and current vary linearly, energy loss during turn-on and THD is so much low due to the inductance in load which blocks
turn-off period of a switch can be given as the higher order harmonics.

ton 6.2 Experimental results

Eon = ∫ V t I t d(t)
0 A prototype setup is demonstrated in Fig. 10, to verify the
(24)
ton
V IGBT simulation results. In the experimental studies, FGW40N120HD
I 1
=∫ t − t − ton d t = V IGBTIton IGBT with a 1200 V/40 A capacity is used as switching device
0 ton ton 6
with driver circuit. Dspace1104 is used to operate the various
switches by interfacing with SIMULINK using real-time
toff
interfacing card. The frequency and magnitude of output
Eoff = ∫ V t I t d t
0 fundamental voltage of inverter can be controlled in real time by
toff
(25) changing reference voltage in the Simulink/Matlab environment.
V IGBT I 1 To avoid the simultaneously turn-on of switches (S1, S2), (S3, S4),
=∫ t − t − toff d t = V IGBTItoff
0 toff toff 6 (S5, S6) and (S7, S8), a delay circuit is used with delay time of 5 μs.
Dspace1104 and prototype is also isolated using MCT2E
where Eon and Eoff are the energy loss during turn-on and turn-off optocoupler. Digital storage oscilloscope, TPS2024B by
period of switch, ton and toff are the turn-on cross-over interval and TEKTRONIX is used in the laboratory for measurement of output
turn-off cross-over interval time of the switch, I is the current voltage and current waveforms. Values of dc voltage sources used
through the switch before turn-off or after turn-on of the switch, V 1, V 2 and V 3 are 13, 26 and 65 V, respectively.

2038 IET Power Electron., 2017, Vol. 10 Iss. 15, pp. 2034-2041
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Fig. 8 Simulation result
(a) 15-level output voltage waveform, (b) 15-level output current waveform

Fig. 9 Harmonic components

(a) Output voltage spectrum, (b) Output current spectrum

Fig. 10 Experimental setup

Fig. 11 shows the stepwise generated output phase voltage and Fig. 11 Output phase voltage and current for proposed 15-level inverter
current waveforms for 15-level proposed inverter. All positive and
negative levels with peak amplitude 91 V are generated in the the output voltage and current waveform obtained using Fluke
output-phase voltage. Due to the presence of RL load at output meter. Figs. 13b and c show the THD in output voltage and current
which acts as a low-pass filter, current waveform is more waveform. As shown in Figs. 13b and c, output voltage has 5.4%
sinusoidal than voltage waveform. The figure shows a good THD, whereas output current has 2% THD, respectively. As the
resemblance with the simulation results. simulation (Figs. 9a and b) and experimental THD results are in
As aforementioned, proposed topology requires unidirectional close agreement and hence validating the proposed topology. A
power electronic switches from the voltage point of view: therefore little difference between the simulated and experimental results is
to verify this fact, voltage across switches S1, S3, S7 and S5 are due to delay time of 5 μs and different platform used for these
shown in Figs. 12a–d. It is observed from the figure that the studies. In the test condition, the measured input and output powers
magnitude of blocked voltage is either positive or zero and there is are about 62.65 and 58.27 W, respectively. Therefore, the
no negative voltage. This fact confirms that proposed topology efficiency of the inverter is about 93%. Power loss based on the
requires unidirectional switches. In addition magnitude of blocked loss calculation given earlier, is about 4.05 W. Therefore, the
voltage by switches S1, S3, S7 and S5 are 26, 91, 52 and 13 V, calculated loss has a good resemblance with measured efficiency.
respectively. Considering the amount of blocked voltages by
switches, equations for maximum blocked voltage by switches are
well confirmed.
7 Conclusion
A Fluke 43 B power quality analyser is used to measure the In this paper, a new multilevel inverter topology is proposed.
THD in experimental output voltage and current. Fig. 13a shows Various structures are presented for obtaining different level in

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Fig. 12 Experimental voltage across switches
(a) S1, (b) S3, (c) S7, (d) S5

Fig. 13 THD results for 15-level output voltage and output current
(a) 15-level output voltage and current waveform, (b) Voltage THD, (c) Current THD

output voltage by connecting more switches and dc voltage sources proposed topology with other topology presented in literature,
with basic structure. Comparisons for proposed topology and confirmed that proposed topology is superior in many aspects.
conventional topologies have been presented by considering
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2040 IET Power Electron., 2017, Vol. 10 Iss. 15, pp. 2034-2041
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