Unit III– Computer Arithmetic

and Memory
Addition and Subtraction with signed magnitude data, Hardware
implementation, Hardware Algorithm, Addition and Subtraction with
signed 2’ s Complement Data, Multiplication Algorithms: Hardware
implementation for signed Magnitude Data, Hardware Algorithm,
Booth Multiplication Algorithm, Array Multiplier, Division
Algorithms: Hardware implementation for signed Magnitude Data,
Divide Overflow, Floating Point Arithmetic: Basic Considerations,
Register Configuration, Addition, Subtraction, multiplication and
Division. The Memory System: Basic Concepts, Semiconductor RAM
Memories, ROM, Cache Memories, Virtual Memories.
Introduction
• Arithmetic instructions in digital computers manipulate data to produce results
necessary for the solutions of computational problems. These instructions
perform arithmetic calculations and are responsible for the bulk of activity
involved in processing data in a computer.
• The four basic arithmetic operations are addition,subtraction,multiplication and
division.
• From these four basic operations , it is possible to formulate other arithmetic
functions and solve problems by means of numerical analysis methods.
• An arithmetic processor is the pat of a processor unit that executes arithmetic
operations.
• An arithmetic instruction may specify binary or decimal data, and in each case
the data may be in fixed-point or floating point form.
• Negative numbers may be in signed magnitude or signed compliment
representation.
• Fixed point numbers may represents integers or fractions.
What is algorithm?
 The solution to any problem that is stated by a finite number of well-
defined procedural steps is called an Algorithm.

In this class we develop the various arithmetic algorithms and show the
procedure for implementing them with digital hardware
we consider addition,subtraction,multiplication,and division for the
following types of data:
 Fixed point binary data in signed-magnitude representation
 Fixed point binary data in signed-2’s compliment representation
 Floating point binary data
 Binary-coded decimal(BCD) data
Addition and Subtraction
The addition and subtraction algorithm for data represented in signed
magnitude and again data represented in signed-2’s complement.
It is important to realize that the adopted representation for negative
numbers refers to the representation of numbers in the register before
and after the execution of the arithmetic operations.

Addition and Subtraction with Signed-magnitude Data:

The representation of numbers in signed-magnitude is familiar because
it is used in everyday arithmetic calculation. The procedure for adding
or subtracting two signed binary numbers with paper and pencils
simple and straight-forward. A review of this procedure will be helpful
for deriving the hardware algorithm.
Cont.……..
We designated the magnitude of the two numbers by A and B. when the
signed numbers are added or subtracted, we find that there are eight
different conditions to consider, depending on the sign of the numbers
and the operation performed. These conditions are listed in the first
column of the table below. The other column in the table show the actual
operation to be performed with the magnitude of the numbers.
The last column is needed to prevent negative zero. In other words ,when
two equal numbers are subtracted, the result should be +0 not -0.
The algorithms for addition and subtraction are derived from the table
and can be stated as follows (the words inside parentheses should be
used for the subtraction algorithm)
Addition (subtraction) algorithm: when the signs of A and B are identical
(different), add the two magnitude and attach the sign of A to the result.
When the sign of A and B are different (identical),compare the
magnitudes.
Hardware implementation
To implement the two arithmetic operations with hardware,it is first necessary
that the two numbers be stored in registers. Let A and B be two registers that
hold the magnitude of the numbers, and As and Bs be two flipflops that hold
the corresponding signs. The results of the operation may be transferred to a
third register however, a saving achieved if the result is transferred into A and
As . thus A and As together from an accumulator register.
Consider now the hardware implementation of the algorithms above. First, a
parallel adder is needed to perform the micro operation A+B. second,
comparator circuit is needed to establish if A>B, A=B, or A<B. third, two
parallel subtractor circuits are needed to perform the micro operation A-B and
B-A. The sign relationship can be determined from an exclusive-OR gate with As
and Bs as inputs.
The output carry is transferred to flip-flop E.
The complementer consists of exclusive-OR gates and the parallel adder
consists of full adder circuit.
Hardware algorithm
The two signs As and Bs are compared by an exclusive-OR gate .
For an add operation, identical signs dictate that the magnitudes be added,
for subtract operation different signs dictate that the magnitudes be added.
The magnitudes are added with a micro operation E AA+B.. Where E A is a
register that combines E and A .

For A 0 indicates that A<B, for this case it is necessary to take the 2’s
compliment of the value in A .this operation can be done with one micro
operation AĀ+1.

However , we assume that A register as circuits for micro operation

compliment and increment, so the 2’s compliment is obtain from these two
micro operations…

The value in AVF provides an overflow indication.

The final value of E is immaterial.

Addition and Subtraction with signed2’s complement
data
The left most bit of binary number represents the sign bit; 0 for positive and 1
for negative. If the sign bit is 1, the entire the entire number is represented in
2’s compliment form.
The addition of two numbers in signed-2’s complement form consists of adding
the number with the sign bits treated the same as the other bits of the number .
A carry out of the sign bit position is discarded .
The subtraction consists of first taking the 2’s compliment of the subtrahend and
then adding it to the minuend
When two numbers of n digits each are added and the sum occupies n+1 Digits,
we say that an overflow occurred.
When the two carries are applied to an exclusive-OR gate, the overflow is
detected when the output of the gate is equal to 1.
 The left most bit in AC and BR represents the sign bits of the numbers
 The over flow flip-flops V is set to 1 if there is an overflow. The output carry in this case is
discarded.
 The sum is obtained by adding the contents of AC and BR(including their sign bits). The
overflow bit V is set to 1 if the ex-OR of the last two carries is 1,and it is cleared to 0
otherwise.
 Unit 7 – Computer Arithmetic

1. Explain the procedure for Addition and Subtraction with

signed-magnitude data with the help of flowchart.
 The flowchart is shown in Figure 7.1. The two signs A, and B, are compared by an
exclusive-OR gate.
If the output of the gate is 0 the signs are identical;
If it is 1, the signs are different.
 For an add operation, identical signs dictate that the magnitudes be added. For a
subtract operation, different signs dictate that the magnitudes be added.
 The magnitudes are added with a microoperation EA  A + B, where EA is a register that
combines E and A. The carry in E after the addition constitutes an overflow if it is equal
to 1. The value of E is transferred into the add-overflow flip-flop AVF.
 The two magnitudes are subtracted if the signs are different for an add operation or
identical for a subtract operation. The magnitudes are subtracted by adding A to the 2's
complemented B. No overflow can occur if the numbers are subtracted so AVF is cleared
to 0.
 1 in E indicates that A >= B and the number in A is the correct result. If this numbs is zero,
the sign A must be made positive to avoid a negative zero.
 0 in E indicates that A < B. For this case it is necessary to take the 2's complement of the
value in A. The operation can be done with one microoperation A A' +1.
 However, we assume that the A register has circuits for microoperations complement
and increment, so the 2's complement is obtained from these two microoperations.
 In other paths of the flowchart, the sign of the result is the same as the sign of A. so no
change in A is required. However, when A < B, the sign of the result is the complement of
the original sign of A. It is then necessary to complement A, to obtain the correct sign.
 The final result is found in register A and its sign in A s. The value in AVF provides an
overflow indication. The final value of E is immaterial.
 Figure 7.2 shows a block diagram of the hardware for implementing the addition and
subtraction operations.
 It consists of registers A and B and sign flip-flops As and Bs.
 Subtraction is done by adding A to the 2's complement of B.
 The output carry is transferred to flip-flop E , where it can be checked to determine the
relative magnitudes of two numbers.
 The add-overflow flip-flop AVF holds the overflow bit when A and B are added.
 The A register provides other microoperations that may be needed when we specify the
sequence of steps in the algorithm.

1
 Unit 7 – Computer Arithmetic

Subtract Operation Addition Operation

Minuend in A Augend in A

=0 =1 =1 =0
A s ⊕ Bs A s ⊕ Bs

EA ← A+ B’ + 1
EA ← A+ B
As ≠ Bs
As ≠ Bs As = Bs
=0 =1
AVF ← E
E A≥B
A<B
≠0 =0
A ← A’ A

A←A+1 AS ← 0

As ← As ’

END

Figure 7.1: Flowchart for add and subtract operations.

Figure 7.2: Hardware for signed-magnitude addition and subtraction

2
Multiplication algorithms:-
multiplication of two fixed point binary numbers in signed
magnitude representation is done with paper and pencil of
successive shift and add operation

if the multiplier bit is a 1,the multiplicand is copied down;

otherwise zero are copied down.
Hardware Implementation for Signed-Magnitude data
 When multiplication is implemented in a digital computer, it is convenient to
change the process slightly. First instead of providing register to store and add
simultaneously as many binary numbers as there are bits in the multiplier , as it
is convenient to provide an adder for the summation of only two binary
numbers and successively accumulate the partial products in a register. Second
instead of shifting the multiplicand to the left , the partial product is shifted to
the right
 The hardware for multiplication consists of the equipment shown in fig. plus
two are more registers.
 These registers are together with registers A and B..
 The multiplier stored in the Q register and its sign in Qs The sequence counter
SC is initially set to a number equal to the number of bits in the multiplier. The
counter is decremented by 1 after forming each partial product
 The sum of A and B forms a partial product which is transferred to the EA
register .
The shift will be denoted by the statement shr EAQ to designate the
right shift depicted .
The least significant bit of A is shifted into the most significant position
of Q.
Hardware Algorithm
Below fig.is a flowchart of the hardware multiply algorithm.. Initially the multiplicand is in B and the
multiplier in Q there corresponding signs are in Bs and Qs .,respectively.
Register A and E are cleared and the sequence counter
SG is set to a number equal to the number of bits of the
multiplier.
After the initialization , the low order bit of the multiplier
is in Qn is tested .if it is 1,the multiplicand In B is added to
the present partial product in A . If it is 0, nothing is done .
Register EAQ shifted once to the right to form the new
partial product.
The process stops when SC=0.
Note that the partial product formed in A is shifted into Q
one bit at a time and eventually replaces multiplier.
The final product is available in both A and Q,with A holding
the most significant bits and Q holding the least significant
bits.
Booth Multiplication Algorithm
 Booth Algorithm gives a procedure for multiplying binary integers in signed-2’s compliment
representation .
Hardware for booth algorithm
 The algorithm requires the register configuration as shown in fig.
Booth algorithm for multiplication of signed-2’s compliment

The two bits of multiplier in Qn and Qn+1

are inspected . If the two bits are equal to
10 it means that the first 1 in a string of 1’s
has been encountered

The final value of Qn+1 is the original sign

bit of the multiplier and should not be taken
as part of the product
 Unit 7 – Computer Arithmetic

2. Explain the Booth’s algorithm with the help of flowchart.

(Sum ’14,Win ’14, win’15)
 Booth algorithm gives a procedure for multiplying binary integers in signed- 2’s
complement representation.
 It operates on the fact that strings of 0’s in the multiplier require no addition but just
shifting, and a string of 1’s in the multiplier from bit weight 2 k to weight 2m can be
treated as 2k+1 – 2m.
 For example, the binary number 001110 (+14) has a string 1’s from 23 to 21 (k=3, m=1).
The number can be represented as 2k+1 – 2m. = 24 – 21 = 16 – 2 = 14. Therefore, the
multiplication M X 14, where M is the multiplicand and 14 the multiplier, can be done as
M X 2 4 – M X 2 1.
 Thus the product can be obtained by shifting the binary multiplicand M four times to the
left and subtracting M shifted left once.

Multiply

Multiplicand in BR
Multiplier in QR

AC ← 0

Qn + 1 ← 0

= 10 = 01
QnQn+1

AC ← AC + BR’ + 1 = 00 AC ← AC + BR

ashr (AC & QR)

≠0 =0
SC

END
Figure 7.3: Booth algorithm for multiplication of signed-2's complement numbers

 As in all multiplication schemes, booth algorithm requires examination of the multiplier

bits and shifting of partial product.

3
 Unit 7 – Computer Arithmetic

 Prior to the shifting, the multiplicand may be added to the partial product, subtracted
from the partial, or left unchanged according to the following rules:
1. The multiplicand is subtracted from the partial product upon encountering the
first least significant 1 in a string of 1’s in the multiplier.
2. The multiplicand is added to the partial product upon encountering the first 0 in a
string of 0’s in the multiplier.
3. The partial product does not change when multiplier bit is identical to the
previous multiplier bit.
 The algorithm works for positive or negative multipliers in 2’s complement
representation.
 This is because a negative multiplier ends with a string of 1’s and the last operation will
be a subtraction of the appropriate weight.
 The two bits of the multiplier in Qn and Qn+1 are inspected.
 If the two bits are equal to 10, it means that the first 1 in a string of 1 's has been
encountered. This requires a subtraction of the multiplicand from the partial product in
AC.
 If the two bits are equal to 01, it means that the first 0 in a string of 0's has been
encountered. This requires the addition of the multiplicand to the partial product in AC.
 When the two bits are equal, the partial product does not change.

3. Explain with proper block diagram the Multiplication Operation

on two floating point numbers.
 The multiplication of two floating-point numbers requires that we multiply the mantissas
and add the exponents.
 No comparison of exponents or alignment of mantissas is necessary.
 The multiplication of the mantissas is performed in the same way as in fixed-point to
provide a double-precision product.
 The double-precision answer is used in fixed-point numbers to increase the accuracy of
the product.
 In floating-point, the range of a single-precision mantissa combined with the exponent is
usually accurate enough so that only single-precision numbers are maintained.
 Thus the half most significant bits of the mantissa product and the exponent will be
taken together to form a single-precision floating-point product.
 The multiplication algorithm can be subdivided into four parts:
1. Check for zeros.
2. Add the exponents.
3. Multiply the mantissas.
4. Normalize the product.
 The flowchart for floating-point multiplication is shown in Figure 7.4. The two operands
are checked to determine if they contain a zero.
 If either operand is equal to zero, the product in the AC is set to zero and the operation
is terminated.
4
 Unit 7 – Computer Arithmetic

 If neither of the operands is equal to zero, the process continues with the exponent
addition.
 The exponent of the multiplier is in q and the adder is between exponents a and b.
 It is necessary to transfer the exponents from q to a, add the two exponents, and
transfer the sum into a.

Multiplicand in BR
Multiplier in QR

=0
BR
≠0
=0
QR

AC ← 0 ≠0

a←q

a←a+b

a ← a - bias

Multiply mantissa

=0
shl AQ
A1
a←a-1
=1

END
(product is in AC)

Figure 7.4: Multiplication of floating-point numbers

 Since both exponents are biased by the addition of a constant, the exponent sum will
have double this bias.
 The correct biased exponent for the product is obtained by subtracting the bias number
from the sum.
 The multiplication of the mantissas is done as in the fixed-point case with the product
residing in A and Q.
 Overflow cannot occur during multiplication, so there is no need to check for it.
 The product may have an underflow, so the most significant bit in A is checked. If it is a
1, the product is already normalized.

5
 Unit 7 – Computer Arithmetic

 If it is a 0, the mantissa in AQ is shifted left and the exponent decremented.

 Note that only one normalization shift is necessary. The multiplier and multiplicand were
originally normalized and contained fractions. The smallest normalized operand is 0.1, so
the smallest possible product is 0.01.
 Therefore, only one leading zero may occur.
 Although the low-order half of the mantissa is in Q, we do not use it for the floating-
point product. Only the value in the AC is taken as the product.

4. Multiply the (-9) with (-13) using Booth’s algorithm. Give each
step. (Sum’14)
 A numerical example of booth algorithm is shown for n=5. It shows the step-by-step
multiplication of (-9) X (-13) = +117.
9: 01001 13: 01101
1’s complement of 9: 10110 1’s complement of 13: 10010
+ 1 + 1
2’s complement of 9: 10111 (-9) 2’s complement of 13: 10011 (-13)
AC QR(-13) Qn+1 M(BR)(-9) SC Comments
00000 10011 0 10111 5 Initial value
01001 10011 0 10111 Subtraction: AC=AC+BR’+1
4
00100 11001 1 10111 Arithmetic Shift Right
00010 01100 1 10111 3 Arithmetic Shift Right
11001 01100 1 10111 Subtraction: AC=AC+BR’+1
2
11100 10110 0 10111 Arithmetic Shift Right
11110 01011 0 10111 1 Arithmetic Shift Right
00111 01011 0 10111 Subtraction: AC=AC+BR’+1
0
00011 10101 1 10111 Arithmetic Shift Right
Answer: -9 X -13 =117 => 001110101

5. Multiply the (7) with (3) using Booth’s algorithm. Give each
step.
7: 0111 3: 0011

AC QR(3) Qn+1 M(BR)(7) SC Comments

0000 0011 0 0111 4 Initial value
1001 0011 0 0111 Subtraction: AC=AC+BR’+1
3
1100 1001 1 0111 Arithmetic Shift Right
1110 0100 1 0111 2 Arithmetic Shift Right
0101 0100 1 0111 Addition: AC=AC+BR
1
0010 1010 0 0111 Arithmetic Shift Right
0001 0101 0 0111 0 Arithmetic Shift Right

6
 Unit 7 – Computer Arithmetic

Answer: 7 X 3 =21 => 00010101

6. Multiply the (15) with (13) using Booth’s algorithm. Give each
step.
15: 01111 13: 01101
15X13=195
AC QR(15) Qn+1 M(BR)(13) SC Comments
00000 01111 0 01101 5 Initial value
10011 01111 0 01101 Subtraction: AC=AC+BR’+1
4
11001 10111 1 01101 Arithmetic Shift Right
11100 11011 1 01101 3 Arithmetic Shift Right
11110 01101 1 01101 2 Arithmetic Shift Right
11111 00110 1 01101 1 Arithmetic Shift Right
01100 00110 1 01101 Addition: AC=AC+BR
0
00110 00011 1 01101 Arithmetic Shift Right
Answer: 15X13=195 => 0011000011

7. Multiply the (+15) with (-13) using Booth’s algorithm. Give each
step.
15: 01111 13: 01101
1’s complement of 13: 10010
+ 1
2’s complement of 13: 10011 (-13)

AC QR(-13) Qn+1 M(BR)(+15) SC Comments

00000 10011 0 01111 5 Initial value
10001 10011 0 01111 Subtraction: AC=AC+BR’+1
4
11000 11001 1 01111 Arithmetic Shift Right
11100 01100 1 01111 3 Arithmetic Shift Right
01011 01100 1 01111 Addition: AC=AC+BR
2
00101 10110 0 01111 Arithmetic Shift Right
00010 11011 0 01111 1 Arithmetic Shift Right
10011 11011 0 01111 Subtraction: AC=AC+BR’+1
0
11001 11101 1 01111 Arithmetic Shift Right

Answer: (+15) X (-13) = -195 => 1100111101

To verify 0011000010
+ 1

+195=> 0011000011

7
Array multiplier
 The multiplication of the two binary numbers can be done with one micro-operation by means of a
combinational circuit that forms the product bits all at once. This is a fast way of multiplying two
numbers since all it takes is the time for the signals to propagate through the gate that form the
multiplication array.
4 bit by 3 bit array multiplexer
Division Algorithm
 Division of two fixed-point binary numbers in signed magnitude
representation is done with paper and pencil by a process of successive
compare ,shift ,and subtract operations ..

Hardware implantation of signed magnitude data

Example of binary division with digital hardware
Instead of shifting the divisor to the right, the dividend
or partial remainder, is shifted to the left, thus leaving
the two numbers in the required relative position,
subtraction may be achieved by adding A to the 2’s
compliment of B.
EAQ is shifted to the left with 0 instead of Qn and the
previous value of E lost.
The divisor is stored in the B register and the double
length dividend is stored in register A and Q
The information about relative magnitude is available
in E. if E=1,it signifies that A ≥B. A quotient bit 1 is
inserted into Qn and the partial remainder is shifted
left to repeat the process. If E=0, it signifies that A<B
so the quotient in Qn remains a 0.
The sign of the remainder is the same as the sign of
the dividend .
Divide overflow
 This occurs because any dividend will be greater than or equal to zero.
 Over flow condition is usually detected when a special flip-flop is set .
Which will call it a divide overflow flip-flop and label it DVF
 The occurrence of a divide overflow can be handled in variety of ways
 In some computers it is the responsibility of the programmers to check
if DVF is set after each divide instruction
 The occurrence of a divide overflow stopped the computer and this
condition was referred to as a DIVIDE STOP.
 The best way to avoid a divide overflow is to use floating point data
 The divide overflow can be handled very simply if numbers are in
floating point representation.
Hardware algorithm
The dividend is in A and Q and the divisor in B.
The sign of the results transferred into Qs to
be part of quotient.
A divide overflow condition is tested by
subtracting divisor in B from half of the bits of
the dividend stored in A. if A≥B, the divide
overflow flip-flop DVF set and the operation is
terminated prematurely.
By doing the process as shown in the flowchart
the quotient magnitude is formed in register Q
and the remainder is found in the register A.
The quotient sign is in Qs and the sign of the
remainder in As is the same as the original sign
of the dividend.
What is restoring method?
 The hardware method just described is
called the RESTORING METHOD. The reason for the name is that the
partial remainder is restored by adding the divisor to the negative
difference. Two other methods are available for dividing numbers,
the COMPARISION method and the NONRESTORING method. In the
comparison method A and B are compared prior to the subtraction
operation .
 No restoring method B is not added if the difference is negative but
instead, the negative difference is shifted left and then B is added.
 RESTORING DIVISION
A division algorithm provides a quotient and a remainder
when we divide two number. They are generally of two
type slow algorithm and fast algorithm. Slow division
algorithm are restoring, non-restoring, non-performing
restoring, SRT algorithm and under fast comes Newton–
Raphson and Goldschmidt.
In this article, will be performing restoring algorithm for
unsigned integer. Restoring term is due to fact that value of
register A is restored after each iteration.
•Step-1: First the registers are initialized with corresponding
values (Q = Dividend, M = Divisor, A = 0, n = number of bits in
dividend)
•Step-2: Then the content of register A and Q is shifted left as if
they are a single unit
•Step-3: Then content of register M is subtracted from A and
result is stored in A
•Step-4: Then the most significant bit of the A is checked if it is
0 the least significant bit of Q is set to 1 otherwise if it is 1 the
least significant bit of Q is set to 0 and value of register A is MSB
restored i.e the value of A before the subtraction with M of
A=1
•Step-5: The value of counter n is decremented
•Step-6: If the value of n becomes zero we get of the loop
otherwise we repeat from step 2
•Step-7: Finally, the register Q contain the quotient and A
contain remainder
 n M A Q Operation
4 00011 00000 1011 initialize

00011 00001 011_ shift left AQ

Examples:
Perform Division Restoring 00011 11110 011_ A=A-M
Algorithm Dividend = 11
Divisor = 3 Q[0]=0 And restore
00011 00001 0110
A

3 00011 00010 110_ shift left AQ

00011 11111 110_ A=A-M

00011 00010 1100 Q[0]=0

2 00011 00101 100_ shift left AQ

00011 00010 100_ A=A-M

00011 00010 1001 Q[0]=1

1 00011 00101 001_ shift left AQ

00011 00010 001_ A=A-M

00011 00010 0011 Q[0]=1

Remember to restore the value of A most significant bit of
A is 1. As that register Q contain the quotient, i.e. 3 and
register A contain remainder 2
 NON
restoring division

Non-Restoring division, it is less complex than the restoring one because simpler operation are
involved i.e. addition and subtraction, also now restoring step is performed. In the method, rely on
the sign bit of the register which initially contain zero named as A.
MSB of
A=1

MSB of
A=1
•Step-1: First the registers are initialized with
corresponding values (Q = Dividend, M = Divisor, A = 0,
n = number of bits in dividend)
•Step-2: Check the sign bit of register A
•Step-3: If it is 1 shift left content of AQ and perform A
= A+M, otherwise shift left AQ and perform A = A-M
(means add 2’s complement of M to A and store it to A)
•Step-4: Again the sign bit of register A
•Step-5: If sign bit is 1 Q[0] become 0 otherwise Q[0]
become 1 (Q[0] means least significant bit of register
Q)
•Step-6: Decrements value of N by 1
•Step-7: If N is not equal to zero go to Step 2 otherwise
go to next step
•Step-8: If sign bit of A is 1 then perform A = A+M
•Step-9: Register Q contain quotient and A contain
remainder
 N M A Q Action
Examples: Perform Non_Restoring
4 00011 00000 1011 Start
Division for Unsigned Integer
Dividend =11 Divisor =3 -M =11101
00001 011_ Left shift AQ

11110 011_ A=A-M

3 11110 0110 Q[0]=0

11100 110_ Left shift AQ

11111 110_ A=A+M

2 11111 1100 Q[0]=0

11111 100_ Left Shift AQ

00010 100_ A=A+M

1 00010 1001 Q[0]=1

Quotient = 3 (Q)
00101 001_ Left Shift AQ
Remainder = 2 (A)
00010 001_ A=A-M

0 00010 0011 Q[0]=1

Floating point Arithmetic operation
 Floating point number in computer register consists of two parts: a mantissa m and
exponent e --------> m X re
 A floating point number that has a 0 in the most significant position of the mantissa is
said to have an UNDERFLOW. To normalize a number that contains an underflow, it is
necessary to shift the mantissa to the left and decrement the exponent until a nonzero
digit appears in the first position.

Register configuration
The register configuration for floating point operation is
quite similar to the layout for fixed point operation. As a general rule, the same
register and adder used for fixed point arithmetic are used for processing the
mantissas. The difference lies in the way the exponents are handled.
Register organization

There are three registers, BR, AC,and QR.

Each register is subdivided into two parts.
The mantissa part has same upper case
letters, the exponent part uses the corres-
ponding lower case letters.

A parallel adder adds the two mantissas

and transfers the sum into A and the carry
into E. A separate parallel adder is used
for the exponents. Since the exponents
are biased.
Addition and subtraction
 During addition and subtraction , the two floating point
operands are in AC and BR. The sum of difference is
formed in the AC . The algorithm can be divided into
four consecutive parts :
1. Check for zeros.
2. Align the mantissa.
3. Add or subtract the mantissa.
4. Normalize the result.
Multiplication
 The multiplication of two floating point numbers requires that we
multiply the mantissas and add the exponents. No comparison of
exponents or alignment of mantissa is necessary.
 The multiplication of the mantissa is performed same as fixed point to
provide a double precision product.
 The multiplication algorithm can be subdivided into four parts :-
1. Check for zeros.
2. Add the exponents.
3. Multiply the mantissa.
4. Normalize the product.
Division
 Floating point division requires that the exponents be subtracted
and the mantissa divided. The mantissa division is done as in fixed
point except that the dividend has a single precision mantissa
that is placed in the AC.
 The division algorithm can be divided into five parts..
1. Check for zeros.
2. Initialize registers and evaluate the sign.
3. Align the dividend
4. Subtract the exponents.
5. Divide the mantissa.
 Unit 9 – Memory Organization

1. How main memory is useful in computer system? Explain the

memory address map of RAM and ROM. (Sum’15)

Main Memory
 The main memory is the central storage unit in a computer system.
 Primary memory holds only those data and instructions on which computer is currently
working.
 It has limited capacity and data is lost when power is switched off.
 It is generally made up of semiconductor device.
 These memories are not as fast as registers.
 The data and instruction required to be processed reside in main memory.
 It is divided into two subcategories RAM and ROM.

Memory address map of RAM and ROM

Figure 9.1: Typical RAM chip

Figure 9.2: Typical ROM chip

 The designer of a computer system must calculate the amount of memory required for
the particular application and assign it to either RAM or ROM.
 The interconnection between memory and processor is then established from
knowledge of the size of memory needed and the type of RAM and ROM chips available.
 The addressing of memory can be established by means of a table that specifies the
memory address assigned to each chip.
 The table, called a memory address map, is a pictorial representation of assigned
address space for each chip in the system, shown in table 9.1.
 To demonstrate with a particular example, assume that a computer system needs 512
bytes of RAM and 512 bytes of ROM.
 The RAM and ROM chips to be used are specified in figure 9.1 and figure 9.2.

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 Unit 9 – Memory Organization

Table 9.1: Memory Address Map for Micro-procomputer

 The component column specifies whether a RAM or a ROM chip is used.
 The hexadecimal address column assigns a range of hexadecimal equivalent addresses
for each chip.
 The address bus lines are listed in the third column.
 Although there are 16 lines in the address bus, the table shows only 10 lines because the
other 6 are not used in this example and are assumed to be zero.
 The small x's under the address bus lines designate those lines that must be connected
to the address inputs in each chip.
 The RAM chips have 128 bytes and need seven address lines. The ROM chip has 512
bytes and needs 9 address lines.
 The x's are always assigned to the low-order bus lines: lines 1 through 7 for the RAM and
lines 1 through 9 for the ROM.
 It is now necessary to distinguish between four RAM chips by assigning to each a
different address. For this particular example we choose bus lines 8 and 9 to represent
four distinct binary combinations.
 The table clearly shows that the nine low-order bus lines constitute a memory space for
RAM equal to 29 = 512 bytes.
 The distinction between a RAM and ROM address is done with another bus line. Here we
choose line 10 for this purpose.
 When line 10 is 0, the CPU selects a RAM, and when this line is equal to 1, it selects the
ROM.

2. Explain Content Addressable Memory (CAM). (Sum’15)

 The time required to find an item stored in memory can be reduced considerably if
stored data can be identified for access by the content of the data itself rather than by
an address.
 A memory unit accessed by content is called an associative memory or content
addressable memory (CAM).
 This type of memory is accessed simultaneously and in parallel on the basis of data
content rather than by specific address or location.
 The block diagram of an associative memory is shown in figure 9.3.

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 Unit 9 – Memory Organization

Figure 9.3: Block diagram of associative memory

 It consists of a memory array and logic form words with n bits per word.
 The argument register A and key register K each have n bits, one for each bit of a word.
 The match register M has m bits, one for each memory word.
 Each word in memory is compared in parallel with the content of the argument register.
 The words that match the bits of the argument register set a corresponding bit in the
match register.
 After the matching process, those bits in the match register that have been set indicate
the fact that their corresponding words have been matched.
 Reading is accomplished by a sequential access to memory for those words whose
corresponding bits in the match register have been set.

Hardware Organization
 The key register provides a mask for choosing a particular field or key in the argument
word.
 The entire argument is compared with each memory word if the key register contains all
1's.
 Otherwise, only those bits in the argument that have 1st in their corresponding position
of the key register are compared.
 Thus the key provides a mask or identifying piece of information which specifies how the
reference to memory is made.
 To illustrate with a numerical example, suppose that the argument register A and the key
register K have the bit configuration shown below.
 Only the three leftmost bits of A are compared with memory words because K has 1's in
these position.

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 Unit 9 – Memory Organization

A 101 111100
K 111 000000
Word1 100 111100 no match
Word2 101 000001 match
 Word 2 matches the unmasked argument field because the three leftmost bits of the
argument and the word are equal.

Figure 9.4: Associative memory of m word, n cells per word.

 The relation between the memory array and external registers in an associative memory
is shown in figure 9.4.
 The cells in the array are marked by the letter C with two subscripts.
 The first subscript gives the word number and the second specifies the bit position in
the word.
 Thus cell Cij is the cell for bit j in words i.
 A bit Aj in the argument register is compared with all the bits in column j of the array
provided that Kj =1.
 This is done for all columns j = 1, 2... n.
 If a match occurs between all the unmasked bits of the argument and the bits in word i,
the corresponding bit Mi in the match register is set to 1.
 If one or more unmasked bits of the argument and the word do not match, Mi is cleared
to 0.

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 Unit 9 – Memory Organization

3. Define Cache memory. Discuss associative mapping in

organization of cache memory. (Win’15)
Cache memory
 Cache is a fast small capacity memory that should hold those information which are
most likely to be accessed.
 The basic operation of the cache is, when the CPU needs to access memory, the cache is
examined.
 If the word is found in the cache, it is read from the fast memory. If the word addressed
by the CPU is not found in the cache, the main memory is accessed to read the word.
 The transformation of data from main memory to cache memory is referred to as a
mapping process.
Associative mapping
 Consider the main memory can store 32K words of 12 bits each.
 The cache is capable of storing 512 of these words at any given time.
 For every word stored in cache, there is a duplicate copy in main memory.
 The CPU communicates with both memories.
 It first sends a 15-bit address to cache. If there is a hit, the CPU accepts the 12-bit data
from cache, if there is miss, the CPU reads the word from main memory and the word is
then transferred to cache.

Figure 9.5: Associative mapping cache (all numbers in octal)

 The associative memory stores both the address and content (data) of the memory
word.
 This permits any location in cache to store any word from main memory.
 The figure 9.5 shows three words presently stored in the cache. The address value of 15
bits is shown as a five-digit octal number and its corresponding 12-bit word is shown as a
four-digit octal number.
 A CPU address of 15 bits is placed in the argument register and the associative memory
is searched for a matching address.
 If the address is found the corresponding 12-bit data is read and sent to CPU.
 If no match occurs, the main memory is accessed for the word.
 The address data pairs then transferred to the associative cache memory.
 If the cache is full, an address data pair must be displaced to make room for a pair that is
needed and not presently in the cache.
 This constitutes a first-in first-one (FIFO) replacement policy.
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 Unit 9 – Memory Organization

4. Discuss direct mapping in organization of cache memory. (Win’15)

 The CPU address of 15 bits is divided into two fields.
 The nine least significant bits constitute the index field and the remaining six bits from
the tag field.
 The figure 9.6 shows that main memory needs an address that includes both the tag and
the index.

Figure 9.6: Addressing relationships between main and cache memories

 The number of bits in the index field is equal to the number of address bits required to
access the cache memory.
 The internal organization of the words in the cache memory is as shown in figure 9.7.

Figure 9.7: Direct mapping cache organization

 Each word in cache consists of the data word and its associated tag.
 When a new word is first brought into the cache, the tag bits are stored alongside the
data bits.
 When the CPU generates a memory request the index field is used for the address to
access the cache.
 The tag field of the CPU address is compared with the tag in the word read from the
cache.
 If the two tags match, there is a hit and the desired data word is in cache.
 If there is no match, there is a miss and the required word is read from main memory.
 It is then stored in the cache together with the new tag, replacing the previous value.
 The word at address zero is presently stored in the cache (index = 000, tag = 00, data =
1220).

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 Unit 9 – Memory Organization

 Suppose that the CPU now wants to access the word at address 02000.
 The index address is 000, so it is used to access the cache. The two tags are then
compared.
 The cache tag is 00 but the address tag is 02, which does not produce a match.
 Therefore, the main memory is accessed and the data word 5670 is transferred to the
CPU.
 The cache word at index address 000 is then replaced with a tag of 02 and data of 5670.
 The disadvantage of direct mapping is that two words with the same index in their
address but with different tag values cannot reside in cache memory at the same time.

5. Discuss set-associative mapping in organization of cache

memory.
 A third type of cache organization, called set associative mapping in that each word of
cache can store two or more words of memory under the same index address.
 Each data word is stored together with its tag and the number of tag-data items in one
word of cache is said to form a set.
 An example one set-associative cache organization for a set size of two is shown in figure
9.8.

Figure 9.8: Two-way set-associative mapping cache

 Each index address refers to two data words and their associated terms.
 Each tag required six bits and each data word has 12 bits, so the word length is 2 (6+12)
= 36 bits.
 An index address of nine bits can accommodate 512 words.
 Thus the size of cache memory is 512 × 36. It can accommodate 1024 words or main
memory since each word of cache contains two data words.
 In generation a set-associative cache of set size k will accommodate K word of main
memory in each word of cache.
 The octal numbers listed in figure 9.8 are with reference to the main memory contents.
 The words stored at addresses 01000 and 02000 of main memory are stored in cache
memory at index address 000.
 Similarly, the words at addresses 02777 and 00777 are stored in cache at index address
777.
 When the CPU generates a memory request, the index value of the address is used to
access the cache.
 The tag field of the CPU address is then compared with both tags in the cache to
determine if a match occurs.

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 Unit 9 – Memory Organization

 The comparison logic is done by an associative search of the tags in the set similar to an
associative memory search: thus the name "set-associative”.
 When a miss occurs in a set-associative cache and the set is full, it is necessary to replace
one of the tag-data items with a new value.
 The most common replacement algorithms used are: random replacement, first-in first-
out (FIFO), and least recently used (LRU).

6. Explain Write-through and Write-back cache write method.

Write Through
 The simplest and most commonly used procedure is to update main memory with every
memory write operation.
 The cache memory being updated in parallel if it contains the word at the specified
address. This is called the write-through method.
 This method has the advantage that main memory always contains the same data as the
cache.
 This characteristic is important in systems with direct memory access transfers.
 It ensures that the data residing in main memory are valid at all times so that an I/O
device communicating through DMA would receive the most recent updated data.

Write-Back (Copy-Back)
 The second procedure is called the write-back method.
 In this method only the cache location is updated during a write operation.
 The location is then marked by a flag so that later when the word is removed from the
cache it is copied into main memory.
 The reason for the write-back method is that during the time a word resides in the
cache, it may be updated several times.
 However, as long as the word remains in the cache, it does not matter whether the copy
in main memory is out of date, since requests from the word are filled from the cache.
 It is only when the word is displaced from the cache that an accurate copy need be
rewritten into main memory.

7. What do you mean by address space and memory space in

virtual memory? Also explain the relation between address
space and memory space in virtual memory. (Win’15)

Virtual Memory
 Virtual memory is used to give programmers the illusion that they have a very large
memory at their disposal, even though the computer actually has a relatively small main
memory.
 A virtual memory system provides a mechanism for translating program-generated
addresses into correct main memory locations.
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 Unit 9 – Memory Organization

Address space
An address used by a programmer will be called a virtual address, and the set of such addresses
is known as address space.

Memory space
An address in main memory is called a location or physical address. The set of such locations is
called the memory space.
Auxiliary Memory Main Memory 32k=215

Program 1
Data 1,1
Data 1,2 Program 1

Program 2
Data 2,1
Data 1,1
Address space 1024k=210

Figure 9.9: Relation between address and memory space in a virtual memory system
 As an illustration, consider a computer with a main-memory capacity of 32K words (K =
1024). Fifteen bits are needed to specify a physical address in memory since 32K = 215.
 Suppose that the computer has available auxiliary memory for storing 220 = 1024K
words.
 Thus auxiliary memory has a capacity for storing information equivalent to the capacity
of 32 main memories.
 Denoting the address space by N and the memory space by M, we then have for this
example N = 1024K and M = 32K.
 In a multiprogramming computer system, programs and data are transferred to and
from auxiliary memory and main memory based on demands imposed by the CPU.
 Suppose that program 1 is currently being executed in the CPU. Program 1 and a portion
of its associated data are moved from auxiliary memory into main memory as shown in
figure 9.9.
 Portions of programs and data need not be in contiguous locations in memory since
information is being moved in and out, and empty spaces may be available in scattered
locations in memory.
 In our example, the address field of an instruction code will consist of 20 bits but physical
memory addresses must be specified with only 15 bits.
 Thus CPU will reference instructions and data with a 20-bit address, but the information
at this address must be taken from physical memory because access to auxiliary storage
for individual words will be too long.

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 Unit 9 – Memory Organization

8. Explain address mapping using pages.

 The table implementation of the address mapping is simplified if the information in the
address space and the memory space are each divided into groups of fixed size.
 The physical memory is broken down into groups of equal size called blocks, which may
range from 64 to 4096 words each.
 The term page refers to groups of address space of the same size.
 Consider a computer with an address space of 8K and a memory space of 4K.
 If we split each into groups of 1K words we obtain eight pages and four blocks as shown
in figure 9.9
 At any given time, up to four pages of address space may reside in main memory in any
one of the four blocks.

Figure 9.10 Address and Memory space split into group of 1K words

Figure 9.11: Memory table in paged system

 The organization of the memory mapping table in a paged system is shown in figure
9.10.
 The memory-page table consists of eight words, one for each page.
 The address in the page table denotes the page number and the content of the word
give the block number where that page is stored in main memory.
 The table shows that pages 1, 2, 5, and 6 are now available in main memory in blocks 3,
0, 1, and 2, respectively.
 A presence bit in each location indicates whether the page has been transferred from
auxiliary memory into main memory.
 A 0 in the presence bit indicates that this page is not available in main memory.

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 Unit 9 – Memory Organization

 The CPU references a word in memory with a virtual address of 13 bits.

 The three high-order bits of the virtual address specify a page number and also an
address for the memory-page table.
 The content of the word in the memory page table at the page number address is read
out into the memory table buffer register.
 If the presence bit is a 1, the block number thus read is transferred to the two high-order
bits of the main memory address register.
 The line number from the virtual address is transferred into the 10 low-order bits of the
memory address register.
 A read signal to main memory transfers the content of the word to the main memory
buffer register ready to be used by the CPU.
 If the presence bit in the word read from the page table is 0, it signifies that the content
of the word referenced by the virtual address does not reside in main memory.

9. What is segment? What is logical address? Explain segmented

page mapping.
Segment
A segment is a set of logically related instructions or data elements associated with a
given name.
Logical address
The address generated by segmented program is called a logical address.
Segmented page mapping
 The length of each segment is allowed to grow and contract according to the needs of
the program being executed. Consider logical address shown in figure 9.12.

Figure 9.12: Logical to physical address mapping

 The logical address is partitioned into three fields.
 The segment field specifies a segment number.
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 Unit 9 – Memory Organization

 The page field specifies the page within the segment and word field gives specific word
within the page.
 A page field of k bits can specify up to 2k pages.
 A segment number may be associated with just one page or with as many as 2k pages.
 Thus the length of a segment would vary according to the number of pages that are
assigned to it.
 The mapping of the logical address into a physical address is done by means of two
tables, as shown in figure 9.12.
 The segment number of the logical address specifies the address for the segment table.
 The entry in the segment table is a pointer address for a page table base.
 The page table base is added to the page number given in the logical address.
 The sum produces a pointer address to an entry in the page table.
 The concatenation of the block field with the word field produces the final physical
mapped address.
 The two mapping tables may be stored in two separate small memories or in main
memory.
 In either case, memory reference from the CPU will require three accesses to memory:
one from the segment table, one from the page table and the third from main memory.
 This would slow the system significantly when compared to a conventional system that
requires only one reference to memory.

12