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    DLD Week 4

    Uploaded by

    Salman Khan
    digital logic and design

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd

    DLD Week 4

    Uploaded by

    Salman Khan
    5 views4 pages
    digital logic and design

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    dld week 4

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    digital logic and design

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    5 views4 pages

    DLD Week 4

    Uploaded by

    Salman Khan
    digital logic and design

    Copyright:

    © All Rights Reserved
    Download as PDF, TXT or read online from Scribd
    Download as pdf or txt
    of 4

    Simplified Boolean expression to the minimum number of literals:

    Equipments:
    • Trainer/proto board
    • Wire cutter/stripper
    • Voltmeter
    • Patch cords
    • Integrated Circuits (ICs) representing different logic gates: AND gate (IC 7408), OR gate (IC
    7432), NOT gate (IC 7404), NAND gate (IC 7400), NOR gate (IC 7402), XOR gate (IC 7486).
    Theory:
    Introduction to Logic Gates and Their Functions:
    Logic gates are fundamental building blocks of digital circuits, responsible for performing logical
    operations on binary inputs to produce a binary output. They are based on Boolean algebra,
    which deals with variables that can take on two values: true (1) or false (0).
    In this lab, we are going to use three gates. One will be AND 2nd will be OR Gate. What we are
    going to do is that we will do complex output procedures to demonstrate and prove the given
    Boolean expression.
    1. AB+A(B+C)+B(B+C)

    Simplification:
    AB+AB+AC+BB+BC
    AB+AC+B+BC
    AB+AC+B(1+C)
    AB+AC+B
    B(A+1)+AC
    B(1)+AC AC+B

    TRUTH TABLE:

    A B C AC AC+B
    0 0 0 0 0
    0 0 1 0 0
    0 1 0 0 1
    0 1 1 0 1
    1 0 0 0 0
    1 0 1 1 1
    1 1 0 0 1
    1 1 1 1 1

    LOGIC DIAGRAMME:

    K-MAP:
    AC(B+B’) + B(A+A’)(C+C’)
    ACB+ACB’ +BA (C+C’) +BA’(C+C’)
    ABC+AB’C ABC+AB’C+AB’C+ABC +ABC’
    A’BC +A’BC’ (7,5,7,5,5,7,6,3,2) (2,3,5,6,7

    1. AB+AC(D+D’)

    Simplification:
    AB + AC A(B+C)

    TRUTH TABLE:
    A B C B+C A(B+C)
    0 0 0 0 0
    0 0 1 1 0
    0 1 0 1 0
    0 1 1 1 0
    1 0 0 0 0
    1 0 1 1 1
    1 1 0 1 1
    1 1 1 1 1

    K-MAP
    AB+AC
    AB(C+C’) + AC(B+B’)
    ABC+ABC’ + ABC+ AB’C
    (7,6,7,5)
    (5,6,7)

    Procedure:
    ➢ Verify the gates
    ➢ Connect the proper power supply
    ➢ Connections are given as per circuit diagram.
    ➢ Logical inputs are given as per circuit diagram.
    ➢ Observe the output and verify the truth table.

    Analysis:
    Simplify to minimum number of literals using properties
    F=A.B.C+A’+A.B’.C
    Lab Assignment:
    Simplify to minimum number of literals using properties and write a verilog code for simplified
    and original expression and generate a timing diagram. F=A.B.C+A’+A.B’.C

    Conclusion:
    Since the output of A(B+C) is correctly displayed on breadboard the experiment has successfully
    concluded.

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