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1995 JSSC
1995 JSSC
3, MARCH 1995
A 10 b, 20 Msample/s, 35
mW Pipeline A/D Converter
Thomas Byunghak Cho, Student Member, IEEE, and Paul R. Gray, Fellow, IEEE
Abstract-This paper describes a 10 b, 20 Msamplds pipeline In CMOS, two A D converter architectures attractive for
A/D converter implemented in 1.2 pm CMOS technology which sampling rate above 10 MS/s and resolution of 10 b are 2step-
achieves a power dissipation of 35 mW at full speed operation. flash and pipeline. For the 2step-flash architecture, the main
Circuit techniques used to achieve this level of power dissipation
include digital correction to allow the use of dynamic com- advantage is that it requires a smaller number of comparators
parators, and optimum scaling of capacitor values through the (-2”I2+l) compared to the full flash architecture (-2”) and
pipeline. Also, to be compatible with low voltage mixed-signal no operational amplifiers for sample-and-hold (SH) [ 11, [2].
system environments, a switched capacitor (SC) circuit in each However, the input bandwidth is usually limited to relatively
pipeline stage is implemented and operated at 3.3 V with a new low frequency compared to the high conversion rate, because
high-speed, low-voltage operational amplifier and charge pump
circuits. Measured performance includes 0.6 LSB of INL, 59.1 of the inherent parallel signal quantization scheme in which
dB of SNDR (Signal-to-Noise-plus-Distortion-Ratio) for 100 kHz comparator offsets and mismatches in signal paths get worse at
input at 20 Msamplds. At Nyquist sampling (10 MHz input), high speed. Therefore, without the use of a dedicated input SH
SNDR is 55.0 dB. Differential input range is fl V, and measured circuit, the 2step-flash architecture is limited to applications
input referred RMS noise is 220 pV. The power dissipation at 1 where the input signal bandwidth is limited to relatively low
MS/s is below 3 mW with 58 dB of SNDR.
frequency.
On the other hand, the pipeline A/D converter [3], [4]
can achieve good high input frequency dynamic performances
I. INTRODUCTION
due to a SH circuit in each stage of the pipeline which
V d V d
(a) (b)
Fig. 2. Residue plots (a) ideal (b) with comparator offset AV.
NCUlUdkd
poav
1.0
0.8
0.6
I I
0.4
02.
0x8
1 I I
=Rout x AV
vout+
7
60 A 09 #r
os f
55 0.7 r
50
/ Y
0.6 I
45
48 I input-referred
II
35
30
25
ZI
40 -30 -m -10 0
I.p( (dm
Fig. 11. Measured probability of getting a code i versus the dc input voltage.
Fig. 9. SNDR versus the input amplitude.
Porero
WB)
1.0
0.5 I 1
0.0
4.5 . .I ... ..,,, .,., . . _
I
-1.0 1
0 d e lo00
1 2 5 10 20
TABLE I
0.0 A/D PERFORMANCE: 3.3 V AND 25OC
-0.5
powcrDissipation 35mW'
0.5 LSB
0.6 LSB
A/D section in the end. Capacitors in the first three stages are SNDR 59.1 dB (F5m= 100 IrHz)
55.0 dB F m = 10 ME?)
calibrated with trim capacitor arrays to achieve high accuracy.
A die photo is shown in Fig. 8. Clock lines are routed in the * Output p d driverpowa unnrmptionnot incloded.
middle, and the analog signal path is folded around to make
the chip area square. Op amp bias circuits are shared between
several op amps, and all bias currents are controlled by one about 20 mW. At a reduced bias current and a sampling
frequency of 1 MSIs, the power consumption was 2.8 mW
external master bias current. Chip area not including the pad
ring is 3.2 x 3.3 mm2. with peak SNDR of 58 dB.
Fig. 9 shows SNDR versus the input amplitude for 100 kHz
and 10 MHz input frequencies at 20-MS/s conversion rate. VI. S m Y
The peak SNDR is 59.1 dB for 100 kHz input sine wave. At This paper describes a 10 b, 20 MSIs, 35 mW pipeline N D
Nyquist sampling (10 MHz input), the SNDR is 55.0 dB. converter in 1.2 pm CMOS technology, and its performance is
Fig. 11 shows the probability of getting a code i versus the summarized in Table I. The key features of this converter are:
dc input voltage near the code transition. The extracted total the usage of dynamic comparators and careful scaling of SC
input-referred RMS noise voltage from this plot was -220 pV circuits down the pipeline to achieve low power dissipation,
while the designed value was 216 pV. This confirms the RT/C and new low voltage op amps and charge pump circuits to
noise-limited design in the prototype. implement SC circuits for low voltage operation of pipeline
Fig. 12 shows the measured power consumption versus the stages. This shows that low voltage, low power operation
sampling frequency on a log-log scale. Of 35 mW of total of pipeline A/D converters can be achieved for video-rate
power dissipation at 20 MSIs, static power consumption was applications.
172 IEEE JOURNAL OF SOLlD-STATE CIRCUITS, VOL. 30, NO. 3, MARCH 1995