I 16h IEEE JOURNAL OF SOLID-STATE! CIRCUITS, VOL. 30, NO.

3, MARCH 1995

A 10 b, 20 Msample/s, 35
mW Pipeline A/D Converter
Thomas Byunghak Cho, Student Member, IEEE, and Paul R. Gray, Fellow, IEEE

Abstract-This paper describes a 10 b, 20 Msamplds pipeline In CMOS, two A D converter architectures attractive for
A/D converter implemented in 1.2 pm CMOS technology which sampling rate above 10 MS/s and resolution of 10 b are 2step-
achieves a power dissipation of 35 mW at full speed operation. flash and pipeline. For the 2step-flash architecture, the main
Circuit techniques used to achieve this level of power dissipation
include digital correction to allow the use of dynamic com- advantage is that it requires a smaller number of comparators
parators, and optimum scaling of capacitor values through the (-2”I2+l) compared to the full flash architecture (-2”) and
pipeline. Also, to be compatible with low voltage mixed-signal no operational amplifiers for sample-and-hold (SH) [ 11, [2].
system environments, a switched capacitor (SC) circuit in each However, the input bandwidth is usually limited to relatively
pipeline stage is implemented and operated at 3.3 V with a new low frequency compared to the high conversion rate, because
high-speed, low-voltage operational amplifier and charge pump
circuits. Measured performance includes 0.6 LSB of INL, 59.1 of the inherent parallel signal quantization scheme in which
dB of SNDR (Signal-to-Noise-plus-Distortion-Ratio) for 100 kHz comparator offsets and mismatches in signal paths get worse at
input at 20 Msamplds. At Nyquist sampling (10 MHz input), high speed. Therefore, without the use of a dedicated input SH
SNDR is 55.0 dB. Differential input range is fl V, and measured circuit, the 2step-flash architecture is limited to applications
input referred RMS noise is 220 pV. The power dissipation at 1 where the input signal bandwidth is limited to relatively low
MS/s is below 3 mW with 58 dB of SNDR.
frequency.
On the other hand, the pipeline A/D converter [3], [4]
can achieve good high input frequency dynamic performances
I. INTRODUCTION
due to a SH circuit in each stage of the pipeline which

R EDUCTION of the power dissipation associated with

high-speed sampling and quantization is a major problem
in many applications, including portable video devices such as
allows the signal to be processed through one single low-
noise path. In this way, path matching problems that are
critical in flash and two-step architectures can be eliminated.
camcorders, personal colnmunication devices such as wireless In addition, the SH circuit implemented in switched capacitor
LAN transceivers, in the read channels of magnetic storage (SC) gain configuration can provide amplification of the signal
devices using digital data detection, and many others. In the for finer conversion. When the interstage gain is incorporated
past high-speed A/D converters required for these applications with the use of digital correction, the comparator accuracy
in the sampling rate range above 5 Msample/s (MS/s) with requirements can be relaxed by making each stage of the
8-12 b of resolutions have consumed large power ranging pipeline capable of correcting comparator offset errors from
typically from 100-500 mW. For battery-powered portable previous stages. Although precision operational amplifiers are
applications, this level of power consumption may not be required to implement the SH circuit in each stage, potential
suitable, and further power reduction is essential for power- advantages in good dynamic performance and tolerance to
optimized A/D interfaces. comparator offset errors make a pipeline approach attractive
Low-voltage operation is another important key factor in for video-rate applications.
these portable A/D interface environments. With the trend In this paper, a power-optimized implementation of a 10
that A/D interfaces are incorporated as a cell in complex b CMOS pipeline A/D converter that operates at 3.3 V
mixed-signal IC’s containing mostly digital blocks for DSP and achieves 1.75 mW per MS/s of sampling rate at 20
and control, the use of the same supply-voltage for both analog MS/s is presented in four main parts. Section I1 gives an
and digital circuits can give advantages in reducing the overall overview of the 1.5 b/stage pipeline architecture. Section I11
system cost by eliminating the need of generating multiple introduces power reduction techniques. In Section IV, low
supply voltages with dc-dc converters. Therefore, in order to voltage implementations of key building blocks are described.
be compatible with low-voltage systems, a new generation of Finally, experimental results of the prototype are presented in
A D converters that can operate at supply voltage below 5 V Section V.
is desired.
11. 1.5 b/STAGE PIPELINE ARCHITECTURE
Manuscript received July 20, 1994; revised November 7, 1994. This work
was supported by the Advanced Research Projects Agency (ARPA) and the A block diagram of a typical pipeline A/D converter is
National Science Foundation (NSF). shown in Fig. 1. It consists of a cascade of N identical
The authors are with the Department of Electrical Engineering and Com-
puter Sciences, University of California, Berkeley, CA 94720 USA. stages in which each stage performs a coarse quantization,
IEEE Log Number 9408741. a D/A function on the quantization result, subtraction, and
0018-9200/95$04.00 0 1995 IEEE
CHO AND GRAY PIPELINE A/D CONVERTER 167

V d V d

(a) (b)
Fig. 2. Residue plots (a) ideal (b) with comparator offset AV.

Fig. 1. A 1.5 Wstage pipeline architecture.

plot due to the comparator offset AV is shown. With the use of

digital correction algorithm in 1.5 b/stage pipeline architecture,
amplification of the remainder. A SH function in each stage the overflow of present stage output from the input range of the
allows all stages to operate concurrently, giving a throughput following stage can be prevented even with the presence of a
of one output sample per clock cycle. Fig. 1 illustrates the large comparator offset up to &V,,f/4, so that this offset error
particular configuration of interest here in which the D/A, amplified down the pipeline can be detected for correction.
subtraction, amplification, and SH functions are performed This large error correction range can also eliminate the
by a switched capacitor (SC) circuit, with a resolution of dedicated input SH circuit. Instead, the input signal can be
1.5 b/stage and an interstage gain of 2. The D/A function is sampled simultaneously by the switched capacitor amplifier
performed by two equal capacitors. When the input signal is and by the dynamic comparators of the flash A/D section in
applied, each stage samples and quantizes the signal to its per- the first stage. This is made possible by the fact that digital
stage resolution of 1.5 b [4], [8] (i.e.. 2 decision levels and 3 correction allows comparator errors up to fV,,f/4 without
possible output codes, 00,01, and 10 excluding 1l), subtracts degradation of linearity or SNR. The overall pipeline contains
the quantized analog voltage from the signal by connecting 9 2-b flash quantizers and 8 interstage amplifiers.
the bottom plate of capacitor c s to VDAC(fVref or o), and
passes the residue to the next stage with amplification for m. POWER REDUCTION TECHNIQUES
finer conversion. Then, 1.5 b from all stages are collected
and produce a full 10 b representation of the applied analog In pipeline A/D converters, a major portion of the total
input signal. power dissipation is from the static power dissipated in analog
The resolution of 1.5 bs/stage is chosen in this pipeline circuit components that require dc bias currents, such as
implementationmainly for the following two reasons. The first precision comparators and op amps. The chargingldischarging
reason is to maximize the bandwidth of the SH/Gain SC circuit of sampling capacitors, clock drivers and digital circuits con-
which limits the overall conversion rate. In order to perform tribute a relatively small amount to the overall power dissipa-
fast interstage signal processing, the output of operational tion. Therefore, in this implementation, major effort is taken
amplifier in the SC circuit has to settle in half the clock period to reduce dc power dissipation. One effective method is to use
to the given accuracy of each stage prior to the next stage dynamic comparators to implement the low-resolution flash
sampling instance. Since the bandwidth of the SC interstage A/D section in each stage, since the digital correction can
amplifier depends on its interstage gain, choosing the per-stage relax the comparator accuracy requirements as mentioned in
resolution which allows the low closed-loop gain configuration Section II. In this way, static power dissipation of precision
for fast settling is essential. With the resolution of 1.5 b/stage, comparators can be eliminated. Also, a substantial power
the closed-loop gain of only 2 allows configuration for low reduction can be achieved by using the minimum possible size
load capacitance (composed of only two sampling capacitors of sampling capacitors at each point in the pipeline, as dictated
of the next stage and input capacitance of two comparators by LT/C thermal-noise considerations. This is possible since
in the flash A/D section) and large feedback factor (of about later stages can tolerate more noise due to decreasing stage
1/3), and as a result a large interstage amplifier bandwidth can resolution down the pipeline and therefore can be made small
be achieved compared to that of larger per-stage resolution to reduce power consumption. These design approaches are
(2-3 b/stage). discussed in detail in the following sections.
Also, the resolution of 1.5 b/stage allows large correction
range for comparator offsets in the flash A/D section. Only A. Dynamic Comparators
two comparators are required in the flash A/D section of each In high resolution A/D converters, precision comparators
stage, and the comparator offset up to fV,,f/4 can be tolerated consume dc power since low-offset pre-amp stages are re-
without degradation of the overall linearity or SNR. This is quired to amplify the signal before an accurate comparison
illustrated with residue plots in Fig. 2. Input and output ranges is made. However, in the pipeline architecture, the error
of each stage are both &Kef.Fig. 2(a) shows ideal case with from a large comparator offset in flash A D section of each
zero comparator offsets, and in Fig. 2@), the shifted residue pipeline stage can be easily compensated with digital correc-
I68 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 3, MARCH 1995

the sampling capacitor size ( ( T ; ~ ~ ~k ~

N T /~C~) .,For instance
if the input signal is sampled on a 1 pF capacitor through a
MOS transmission gate, the voltage sampled on the capacitor
contains not only the signal but also the noise voltage whose
rms value is 64 pV at room temperature. Therefore, in this
ideal case, the minimum achievable power dissipation in a
MOS samplehold circuit is set by the maximum allowable
value of this kT/G noise to achieve the required signal-to-
noise-ratio (SNR) before quantization. This sets the minimum
sampling capacitor value, which in turn sets the minimum
Fig. 3. A dynamic comparator with a built-in threshold level. power dissipation for a given sample rate assuming the ca-
pacitor must be completely discharged on each sample period.
tion. As mentioned above, for a 1.5 b per-stage resolution, At room temperature this limit corresponds to about 0.2 pW
the comparator offset up to fVr,f/4 can be corrected. So, per MSis at the 10 b resolution level, assuming the rms thermal
for example, with a reference voltage of 1 V used in the noise is set to cause 1 dB decrease in overall SNR over
prototype, comparator offset up to f 2 5 0 mV can be tolerated. and above that contributed by ADC quantization noise in the
In typical dynamic cross-coupled inverter latches, process ideal case, and that the signal swing is equal to the supply
variations and mismatches can result in large offset voltage but voltage. The required power dissipation quadruples for each
they can still meet this offset requirement easily. So, without additional bit of resolution and is independent of power supply
the use of a pre-amp, simple dynamic latches can implement voltage.
the comparators in the low resolution flash A/D converter to This limit is about four orders of magnitude below the
remove dc power dissipation. dissipation achieved in recently described high-speed A/D con-
One implementation of a dynamic comparator is shown verters. In practice, the SH power is dominated by dissipation
in Fig. 3. Here the lower set of NMOS devices operate in the (usually class A) operational amplifier or buffer that
in the triode region and they are connected to the input drives the sampling capacitor in the sample andor charge
and the reference. As the upper cross-coupled inverter-latch transfer modes. As a practical matter, power minimization in
regenerates when the latch clock goes high, the drain currents the overall A/D converter translates to minimizing the power
of the active switching NMOS devices are steered to obtain a in the active circuitry driving the sampling capacitor whose
final state determined by the mismatch in the total resistance. kT/G noise limits the SNR of the converter.
In this case, resistances (.RI and R2) or conductance (GI = In the pipeline architecture, this again translates into min-
1/R1 and G2 = 1/R2) of NMOS pairs biased in triode region imizing the SC circuit power in each stage. In order to do
are given to the first order by so, the minimum allowable value of sampling capacitor must
be used at each point of pipeline, since it becomes the load
capacitance of the previous stage and the size of the amplifier
is proportional to that of the capacitor for given speed. Thus,
optimization of the power dissipation of each of the operational
amplifier in the pipeline can be performed taking into account
the source, load, and feedback capacitors seen by each one.
(2) Noting that the stage requirements on the speed and accuracy
become less stringent as the stage resolution decreases down
The input voltage which causes G1 equal to G2 is the the pipeline, stages in the later part of the pipeline can be
comparator threshold voltage. From (1) and (2), it is given by scaled down by using smaller sampling capacitors and op
amps. In this case, the sizes of sampling capacitors and op
(3) amps near the front end are determined by the noise floor, and
toward the end of the pipeline, parasitic capacitances begin
where V;, = Vn+ - Kn... and Vref = Kef+ - I & . - . to dominate, and so settling time requirements determine the
Therefore, arbitrary noncritical thresholds can be set by size of each stage.
properly ratioing the triode region device widths, (Wz/W1), In the prototype, the optimization resulted in power dis-
without the use of any sampling capacitors or switches at the sipation ranging from 4.8 mW in the first stage amplifier
input. In this implementation, the required (Wz/Wl)ratio is to 0.5 mW in the last stage amplifier. In Fig. 4, normalized
1/4 to generate comparator threshold levels at fV,,f/4. Of the op amp bias currents of each stage are shown. Through this
35 mW total dissipation in the experimental A/D converter optimization process, the power dissipation can be reduced
operating at 20 MS/s, it is estimated that only 3.5 mW was by about 40-50% relative to the dissipation if all stages are
dissipated in 18 comparators. identical.
One implication of the use of small capacitors in the first
B. Scaling of SC Circuits Through the Pipeline three stages is that the 0.1% matching in the D/A capacitors
A fundamental noise source present in A/D converters is required for 10 b INL will not be achieved in the as-fabricated
thermal noise, and the magnitude of this noise is a function of state. Calibration circuitry has been incorporated into the first
CHO AND GRAY:PIPELINE A/D CONVERTER I69

NCUlUdkd
poav
1.0

0.8

0.6
I I
0.4

02.

0x8

Fig. 4. Scaling of pipeline stages.

1 I I

three stages to remove these mismatch errors [5]. This circuitry k z i

consists of a small T network of trim capacitors around
the input sampling capacitor, and in the prototype, these are Fig. 5. A 3.3 V high-speed high-gain op amp.
adjusted using extemal calibration logic control.
property of the cascode amplifier that the load capacitance is
IV. Low VOLTAGEOPERATION also the compensation capacitance. The low-gain preamplifier
increases the effective gm of the transconductance stage and
For compatibility with low voltage digital IC systems, 3.3
provides necessary dc bias level shifting for the second stage
V supply was chosen for the prototype, and this requires the
input. However, a nondominant pole is introduced due to the
solution of two problems to operate SC circuits at low voltage.
input capacitance of the transconductance stage. In this case,
First, a high-speed 3.3 V op amp with an output swing that is
choosing the optimum value for preamplifier gain is important
a large fraction of the supply voltage, and with large enough
not to waste any achievable bandwidth. For example, if the
voltage gain for the desired resolution, is required. A second
preamplifier gain is too small, the “boosting” effect on the gm
major problem in standard CMOS technologies is the fact that
of the transconductance stage will be sub-optimum. If it’s too
for 3.3-volt supplies, transmission gates produce a high (or
large, then the nondominant pole will be brought down and
infinite) resistance region near the mid-supply voltage due to
limit the bandwidth. Therefore, there will be an optimum value
insufficient gate drive. Solutions to these two problems are
for the preamplifier gain for the given SC configuration which
described next.
achieves minimum settling time.
This configuration was utilized in the prototype, and its
A. High-speed 3.3 V Op Amp circuit diagram is shown in Fig. 5. The optimum value for the
In the pipeline architecture the most stringent requirement preamplifier gain for the given SC configuration was about
on the op amp is on the first stage where dc gain in excess 1.75. In the particular technology used for the prototype, the
of 60 dB and 0.1% settling time under -20 ns are required to output resistance of the PMOS transistor was much worse than
implement an accurate SC SWGain block for 10 b 20 MS/s that of the NMOS transistor for the same bias condition. Thus
operation. In a typical 1.2 pm CMOS technology, designing series feedback gain-boost amplifiers [6] are included in the
such an op amp with power consumption of a few m W s is PMOS current source to provide an adequate voltage gain as
a difficult task. Especially with a 3.3 V supply, it becomes shown in Fig. 6. These amplifiers implemented in differential
more challenging where the triple-cascode op amp structure, configuration are capacitively coupled into the signal path
the simplest way to increase gain while maintaining high speed using level shift capacitors C1 and C2 which are initialized by
as in [3] and [4] cannot be used due to a limited output swing. closing switches SW, and SW2 with transistor A41 connected
while a folded cascode op amp can be used at 3.3 V, its folded to desired input common mode level. The common-mode
implementation requires a slow PMOS transistor in the signal feedback of the main amplifier is also capacitive through C,
path and degrades achievable dc-gain due to reduced output and C,. This is also illustrated in Fig. 6.
resistance at the folding node compared to straightforward Running on a single 3.3 V supply, the first stage amplifier
cascode. To improve the dc-gain, multi-stage configurations achieved a simulated 0.1% settling time of about 17 ns with
with pole-split compensation are attractive, but because of the Cs = CF = 0.39 pF and extemal load of 1.8 pF. Power
nondominate pole resulting from the load capacitance and the dissipation of the first stage op amp is 4.8 mW and from
necessity of driving a compensation capacitor, a substantial experimental results it can be deduced that the voltage gain
degradation in achievable bandwidth and settling time at a is greater than 60 dB. Gain-boost amplifiers are used only for
given power dissipation can result. first three stages, since dc gain requirements in later stages
For 10 b 3.3 V operation, however, another viable solution is are relaxed.
to use a cascode stage with a low-gain, wideband preamplifier In Fig. 10, differential nonlinearity (DNL) and integral non-
to increase the gain by a factor of about 2. While this does linearity (INL)versus input code are plotted. The magnitude
add another stage with its power dissipation, it has only NMOS of the maximum DNL and INL are 0.5 LSB and 0.6 LSB,
transistors in its signal path and preserves the very desirable respectively.
I70 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 30, NO. 3. MARCH 1995

=Rout x AV
vout+
7

Fig. 6. CMFB and gain-boost amplifier.

B. Law Voltage Operation of SC Circuits

In standard CMOS technologies, the threshold voltage of
MOS transistors (typically I-JO.SV/)does not scale with the U I
supply voltage, and it becomes a large portion of the supply
voltage leading to problems when MOS transistors are used
as switches at low voltages. For instance, assuming supply
voltage of 3.3 V, the input signal voltage at the mid-point of (b)
the supply, and threshold voltage of about 1.3 V with body- Fig. 7. (a) A high voltage generator for switches. (b) A bias voltage
effect, the gate voltage overdrive given by (Vgs- & h ) becomes generator for the well of M I to prevent latch-up.
0.35 V ( V , - V , - V h = 3.3V -1.65V -1.3V = 0.35V).In
this case, switch on-resistance can vary by 30-60% if threshold
voltage changes by f100-200 mV with process variations,
resulting in speed degradation of the SC circuits. Although
large transistor switches can be used for the worst case
&h design, the switch parasitic capacitance can significantly
overload the output of SC circuits, especially in later stages
where they are small due, to scaling. Therefore, in order to
solve this problem, increasing (vgs
- & h ) is desirable to
implement low on-resistance MOS switch without adding too
much parasitic capacitance.
There are several possible ways to increase this gate voltage
drive. One method is to reduce by including an extra low-
threshold (-0-0.3 V) transistor in the process. However, this
adds process complexity. Another method is to increase V,,
by using one large 5 V supply created from 3.3 V chip supply
to drive all switches on the chip, but potential problems of
this method include possible crosstalk to some sensitive nodes
through the shared supply and difficulty in estimating the total
charge drain to drive all switches. Another viable solution is to
simply use a dynamic circuit to locally boost the clock drive.
In this case each individual charge pump circuit drives each
Fig. 8. A die photo.
transmission gate or set of transmission gates that use the same
clock to avoid the problem of crosstalk through the clock line.
In the prototype, the last approach is used with the use of a are implemented with only NMOS transistors, and the parasitic
high voltage generator circuit shown in Fig. 7(a). By applying capacitance from PMOS transistors is eliminated. Fig. 7(b)
a square wave input signal of 3.3 V, C1 and Cz are self- shows the bias voltage generator for the n-well of the PMOS
charged to 3.3 V through the cross-coupled NMOS transistors transistor MI! which has been designed to prevent latch
[7], and an inverted square wave output of (5 V is generated up during the initial power-up transient. Reliability is not a
according to concern here since 5-volt-capable technology is used at 3.3 V.
c 2
vht = 2Vdd (4)
'
Cgate,Mz + CZ+ Cparasitic ' V. EXPERIMENTAL
RESULTS
where C g a t e , ~ 2is the gate capacitance of transistor M,. A prototype A D converter based on the above architecture
Because this gate voltage overdrive is much higher than the was fabricated in a double-poly double-metal 1.2-pm CMOS
signal common-mode voltage ( x V & / ~ )sampling
, switches technology. It consists of 8 pipelined stages and one flash
CHO AND GRAY PIPELINE A D CONVERTER 171

SNDR (a) 1.0 I I I

60 A 09 #r
os f
55 0.7 r
50
/ Y
0.6 I
45

48 I input-referred
II
35
30
25
ZI
40 -30 -m -10 0
I.p( (dm
Fig. 11. Measured probability of getting a code i versus the dc input voltage.
Fig. 9. SNDR versus the input amplitude.

Porero
WB)
1.0
0.5 I 1
0.0
4.5 . .I ... ..,,, .,., . . _
I
-1.0 1
0 d e lo00

1 2 5 10 20

Fig. 12. Power versus the sampling frequency.

TABLE I
0.0 A/D PERFORMANCE: 3.3 V AND 25OC

-0.5

powcrDissipation 35mW'
0.5 LSB
0.6 LSB
A/D section in the end. Capacitors in the first three stages are SNDR 59.1 dB (F5m= 100 IrHz)
55.0 dB F m = 10 ME?)
calibrated with trim capacitor arrays to achieve high accuracy.
A die photo is shown in Fig. 8. Clock lines are routed in the * Output p d driverpowa unnrmptionnot incloded.
middle, and the analog signal path is folded around to make
the chip area square. Op amp bias circuits are shared between
several op amps, and all bias currents are controlled by one about 20 mW. At a reduced bias current and a sampling
frequency of 1 MSIs, the power consumption was 2.8 mW
external master bias current. Chip area not including the pad
ring is 3.2 x 3.3 mm2. with peak SNDR of 58 dB.
Fig. 9 shows SNDR versus the input amplitude for 100 kHz
and 10 MHz input frequencies at 20-MS/s conversion rate. VI. S m Y
The peak SNDR is 59.1 dB for 100 kHz input sine wave. At This paper describes a 10 b, 20 MSIs, 35 mW pipeline N D
Nyquist sampling (10 MHz input), the SNDR is 55.0 dB. converter in 1.2 pm CMOS technology, and its performance is
Fig. 11 shows the probability of getting a code i versus the summarized in Table I. The key features of this converter are:
dc input voltage near the code transition. The extracted total the usage of dynamic comparators and careful scaling of SC
input-referred RMS noise voltage from this plot was -220 pV circuits down the pipeline to achieve low power dissipation,
while the designed value was 216 pV. This confirms the RT/C and new low voltage op amps and charge pump circuits to
noise-limited design in the prototype. implement SC circuits for low voltage operation of pipeline
Fig. 12 shows the measured power consumption versus the stages. This shows that low voltage, low power operation
sampling frequency on a log-log scale. Of 35 mW of total of pipeline A/D converters can be achieved for video-rate
power dissipation at 20 MSIs, static power consumption was applications.
172 IEEE JOURNAL OF SOLlD-STATE CIRCUITS, VOL. 30, NO. 3, MARCH 1995

REFERENCES Paul R. Gray (S’65-M’69-SM’76-F’81) was born

in Jonesboro, AR, on December 8, 1942. He
K. Kusumoto et al., “A IO-b 20-MHz 30” pipelined interpolating received the B.S., M.S., and Ph.D. degrees from
CMOS ADC,” in ISSCC Dig. Tech. Pap., Feb. 1993, pp. 62-63. the University of Arizona, Tucson, in 1963, 1965,
M. Ito et al., “A 10-b 20-Mds 3 V-supply CMOS An> converter for and 1969, respectively.
integration into system VLSIs,” in ISSCC Dig. Tech. Pap., Feb. 1994, In 1969 he joined the Research and Development
pp. 48-49. Laboratory, Fairchild Semiconductor, Palo Alto,
[31 T. Matsuura er al., “A 95-mW, 10-b 1.5-MHz low-power CMOS ADC CA, where he was involved in the application of
using analog double-sampled pipelining scheme,” in VLSI Symp. Dig. new technologies for analog integrated circuits,
Tech. Pap., 1992, pp. 98-99. including power integrated circuits and ‘data con-
[41 S. H. Lewis et al., “10-b 20-Msamplds analog-to-digital converter,” version circuits. In 1971 he joined the Department
IEEE J. Solid-State Circuits, vol. 27, pp. 351-358, Mar. 1992. of Electrical Engineering and Computer Sciences, University of California,
151 Y. M. Lin, B. Kim, and P. R. Gray, “A 13-b 2.5 MHz self-calibrated Berkeley, where he is now a Professor. His research interests during this period
pipelined A/D converter in 3-pm CMOS,” IEEE J. SoIid-Stare Circuits, have included bipolar and MOS circuit design, electro-thermal interactions in
vol. 26, pp. 628-636, Apr. 1991. integrated circuits, device modelling, telecommunications circuits, and analog-
K. Bult and G . J. G . M. Geelen, “A fast-settling CMOS opamp with 90- digital interfaces in VLSI systems. He is the co-author of a widely used college
dB dc gain and 116 MHz unity-gain frequency,” in ISSCC Dig. Tech. textbook on analog integrated circuits. During year-long industrial leaves of
Pap., Feb. 1990, pp. 108-109. absence from Berkeley, he served as Project Manager for Telecommunications
[71 Y . Nakagome et al., “Experimental 1.5-V 64-Mb DRAM,” IEEE J. Filters at Intel Corporation, Santa Clara, CA during 1977-1978, and as
Solid-Sfafe Circuits, vol. 26, pp. 465472, Apr. 1991. Director of CMOS Design Engineering at Microlinear Corporation, San Jose
181 G . Jusuf, “A I-bitkycle algorithmic analog-to-digital converter without
CA, during 1984-1985. At Berkeley he has held several administrative posts
high-precision comparators,” Electron. Res. Lab., Univ. of California.
including Director of the Electronics Research Laboratory (1985-1986). Vice-
Berkeley, Memo. UCBERL M90/69, Aug. 1990. Chairman of the EECS Department for Computer Resources (1988-1990), and
Chairman of the Department of Electrical Engineering and Computer Sciences
(1990-1993). He currently holds the Edgar R. and Harold H. Buttner Chair
in Electrical Engineering at Berkeley.
Thomas Byunghak Cho (S’90) was born in Seoul, Dr. Gray has been co-recipient of best-paper awards at the International
Korea on March 27, 1967. He received the B.S. Solid State Circuits Conference, the European Solid-state Circuits Conference,
degree in electrical engineering from the University and was co-recipient of the IEEE R. W. G Baker Prize in 1980, the IEEE
of California, Los Angeles in 1989, and the M.S. Moms K. Liebman Award in 1983, and the IEEE Circuits and Systems Society
degree in electrical engineering from the University Achievement Award in 1987. In 1994 he received the IEEE Solid-state
of California, Berkeley in 1991. Circuits Award. He served as Editor of the IEEE JOURNAL OF SOLID-STATE
He is currently a Ph.D. candidate in electrical CIRCUITSfrom 1977 through 1979, and a Program Chairman of the 1982
engineering at Berkeley and his research interests International Solid State Circuits Conference. He served as President of the
include mixed signal IC design for high-speed data IEEE Solid-state Circuits Council from 1988 to 1990. He is a member of
acquisition and telecommunication applications. the National Academy of Engineering.
Mr. Cho is a member of Eta Kappa Nu.