Module 2

Introduction
 Algorithm – solution to any problem that is stated
by a finite number of well-defined procedural
steps.
 Algorithms for addition, subtraction, multiplication
and division
 Fixed point binary data in signed magnitude
representation
 Fixed point binary data in signed 2’s complement
representation
 Floating point binary data
Signed Numbers
Need to be able to represent both positive and negative numbers

- Following 3 representations

Signed magnitude representation

Signed 1's complement representation
Signed 2's complement representation

Example: Represent +9 and -9 in 7 bit-binary number

Only one way to represent +9 ==> 0 001001

Three different ways to represent -9:
In signed-magnitude: 1 001001
In signed-1's complement: 1 110110
In signed-2's complement: 1 110111

In general, in computers, fixed point numbers are represented

either integer part only or fractional part only.
Pros and cons of integer representation
 Signed magnitude representation:
 2 representations for 0
 Simple
 255 different numbers can be represented.
 Need to consider both sign and magnitude in arithmetic
 Different logic for addition and subtraction
 1’s complement representation:
 2 representations for 0
 Complexity in performing addition and subtraction
 255 different numbers can be represented.
 2’s complement representation:
 Only one representation for 0
 256 different numbers can be represented.
 Arithmetic works easily
 Negating is fairly easy
Overflow
 Overflow in unsigned addition – result occupies
more number of bits.
 Overflow in signed-magnitude / 2’s complement
addition – result occupies more number of bits /
addition of two positive number resulting negative
number and sum of two negative numbers
resulting in positive number.
 There will no overflow during unsigned
subtraction / signed – magnitude subtraction.
 Overflow bit in 2’s complement subtraction is
ignored.
2’s complement subtraction
 Represent negative numbers in 2’s complement
form
 Subtract the given two numbers
 Take 2’s complement of subtrahend (second number)
and add to the minuend (first number)
 If carry
 Discard it
 Answer is positive
 Else
 Answer is negative
 So, answer is in 2’s complement form
Overflow / Underflow Problem
 Addition and bit-size restriction allow for possible
overflow / underflow
 Overflow – when the addition of two binary numbers
yields a result that is greater than the maximum
possible value
 Underflow – when the addition/subtraction of two
binary numbers yields a result that is less than the
minimum possible value
Overflow Example
 Assume 4-bit restriction and 2’s complement
 Maximum possible value: 24-1 – 1 = 7

610 + 310 = 910

01102 610
+00112 +310
10012 -710  not good!
Underflow Example
 Assume 4-bit restriction and 2’s complement
 Minimum possible value: -(24-1) = -8

-510 + -510 = -1010

10112 -510
+10112 +-510
01102 610  not good!
Signed Overflow
carry and overflow
carry generated, but no overflow

no carry and overflow

no carry and no overflow
Addition/subtraction of signed numbers
xi yi Carry-in ci Sumsi Carry-out ci +1
At the ith stage:
0 0 0 0 0 Input:
0 0 1 1 0 ci is the carry-in
0 1 0 1 0
0 1 1 0 1
Output:
1 0 0 1 0 si is the sum
1 0 1 0 1 ci+1 carry-out to (i+1)st
1 1 0 0 1
1 1 1 1 1
state

si = xi yi ci + xi yi ci + xi yi ci + xi yi ci = x i  yi  ci
ci +1 = yi ci + xi ci + xi yi

Example:

X 7 0 1 1 1 Carry-out xi Carry-in
+Y = +6 = + 00 1 1 1 1 0 0 0 yi
ci+1 ci
Z 13 1 1 0 1 si

Legend for stage i

Addition logic for a single stage
Sum Carry
yi
c
i
xi
xi
yi si c
c i +1
i
ci
x
xi yi i
yi

ci + 1 Full adder ci
(FA)

s
i

Full Adder (FA): Symbol for the complete circuit

for a single stage of addition.
n-bit adder
•Cascade n full adder (FA) blocks to form a n-bit adder.
•Carries propagate or ripple through this cascade, n-bit ripple carry adder.

xn - 1 yn - 1 x1 y1 x0 y0

cn - 1 c1
cn FA FA FA c0

sn - 1 s1 s0
Most significant bit Least significant bit
(MSB) position (LSB) position

Carry-in c0 into the LSB position provides a convenient way to

perform subtraction.
K n-bit adder
K n-bit numbers can be added by cascading k n-bit adders.

xk n - 1 yk n - 1 x2n - 1 y2n - 1 xn y n xn - 1 y n - 1 x 0 y 0

cn
n-bit n-bit n-bit c
c kn 0
adder adder adder

s s( s s s s
kn - 1 k - 1) n 2n - 1 n n- 1 0

Each n-bit adder forms a block, so this is cascading of blocks.

Carries ripple or propagate through blocks, Blocked Ripple Carry Adder
n-bit subtractor
•Recall X – Y is equivalent to adding 2’s complement of Y to X.
•2’s complement is equivalent to 1’s complement + 1.
•X – Y = X + Y + 1
•2’s complement of positive and negative numbers is computed similarly.

xn - 1 yn - 1 x1 y1 x0 y0

cn - 1 c1
cn FA FA FA 1

sn - 1 s1 s0
Most significant bit Least significant bit
(MSB) position (LSB) position
n-bit adder/subtractor (contd..)
y y y
n- 1 1 0
Add/Sub
control

x x x
n- 1 1 0

c n-bit adder
n c
0

s s s
n- 1 1 0

•Add/sub control = 0, addition.

•Add/sub control = 1, subtraction.
Detecting overflows
 Overflows can only occur when the sign of the two operands is
the same.
 Overflow occurs if the sign of the result is different from the
sign of the operands.
 Recall that the MSB represents the sign.
 xn-1, yn-1, sn-1 represent the sign of operand x, operand y and result s
respectively.
 Circuit to detect overflow can be implemented by the
following logic expressions:

Overflow  xn1 yn1sn1  xn 1 yn 1sn 1

Overflow  cn  cn1
Computing the add time
x0 y0
Consider 0th stage:
•c1 is available after 2 gate delays.
•s1 is available after 1 gate delay.
c1 FA c0

s0

Sum Carry
yi
c
i
xi
xi
yi si c
c i +1
i
ci
x
i
yi
Computing the add time (contd..)
Cascade of 4 Full Adders, or a 4-bit adder

x0 y0 x0 y0 x0 y0 x0 y0

FA FA FA FA c0
c4 c3 c2 c1

s3 s2 s1 s0

•s0 available after 1 gate delays, c1 available after 2 gate delays.

•s1 available after 3 gate delays, c2 available after 4 gate delays.
•s2 available after 5 gate delays, c3 available after 6 gate delays.
•s3 available after 7 gate delays, c4 available after 8 gate delays.

For an n-bit adder, sn-1 is available after 2n-1 gate delays

cn is available after 2n gate delays.
Fast addition
Recall the equations:

Second equation can be written as:

ci 1  xi yi  ( xi  yi )ci
We can write:
ci 1  Gi  Pi ci
where Gi  xi yi and Pi  xi  yi

•Gi is called generate function and Pi is called propagate function

•Gi and Pi are computed only from xi and yi and not ci, thus they can
be computed in one gate delay after X and Y are applied to the
inputs of an n-bit adder.
Carry lookahead
ci 1  Gi  Pi ci
ci  Gi 1  Pi 1ci 1
 ci1  Gi  Pi (Gi 1  Pi 1ci 1 )
continuing
 ci1  Gi  Pi (Gi 1  Pi 1 (Gi  2  Pi 2 ci 2 ))
until
ci1  Gi  PiGi 1  Pi Pi1 Gi 2  ..  Pi Pi 1 ..P1G0  Pi Pi 1 ...P0 c 0
•All carries can be obtained 3 gate delays after X, Y and c0 are applied.
-One gate delay for Pi and Gi
-Two gate delays in the AND-OR circuit for ci+1
•All sums can be obtained 1 gate delay after the carries are computed.
•Independent of n, n-bit addition requires only 4 gate delays.
•This is called Carry Lookahead adder.
Multiplication of unsigned numbers

Product of 2 n-bit numbers is at most a 2n-bit number.

Unsigned multiplication can be viewed as addition of shifted
versions of the multiplicand.
 Multiplication of unsigned
numbers (contd..)
 We added the partial products at end.
 Alternative would be to add the partial products at each stage.

 Rules to implement multiplication are:

 If the ith bit of the multiplier is 1, shift the multiplicand and add the
shifted multiplicand to the current value of the partial product.
 Hand over the partial product to the next stage
 Value of the partial product at the start stage is 0.
Multiplication of unsigned numbers
Typical multiplication cell

Bit of incoming partial product (PPi)

jth multiplicand bit

ith multiplier bit ith multiplier bit

carry out FA carry in

Bit of outgoing partial product (PP(i+1))

Combinatorial array multiplierCombinatorial array multiplier

Multiplicand
0 m3 0 m2 0 m1 0 m0
(PP0)
q0
0
PP1 p0
q1
0
PP2 p1
q2
0
PP3 p2
q3
0
,
p7 p6 p5 p4 p3

Product is: p7,p6,..p0

Multiplicand is shifted by displacing it through an array of adders.

Combinatorial array multiplier
(contd..)
 Combinatorial array multipliers are:
 Extremely inefficient.
 Have a high gate count for multiplying numbers of practical size such as 32-
bit or 64-bit numbers.
 Perform only one function, namely, unsigned integer product.

 Improve gate efficiency by using a mixture of

combinatorial array techniques and sequential
techniques requiring less combinational logic.
Sequential multiplication
 Recall the rule for generating partial products:
 If the ith bit of the multiplier is 1, add the appropriately shifted multiplicand
to the current partial product.
 Multiplicand has been shifted left when added to the partial product.

 However, adding a left-shifted multiplicand to an

unshifted partial product is equivalent to adding an
unshifted multiplicand to a right-shifted partial
product.
Sequential Circuit Multiplier
Register A (initially 0)

Shift right

C a a q q
n - 1 0 n - 1 0

Multiplier Q
Add/Noadd
control

n-bit
Adder
MUX Control
sequencer

0 0

m m
n - 1 0

Multiplicand M
Sequential multiplication (contd..)
M
1 1 0 1
Initial configuration
0 0 0 0 0 1 0 1 1
C A Q
0 1 1 0 1 1 0 1 1 Add
Shift First cycle
0 0 1 1 0 1 1 0 1

1 0 0 1 1 1 1 0 1 Add
Shift Second cycle
0 1 0 0 1 1 1 1 0

0 1 0 0 1 1 1 1 0 No add
Shift Third cycle
0 0 1 0 0 1 1 1 1

1 0 0 0 1 1 1 1 1 Add
Shift Fourth cycle
0 1 0 0 0 1 1 1 1

Product
Signed Multiplication
 Considering 2’s-complement signed operands, what will happen to (-
13)(+11) if following the same method of unsigned multiplication?

1 0 0 1 1 ( - 13)
0 1 0 1 1 ( + 11)

1 1 1 1 1 1 0 0 1 1

1 1 1 1 1 0 0 1 1
Sign extension is
shown in blue 0 0 0 0 0 0 0 0

1 1 1 0 0 1 1

0 0 0 0 0 0

1 1 0 1 1 1 0 0 0 1 ( - 143)

Sign extension of negative multiplicand.

Signed Multiplication
 For a negative multiplier, a straightforward solution is
to form the 2’s-complement of both the multiplier and
the multiplicand and proceed as in the case of a
positive multiplier.
 This is possible because complementation of both
operands does not change the value or the sign of the
product.
 A technique that works equally well for both negative
and positive multipliers – Booth algorithm.
Booth Algorithm
 Consider in a multiplication, the multiplier is positive
0011110, how many appropriately shifted versions of
the multiplicand are added in a standard procedure?

0 1 0 1 1 0 1
0 0 +1 +1 + 1+1 0
0 0 0 0 0 0 0
0 1 0 1 1 0 1
0 1 0 1 1 0 1
0 1 0 1 1 0 1
0 1 0 1 1 0 1
0 0 0 0 0 0 0
0 0 0 0 0 0 0
0 0 0 1 0 1 0 1 0 0 0 1 1 0
Booth Algorithm
Multiplier
Version of multiplicand
selected by biti
Bit i Bit i -1

0 0 0 XM
0 1 +1 XM
1 0 1 XM
1 1 0 XM

Booth multiplier recoding table.

Booth Algorithm
 In general, in the Booth scheme, -1 times the shifted multiplicand is
selected when moving from 0 to 1, and +1 times the shifted
multiplicand is selected when moving from 1 to 0, as the multiplier
is scanned from right to left. Ex:
0 0 1 0 1 1 0 0 1 1 1 0 1 0 1 1 0 0

0 +1 -1 +1 0 - 1 0 +1 0 0 - 1 +1 - 1 + 1 0 - 1 0 0

Booth recoding of a multiplier.

Booth Algorithm
0 1 1 0 1 ( + 13) 0 1 1 0 1
X1 1 0 1 0 (- 6) 0 - 1 +1 - 1 0
0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 0 0 1 1
0 0 0 0 1 1 0 1
1 1 1 0 0 1 1
0 0 0 0 0 0
1 1 1 0 1 1 0 0 1 0 ( - 78)

Booth multiplication with a negative multiplier.

Booth Algorithm
 Best case – a long string of 1’s (skipping over 1s)
 Worst case – 0’s and 1’s are alternating
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Worst-case
multiplier
+1 - 1 +1 - 1 +1 - 1 +1 - 1 +1 - 1 +1 - 1 +1 - 1 +1 - 1

1 1 0 0 0 1 0 1 1 0 1 1 1 1 0 0
Ordinary
multiplier
0 -1 0 0 +1 - 1 +1 0 - 1 +1 0 0 0 -1 0 0

0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1
Good
multiplier
0 0 0 +1 0 0 0 0 -1 0 0 0 +1 0 0 -1
 Refer to Booth algorithm and Modified booth algorithm
illustration
Manual Division
21 10101
13 274 1101 100010010
26 1101
14 10000
13 1101
1 1110
1101
1

Longhand division examples.

Simple Integer Division: Pencil-Paper Method

Let,
Dividend, D=1001011
Divisor, M=1000
Longhand Division Steps
 Position the divisor appropriately with respect to the
dividend and performs a subtraction.
 If the remainder is zero or positive, a quotient bit of 1
is determined, the remainder is extended by another
bit of the dividend, the divisor is repositioned, and
another subtraction is performed.
 If the remainder is negative, a quotient bit of 0 is
determined, the dividend is restored by adding back
the divisor, and the divisor is repositioned for another
subtraction.
 Fixed Point Division

C =a/b;  Restoring Division

 Non-Restoring Division
Circuit Arrangement
Shift left

an an-1 a0 qn-1 q0
Dividend Q
A Quotient
Setting

N+1 bit Add/Subtract

adder
Control
Sequencer

0 mn-1 m0

Divisor M

Figure 6.21. Circuit arrangement for binary division.

Restoring Division
 Shift A and Q left one binary position
 Subtract M from A, and place the answer back in A
 If the sign of A is 1, set q0 to 0 and add M back to A
(restore A); otherwise, set q0 to 1
 Repeat these steps n times
Flow chart representation
Examples Initially 0

Shift
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1 0 0 0

0 0 0
Subtract 1 1 1 0 1 First cycle
Set q0 1 1 1 1 0
Restore 1 1
0 0 0 0 1 0 0 0 0
10 Shift 0 0 0 1 0 0 0 0
11 1000 Subtract 1 1 1 0 1
11 Set q0 1 1 1 1 1 Second cycle
Restore 1 1
10 0 0 0 1 0 0 0 0 0
Shift 0 0 1 0 0 0 0 0
Subtract 1 1 1 0 1
Set q0 0 0 0 0 1 Third cycle

Shift 0 0 0 1 0 0 0 0 1
Subtract 1 1 1 0 1 0 0 1
Set q0 1 1 1 1 1 Fourth cycle
Restore 1 1
0 0 0 1 0 0 0 1 0

Remainder Quotient

Figure 6.22. A restoring-division example.

Q=7=0111
M=3=0011

Solution:
Quotient =0010=2
Remainder=0001=1
Non-restoring Division
Modifying the basic division algorithm by eliminating restoring step
is non-restoring division

Algorithm
1. Start by initializing register A to 0 and repeat steps (2-4) n times
2. If A is positive,
2.1 Shift A and Q left by one bit position
2.2 Subtract M from A
3. If A is negative
3.1 Shift A and Q left by one bit position
3.2 Add M to A
4. If A is positive, set Q0 to 1, else Q0 to 0
5. If A is negative, add M to A as a final corrective step
Non-Restoring Division
Flowchart
 Examples Initially

Shift
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1 0 0 0

0 0 0 First cycle
Subtract 1 1 1 0 1
Set q0 1 1 1 1 0 0 0 0 0

Shift 1 1 1 0 0 0 0 0
Add 0 0 0 1 1 Second cycle

Set q 1 1 1 1 1 0 0 0 0
0

Shift 1 1 1 1 0 0 0 0
1 1 1 1 1 Add 0 0 0 1 1 Third cycle
Restore
0 0 0 1 1 Set q 0 0 0 0 1 0 0 0 1
remainder 0
Add 0 0 0 1 0
Remainder Shift 0 0 0 1 0 0 0 1
Subtract 1 1 1 0 1 Fourth cycle
Set q 1 1 1 1 1 0 0 1 0
0

Quotient
A nonrestoring-division example.
Q=7=0111
M=3=0011

Solution:
Quotient =0010=2
Remainder=0001=1
Floating Point Numbers : Scientific Notation

We use scientific notation to represent fraction/floating point

numbers. It has single digit to the left of decimal point.

A number 0.000000001ten can be represented as 1.0ten x 10–9

Small number:
Mass of neutron=1.67 x 10-27 kg
Seconds in nanosecond=1.0 x 10-9 s

Large number:
Mass of earth=5.92 x 1024 kg
Seconds in a century=3.16 x 109 s
Nanoseconds in a day=8.64 x 1013 ns
Scientific notation
Fixed point representation suffers from a drawback that the representation can
only represent a finite range (and quite small) range of numbers.

A more convenient representation is the scientific representation, where

the numbers are represented in the form:

x  m1.m2m3m4  b e

Components of these numbers are:

Mantissa (m), implied base (b), and exponent (e)

A sample representation
1 7 24

Sign Exponent Fractional mantissa

bit
•24-bit mantissa with an implied binary point to the immediate left
•7-bit exponent in 2’s complement form, and implied base is 2.
Floating Point Representation: IEEE 754 Standard

A floating point number is represented using three fields: sign bit,

exponent and fraction field
IEEE 754 Floating Point Standard Cntd…

Possibility : numbers(large)
IEEE 754 Floating Point Standard Cntd…

Underflow or overflow problems: solved using exponent(larger)

The following is IEEE 754 double precision floating point format.

This floating point number takes two 32-bit word. S is single bit sign,
11-bits exponent field, 52-bits fraction field.
Floating Point Numbers :Normalized Scientific Notation
The procedure for normalizing a floating point number is:
Do (until MSB of mantissa = = 1)
Shift the mantissa left (or right)
Decrement (increment) the exponent by 1
end do
Biased Exponent Representation

IEEE 754 : exponent -biased representation

For single precision, IEEE 754 uses a bias of 127.

So -1 is represented as -1+127=12610= 0111 11102(Exponent)

+1 is represented as 1+127=12810= 1000 00002
In general, excess-p coding is represented as:
E’ = Etrue + p

For double precision, IEEE 754 uses a bias of 1023.

Exercise 1:
0.75 * 2 = 1.50  (1)
0.5 * 2 =1.00  (1)

So, -0.7510  (-0.11) * 20

Exercise 2:
Exercise 3: Find the decimal value for the
given IEEE 754 binary representation
Floating Point Addition
Question: Add 0.510 and –0.437510 in binary.
Floating Point Multiplication
Floating point arithmetic: DIV rule
 Subtract the exponents
 Add the bias.
 Divide the mantissas and determine the sign of the result.
 Normalize the result if necessary.
 Truncate/round the mantissa of the result.

Note: Multiplication and division does not require alignment of the

mantissas the way addition and subtraction does.
 Guard bits
• While adding two floating point numbers with 24-bit mantissas, we shift
the mantissa of the number with the smaller exponent to the right until
the two exponents are equalized.
• This implies that mantissa bits may be lost during the right shift (that is,
bits of precision may be shifted out of the mantissa being shifted).
• To prevent this, floating point operations are implemented by keeping
guard bits, that is, extra bits of precision at the least significant end
of the mantissa.
• The arithmetic on the mantissas is performed with these extra bits of
precision.
• After an arithmetic operation, the guarded mantissas are:
- Normalized (if necessary)
- Converted back by a process called truncation/rounding to a 24-bit mantissa.
Truncation/rounding
 Straight chopping:
 The guard bits (excess bits of precision) are dropped.

 Von Neumann rounding:

 If the guard bits are all 0, they are dropped.
 However, if any bit of the guard bit is a 1, then the LSB of the retained bit is
set to 1.
 Rounding:
 If there is a 1 in the MSB of the guard bit then a 1 is added to the LSB of the
retained bits.
Rounding
 Rounding is evidently the most accurate truncation
method.
 However,
 Rounding requires an addition operation.
 Rounding may require a renormalization, if the addition operation de-
normalizes the truncated number.

 IEEE uses the rounding method.