Operational Amplifiers

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-1 郭泰豪, Analog IC Design, 2018
 Operational Amplifiers
 Ideal voltage op-amp
 Voltage-controlled voltage source
+
 Infinite voltage gain va
+
 Infinite input impedance vb - A(va-vb) vo
 Zero output impedance
 No noise
-
 Infinite bandwidth
 No offset voltage
 Infinite CMRR

 Differences between the ideal op-amp and real op-amp

 Finite gain (practical op-amps, A≈102~104, i.e., 40~80dB)
 Finite linear range(VDD>Vo>GND)

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-2 郭泰豪, Analog IC Design, 2018
 Operational Amplifiers (Cont.)
 Offset voltage:
 Ideal op-amps Va=Vb ⇨ Vo=0
 Real op-amps
This is not exactly true and Vo≠0 is always occurred.
 Input offset voltage V is defined as the differential input voltage
needed to restore Vo=0.
 For MOS op-amps, Voffset is about 5-15 mV.
For BJT op-amps, Voffset is about 1-2 mV.

 Common Mode Rejection Ratio(CMRR)

 The CMRR measure how much the op-amp can suppress
common-mode signal at its input.
 Typically CMRR=60~80dB common-mode input voltage:
Vin,c=(Va+Vb)/2

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-3 郭泰豪, Analog IC Design, 2018
 Operational Amplifiers (Cont.)
differential-mode input voltage : Vin,d = Va – Vb
Vo
differential gain A d 
Vin ,d
V
common-mode gain A c  o
Vin ,c
CMRR=(Ad/Ac) or 20log10(Ad/Ac) in dB
+ Va +
+ A +
- Vb -
Vin,c + vo vo
-

- -
common-mode input differential-mode input

 Frequency Response:
 Limited bandwidth(10GHz unity-gain bandwidth is typical)
 Gain decreases at high frequency, because
○ Stray capacitances
○ Finite carrier mobilities
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-4 郭泰豪, Analog IC Design, 2018
 Operational Amplifiers (Cont.)
 Slew Rate (typically, for MOS op-amps, 1~50V/μs)
 The maximum rate of output change dVo/dt
 For a large input voltage, some transistors may be driven out of
their saturation regions or completely cut off. As a result, the
output will follow the input at a slower finite rate.
 Nonzero Output Resistance
 0.1~5kΩ → typical value
 Large R will limit frequency response(i.e., speed) when a
capacitor is connected to its output.
 Noise
 Noisy transistors in op-amps give rise to a noise voltage Von at
the output of op-amp.
 Equivalent input noise voltage=Von/A=Vn -
+
Vn

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-5 郭泰豪, Analog IC Design, 2018
 Operational Amplifiers (Cont.)
Vin ,max
 Dynamic Range(DR) = 20 log10 ( )
Vin ,min
 Open loop~30-40dB

Vin ,min  Vn ~ 30V

2

Vdd
Vin ,max 
A
 Close loop~100dB has larger DR than open loop.
 Can be increased by using correlated double sampling (CDS)
 PSRR (Power supply rejection ratio)
Ad
 PSRR+= 20 log10 (  ) V1
A - A+V1+A-V2
Ad
 PSRR = - 20 log10 ( 
) +
A
V2
 DC Power Dissipation(10μW~100μW)

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-6 郭泰豪, Analog IC Design, 2018
 CMOS Amplifier with Resistive Load
 Resistor Load IDS
A  g m R o //ro 
Ro Large R o
 gmR o
I R Vout
 D o ro
Vov Vin
Small R o
VDS
 For high gain
 High IDRo
 High IDRo means large voltage drop on Ro
 Large power supply
 High Ro reduces speed
 Use active loads to overcome the above problems.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-7 郭泰豪, Analog IC Design, 2018
 CMOS Amplifier with Active Load
 With external bias

M3 M4 IDS(M1, M3)
Vbias2
Vo- M3 M1
Vo Vo+

Vin+ Vin-
load line
M1 M2
 large rO 
Vbias1 M5

GND VDS(M1, M3)

 Why not?
 Quiescent point of Vo+ and Vo-
can’t be determined due to process variations

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-8 郭泰豪, Analog IC Design, 2018
 CMOS Amplifier with Active Load (Cont.)
 Self-biased active load, where quiescent Vo less sensitive to I ds3,4 variations
 Performs differential gain and differential to single-ended
 Differential gain Adm
1
g m,M 1,g m,M 2 ,g m,M 3 ,g m,M 4   Model of Acm
rds
VDD
rout  rds 2 //rds 4 1 v1  1  M3 M4
 // rds1 // rds3 
Adm  g m1 rds 2 //rds 4  2 rds 0  g m 3 
Vo
 Common-mode gain Acm A B

v1 v1
1 1  1  1 M1 M2
Acm   // rds1 // rds 3  
C

2 rds 0  g m3  2 g m3rds 0 Vi1 v1 v1 Vi2

rds 0
 CMRR(Common-Mode Rejection Ratio) rds0 Io

CMRR  dm  2 g m1 rds 2 // rds 4 g m 3 rds 0

A GND
Acm

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-9 郭泰豪, Analog IC Design, 2018
 Uncompensated CMOS OPAMP
 Basic building blocks of an operational amplifier
Vin-
-
G1 G2 Vout
Vin+ +

Differential stage Single-ended

+ gain-stage
Differential-to-single-ended converter

VDD

M5 M7
M1 M2
Vin- Vin+ I2
I1 B
A
M6 C
L
M3 M4 C1 Vout

GND

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-10 郭泰豪, Analog IC Design, 2018
 Uncompensated CMOS OPAMP (Cont.)
A V1  g m1R o1  g m1 rds 4 // rds 2 
A V 2  g m 6 R o 2  g m 6 rds 6 // rds 7 
where Ro1 is low frequency output impedance of node A
Ro2 is low frequency output impedance of node B
CA(CB) is capacitive loading at node A(B)

 Block diagram showing the origin of the dominant poles

Vin- Ro1 Ro2
- A B Vout
G1
Vin+ +
Input CA CB
Second
Stage Stage

Vi Vo 1
Vo (s) sCA 1
CA   
Vi (s) R  1 1  sR o1C A
o1
sCA

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-11 郭泰豪, Analog IC Design, 2018
 Uncompensated CMOS OPAMP (Cont.)

1 1
Vout (s) sCA sCB
A V (s)   
 A v ( 0)
Vin (s)  Vin (s) R o1 
1
R o2 
1
sCA sCB
1 1 1
 A v ( 0) ; SA  ; SB 
s s R o1C A R o 2C B
(1  )(1  )
SA SB

 SA and SB are dominant poles since Ro1 and Ro2 are normally large.

 The effects of other poles are usually negligible.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-12 郭泰豪, Analog IC Design, 2018
 Uncompensated Two-Stage CMOS OPAMP
A0 VDD
A(s) 
(1  s ω P1 )(1 s ω P2 ) M8 M5 M7
A 0  g m1R 01g m 6 R 02
g m1  2 μCox (W L) M1 I1
 
I2
g m 6  2 μCox (W L) M6 I 2 M1 I1 M2
Iref 
R 01  rds2 //rds4 M3 M4 M6
C1 Vo
R 02  rds6 //rds7 CL

ωP1  1 R 01C1 GND
ωP2  1 R 02C L
  
vid g m1vid R 01 vA C1 g m6vA R 02 C L Vo
  

 P1 & P2 are dominant poles since R01 and R02 are normally large.
The effects of other poles are usually negligible.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-13 郭泰豪, Analog IC Design, 2018
 Uncompensated CMOS OPAMP (Cont.)
 For low frequency, A ( j)  A V (0)
g g
For high frequency, A( j)   2m1 m 5
 C1C L
For high frequency, the amplifier inverts the input voltage. If feedback is
used, then positive feedback occurs.

 Two dominant poles

 Phase margin is not large enough
 Pole-splitting technique to solve this problem

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-14 郭泰豪, Analog IC Design, 2018
 Pole-Splitting of Two-Stage CMOS OPAMP
 Reduce ωP1 and increase ωP2 A 0 (1  s ω Z )
A(s) 
VDD
(1  s ω P1 )(1 s ω P2 )
M5 M7 A 0  g m1R 01g m 6 R 02
g m1  2 μCox (W L) M1 I1
M1 M2 g m 6  2 μCox (W L) M6 I 2
  R 01  rds2 // rds 4
Cc R 02  rds 6 //rds 7
I1 g
I2  ωZ  m6 If g m 6 R 02  1
M3 M4 CC
CL 1  g m1
C1 Vo ω P1  
M6 (1  g m 6 R 02 ) CC R 01 A 0CC

GND If CC & C L  C1
C1  Cgd 2  Cdb2  Cgd 4  Cdb4  Cgs6  g m 6CC g
ωP 2   m6
CL  Cdb6  Cdb7  Cgd 7  Cload C L C1  C L C C  C C C1 CL
CC includes Cgd 6 CC

  
vid g m1vid R 01 vA C1 g m6vA R 02 C L Vo
  
 Right plane zero causes slower gain drop but quick phase drop
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-15 郭泰豪, Analog IC Design, 2018
 Pole-Splitting of Two-Stage CMOS OPAMP (Cont.)
P1 1 g m1
 Unity-gain frequency ft  A0 
2 2 C C

 To achieve a uniform -20dB/dec gain rolloff down to 0dB, the

following two conditions
g m1 g m 6
must be satisfied
1. f t  f P 2  C  C 20log|A| (dB)
C L
2. f t  f Z  g m1  g m 6 20log|Av|

fP1 fP2 fZ
0
 At unity-gain frequency ft (or fu) ft f (log scale)

Φ total  tan 1 f t f p1   tan 1 f t f p2   tan 1 f t f z 

where tan 1 f t f p1   90 Φ
0 f (log scale)
Phase margin  180  Φ total

-90º
 90  tan 1 f t f p2   tan 1 f t f z 
Phase margin
-180º

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-16 郭泰豪, Analog IC Design, 2018
 Right Plane Zero
 Causes slower gain drop but quick phase drop
Usually moved away if phase margin is not large enough
Im
Re
P2 P1 Z
g m5 g g m5
P2   P1   m1 Z
CL A 0CC CC

gain, dB


Phase
0
 90
180 
P1 Z P2
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-17 郭泰豪, Analog IC Design, 2018
 Right-Plane Zero (Cont.)
 The zero is due to the existence of two path through which the
signal can propagate from node A to node B CC

g m1 A gm6 B
R O1 C1 R O2 CL

1. through CC
2. through the controlled source gm6VA

 To eliminate zero ωz
1. Method-1 2. Method-2

C C unity gain buffer CC RZ

A1 A2 A1 A2

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-18 郭泰豪, Analog IC Design, 2018
 Eliminating Right-Plane Zero
 Method-1 : Using unity-gain buffer  Zero moves to infinity

or
Unity gain buffer
CC

A1 A2

Zero moves to infinity

ω
ωP2 ω P1 ωZ

A0  g m1  g m6
A(s)  where ω P1  , ω P2 
s s A 0CC CL
(1  )(1 )
ω P1 ω P2

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-19 郭泰豪, Analog IC Design, 2018
 Eliminating Right-Plane Zero (Cont.)
 Method-2 : Using R instead of buffer
1
 Eliminating zero  Let R Z 
gm6
 Pole-zero cancellation  Let ωZ  ωP2

g m1 CC R Z
ω P1  
A 0CC
g m6
ω P2   A1 A2
CL
1 1 1 1
ω P3   (   )
R Z C C C1 C L Zero moves toward
1 the left plane
ωZ  
1 ω
[R Z  ( )] C C ωP2 ω P1 ωZ
g m6

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-20 郭泰豪, Analog IC Design, 2018
 Pole Separation vs. Phase Margin and Speed
1
 ωu  ω 2  βA 0 ω1
n
 For fixed ω2
 n=1, Phase margin = 45o βA0
 n=2
 Phase margin = 63o ω2
 Fast (Step response)
ω1 ωu
 n=3, Phase margin = 71o
 n=4
 Phase margin = 76o

 Critically damped (Step response)

For n  2 For n  4

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-21 郭泰豪, Analog IC Design, 2018
 Pole-Zero Doublet
 First stage of a two-stage opamp
Assume : g m1  g m 2 , g m 3  g m 4 ,
VDD
C X  C gs3  C gs4  C db1  C db3  C gd1  C gd4

M6
i out1  i 2  i 3 
1  1 1  1 
M1 M2   v in  g m1   //   g m4  v in  g m2 
2  g m3 sCX  2 
 1 vin  1 vin
2 i1 i3 2
1  1  g m3
 g m1v in   1
i out1
where p 
 
 1  s/ω p 
vout1 2 CX
M3 M4
i2
1 s  i out1
rout  2ω p  |
v in
| (dB)
Cx  g m1v in   
 1  s 
 ω p 
GND
1 s 
 2ω p 

i out1
 g m1    p

2 p
v in  1 ω 
s
 p 

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-22 郭泰豪, Analog IC Design, 2018
 Pole-Zero Doublet (Cont.)
 Equivalent circuit of two-stage opamp (example: buffer in feedback
path) v
CC Unity gain buffer | out 2 | (dB)
v in
w/ pole-zero doublet
w/o pole-zero doublet

i out1 v out 2
vin A1 A2 p 2
v out1 
p1 p 2 p

1 s 
i out1  2ω p  v out 2 R o1g m 5 R o 2 1 g g
  g m1   , and  where ω P1   m1 , ω P 2  m 5
v in  1 s ω  i out1  s  s  R o1g m 5 R o 2 Cc A 0 Cc CL
 p   1 
 ω  ω   1  
 P1  P2 

1 s   
 1 s 
v out 2 i out1 v out 2 g m1R o1g m 5 R o 2  2ω p   2ω 
       A0
p

 s  s   1 s  s  s  
ω p 
v in v in i out1
1  1    1  1  1  s 
ωp 
 ω P1  ω P 2   ω P1  ω P 2 
 The parasitic capacitance Cx creates a pole at ωp and a zero at 2ωp.
 It may affect OPAMP stability if ωp close to unity gain frequency.
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-23 郭泰豪, Analog IC Design, 2018
 Introduction of Slew Rate (SR)
 Definition: Maximum change rate of voltage
Input Output
Input
Step Ideal
System Finite SR
(e.g. unity-gain buffer)
Slope=SR
Sine

 SR depends on system driving currents and capacitive loads

 SR should be considered at all nodes in circuit, for example:
dv o Ii
SR   i  1,2,3....
dt max Ci min

Sub- V1 Sub- V2 Sub- V3

Vi Vo
system1 system2 system3

I1 C1 I2 C2 I3 C3

System

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-24 郭泰豪, Analog IC Design, 2018
 SR Effect on Sinusoidal Response
 Voltage change rate without SR limitation
dv o dv o V̂i
vi  v o  V̂isinω t   ωV̂i cosω t   ωV̂i cos 0  ωV̂i
dt dt max
 Full-power bandwidth (fM)
SR  ωM Vo_max  f M 
SR
2 πVo_max  Vo_max: rated opamp output voltage
ωM : maximum input frequency without distortion
 SR effect on sine waves
 Small amplitude, low freq.  Large amplitude, low freq.
Vo without SR limitation
V Vo without SR limitation V
Vo with SR limitation
t t

 Small amplitude, high freq.

V Vo without SR limitation SR limitation depends on
t amplitude and frequency
Vo with SR limitation
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-25 郭泰豪, Analog IC Design, 2018
 SR Effect on Step Response of a One-Pole System
 Step response of a one-pole system
 Ideal response: Exponential output vO,Ideal(t)



-t
τ 
v O ,Ideal (t)  Vi 1 - e  
d
v 
 dt O ,Ideal

t   e
Vi - t τ
τ
 Without large enough system SR → Slewing happens

When SR 
d
dt
 
v O ,Ideal t  
d
dt
 
v O ,Real t   SR (As 0~t1 in the waveform below)

 Example: RC filter with current-limited voltage source

Slope=SR
vO V vI(t): Input
R vO,Ideal(t): Ideal
vI C vO,Real(t): Finite SR

t
Current-limited
voltage source SR Exponential
0 Limited t1 Response

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-26 郭泰豪, Analog IC Design, 2018
 Example 1 - Two-Stage OPAMP
 Vo rising process VDD
I6
 Large positive input at Vi+ M3 M4 M6
I5
 M1 turned off Iref Vo
M1 M2 Cc Rc
Vi- Vi+ I7
 I5 flows through Cc
CL
 Driving capability of I6 is usually large M7
 SR not limited by I6 M8 M5

 SR = I5 / Cc GND

 Vo falling process VDD

M3 M4 M6
 Large positive input at Vi-
I5
Iref Vo
 M2 turned off M1 I5 M2 Cc Rc
Vi- Vi+ I7
 I5 flow through Cc
CL
 I7 large enough: SR= I5 / Cc M7
M8 M5
 I7 not large enough: SR= I7 / (Cc+CL)
 SR when I7 is large enough GND

WM1 I 5 g dv o (t) I I 5 L M1
g m1  2 μCox , ω t  m1  SR   5  ωt  (VGS  Vt ) ω t
L M1 2 CC dt max CC μCox WM1

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-27 郭泰豪, Analog IC Design, 2018
 Example 2 - Negative Feedback Amplifier
R
 Slew rate
VDD
dVout 1 dQ c I
SR    o Io CC
dt CC dt CC M3 M4
Io
Io
 g m1 g m1 Vout
ω
 u C   C C  A2
 C ωu Vin R M1 M2
For 
g  2 μC W I V1 -V1
 m1 ox
L
o 0

 SR 
I o ωu
 ωu
Io
W
∥
g mi 2 μCox
L R

 Slew rate can be increased by Vin R

Vout
 Increasing the unity-gain bandwidth
 Increasing bias current of input stage
 Decreasing the W/L ratio of the input transistors

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-28 郭泰豪, Analog IC Design, 2018
 Example 3 - Voltage Follower (1/2)
 Vout at large positive input (t1 ~ t2)
Vin (t)  V1u(t)
dVW (t) dV (t) Vout
i W (t)  C W  C W in  C W V1δ(t) Vin
dt dt
1 t Io t C W tdVin Io CW Voltage follower
Vout (t) 
CC 
0
(Io  i W ) dt  
CC CC 0 dt dt 
CC
t 
CC
V1u(t)

 Circuit diagram
VDD Vin
off off
M3 M4 CC
V1

Io+iw A2 Vout t
off on
M1 M2 V1 Vout

With large driving capability V1

iw CW
VW Io Vin V1 V1
t
Cw CC
t1 t2 t3 t4
GND
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-29 郭泰豪, Analog IC Design, 2018
 Example 3 - Voltage Follower (2/2)
 Vout at large negative input (t3 ~ t4)
dVout dVW
As a source follower, VW follows Vout  
dt dt
dVout I i i dVW Vout
  o W   W ( ) Vin
dt CC CW dt
dVout Io Io Io Voltage follower
  SR reduced by C W , from to
dt CC  C W CC CC  C W
 Circuit diagram
VDD Vin
on on
M3 M4 CC
V1
Io-iw
Io-iw A2 Vout t
on off
M1 M2 V1 Vout

With large driving capability V1

iw CW
VW Io Vin V1 V1
t
Cw CC
t1 t2 t3 t4
GND
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-30 郭泰豪, Analog IC Design, 2018
 Noise Performance of CMOS OPAMP
 Noise is fundamental limitation of OPAMP performance
 The equivalent noise voltage of MOS OPAMPs may be 10 times larger
than that of a comparable bipolar amplifier
 Example
A d  g m1  (rds 2 // rds 4 ) for input signal, Vn1 and Vn2
A v  g m 3  (rds 2 // rds 4 ) for Vn3 and Vn4
VDD
Vn3 Vn4
M3 M4 V
n6
M6
ⓐ
Vn1 Vn2 Vout
Vin-
M1 M2 ⓑ

Vin+

Vbias M5 Vn7
M7
GND
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-31 郭泰豪, Analog IC Design, 2018
 Noise Performance of CMOS OPAMP (Cont.)
Vns
+ ⓐ ⓑ Vout
Vin Ad As

Vnd2
Differential Second
input stage Gain stage
Mean-square voltage at node ⓐ
VA2  A d2 (Vn21  Vn22 )  A 2v (Vn23  Vn24 )
2
V 2
 g m3 
Vnd 
2
 Vn1  Vn 2  
2
A
2
2
 (Vn23  Vn24 )
A d  g m1 
Equivalent input noise voltage
Vns2
V V  2
2
n
2
nd
Ad
g m3 2 2 g m 6 Vn26  g m 7 Vn27
 V V (
2
n1
2
n2 ) (Vn 3  Vn 4 ) 
2

g m1 A d2

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-32 郭泰豪, Analog IC Design, 2018
 Noise Performance of CMOS OPAMP (Cont.)
 Device noise
flicker noise
thermal noise
f
 1/f noise component dominates at low frequencies
 The equivalent input noise voltage is greatest at low frequencies
(below 1kHz)

 If |Ad()|>>1, then the input devices M1 and M2 tend to be the dominant

noise sources and their optimization is the key to low-noise design.

 1/f noise of OPAMP can be cancelled using

 Chopper-stabilized technique
(Dynamic Range over 100dB can be obtained)
 Correlated double sampling (CDS)

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-33 郭泰豪, Analog IC Design, 2018
 Offset Voltage of Two-Stage CMOS OPAMPs
 Input voltage need to restore the output to zero
 Two components
VDD (DC≠0, AC=0)
 Systematic offset
 Random offset M5 M7
Vbias
I I7 Ig
M1 M2
 To avoid systematic offset, VCM VCM VCM
(DC≠0, (DC≠0, (DC≠0,
design must follow the rule AC=0)
I/2 AC=0) I6 AC=0)
I/2

 
(W/L)M3 (W/L)M4 1 (W/L)M6
(W/L)M5 (W/L)M5 2 (W/L)M7 M3 M4 M6
DC GND (DC=0, AC=0)

 To minimize random offset

 L1=L2, W1=W2, L3=L4, W3=W4, L3=L6 and L5=L7 to minimize the
offsets of channel length and channel width variations
 Large L and W such that L/L and W/W can be ignored

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-34 郭泰豪, Analog IC Design, 2018
 Input Common-Mode Range and Output
Swing of Two-Stage CMOS OPAMP
 Input common-mode range, VICM
 Minimum VICM
To keep M1 and M2 in saturation, Vdg1,2 < |Vtp|. Hence,
VICM = Vtn + VOV3 − Vtp where Vov is overdrive voltage
 Maximum VICM
To keep M5 in saturation, Vds5 > Vov5. Hence,
VDD (DC≠0, AC=0)
VICM  VDD  VOV5  Vtp  VOV1
Vbias M5
 VOV3  Vtn - Vtp  VICM  VDD  Vtp  VOV1  VOV5
M7
I I7
 Output swing, VO VICM VICM Ig
M1 M2
To keep M6 and M7 in saturation I6
VOV 6  v o  VDD  VOV 7 I/2 I/2

M3 M4 M6

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-35 郭泰豪, Analog IC Design, 2018
 Amplifier Classification
Class A Iout

VX>>Vth
Iout Vin
Vin
VX  Vth
VX

Class B Iout

VX=Vth
Iout Vin
Vin
VX

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-36 郭泰豪, Analog IC Design, 2018
 Amplifier Classification (Cont.)
Class AB Iout

VX>Vth
Iout Vin
Vin
VX

Class C Iout

0<VX<Vth
Iout Vin
Vin
VX

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-37 郭泰豪, Analog IC Design, 2018
 Class D Amplifier
Class A, B and AB amplifier  Linear amplifier
Class D amplifier  Switching amplifier
 Block diagram  Common PWM Generator
VDD
Vin Vpwm
+
Vin Vpwm Vtri -
PWM Gate Low-pass
Generator Driver filter Vout

Amplitude(V)
1
Vin 0
-1
Vtri Vtri 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time(ms)

Amplitude(V) Amplitude(V)
GND 1
Vpwm 0.5
0

Characteristics 1
0 0.1 0.2 0.3 0.4 0.5
Time(ms)
0.6 0.7 0.8 0.9 1

 Low power dissipation  High efficiency

0.5
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time(ms)

Amplitude(V)
 Small heat sink  Small size
1
0
-1
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time(ms)

Amplitude(V)
 Distortion problem due to switching scheme 1
0.5
0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Time(ms)

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-38 郭泰豪, Analog IC Design, 2018
 Class D Amplifier (cont.)
Spectrum of Class D signal
 Square wave  PWM
Triangular wave: Vpp = 1V, Freq. =20KHz Triangular wave: Vpp = 2, Freq.=20KHz
Input sine wave: Vpp =0V Input sine wave: Vpp =2V, Freq.=1KHz

0 0

PSD Magnitude (dB)

PSD Magnitude (dB)

1KHz 20KHz
-10 20KHz -10
40KHz
-20 60KHz -20 60KHz
100KHz
-30 -30
-40 -40
-50 -50
-60 -60
10 20 30 40 50 60 70 80 90 100 10 20 30 40 50 60 70 80 90 100
Frequency (KHz) Frequency (KHz)
1 1
0.5 0.5

Magnitude (V)
Magnitude (V)

0 0
-0.5 -0.5
-1 -1
1 1

0.5 0.5

0 0
0.25 0.5 0.75 1 0.25 0.5 0.75 1
Time (ms) Time (ms)

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-39 郭泰豪, Analog IC Design, 2018
 Efficiency of Class D Amplifier (Cont.)
 Power loss source
VDD
VDD Mp

Io(RMS)
Gate Cgp Low-pass
Vin +
Driver filter
Cd RL Vo(RMS)
=Cdp+Cdn -
Cgn
Switching loss (Psw): Mn

 Conduction loss (Pcon):

Psw  (Cgp  C dp  C gn  C dn )  VDD 2  f sw
 Efficiency estimation
 
Pcon  D  R on(Mp)  (1  D)  R on(Mn)  I o(RMS)
2

Output of Gate Driver(V)

Where D is the duty of PMOS on
D×Ts (1-D)×Ts
I o(RMS)  R L
2
Po
η  100%   100% ...
I o(RMS)  R L  Psw  Pcon
2
Pi
Ts Time(s)
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-40 郭泰豪, Analog IC Design, 2018
 Output Stage of Two-Stage OPAMP
 Current waveforms
Class A amplifier
ic
IC
0 t

iC
2IC

0 t

 M6 conducts for entire cycle of the input signal

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-41 郭泰豪, Analog IC Design, 2018
 Cascode Circuit as a load
 To reduce # of stages in the design of high-gain OPAMP, cascode is
used.
 Ro=(gm2rds2)rds1 V DD

VSG1
Vbias1 rd1
M1
vA ⓐ
VSG2
Vbias2
gm2vA+gd2(vA-v)
M2 i
v Ro v Ro

 Voltage drop on the two MOSFETs must be minimized to increase

voltage swing
 Both transistors work at the voltage of VDS(min)

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-42 郭泰豪, Analog IC Design, 2018
 Cascode Circuit as a load (Cont.)
 (W/L)M1= (W/L)M2= (W/L)M3= 4(W/L)M4 VDD
VGS1
 (VGS3-Vtp)=VDS3(sat)= VDS1(sat) M3 VDS1
M1
= (VGS4-Vtp)/2= (VGS2-Vtp)
For safety, it is better to make VDS1 and VGS4 VGS2
VDS2 larger than saturation voltage
M4
 (W/L)M4< (1/4)(W/L)M1 M2

Iref Iref Ro

 One of other examples is self-biased VDD

VGS3
g m3
R o  (g m 2 rds 2 ) ( rds 3 // ri ) M3 VDS1
g m1 M1

where ri is the output resistance of Iref VGS4 VGS2

M4
M2
Iref
Ro
GND
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-43 郭泰豪, Analog IC Design, 2018
 CMOS OPAMP Using Cascode Load
 High gain stage VDD
 Example
M3 M4 V M11
1 bias1
R0  Vbias2 M5 M6
 1   1  M12
     Ro
 g m 6 rd 6 rd 4   g m8 rd8 rd 2 
Vbias3 M10

M7 M8 CC Vout
M14
M1 M2
Vin- Vin+

Vbias4 M9 M13

GND

 Normally, the differential stage must be followed by a level shifter

(usually a source follower) and often also by an output amplifier stage. It
needs them to be compensated by a pole-splitting capacitor and a
resistor or source follower.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-44 郭泰豪, Analog IC Design, 2018
 CMOS OPAMP Using Cascode Load (Cont.)
 Problems
 For large CL, the bandwidth will be limited by nondominant pole.
 Limited slew rate because of large Cc .
 PSRR is reduced by pole-splitting.

 All problems can be eliminated, and the circuit made faster as well as
simpler, by using “folded cascode” configuration.
 Q3~Q8 is disconnected from VDD, folded down, and connected to GND
instead.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-45 郭泰豪, Analog IC Design, 2018
 Folded-Cascode OPAMP
 Many modern CMOS OPAMPs are designed to drive only capacitive
load.
 It’s not necessary to use a voltage buffer to obtain a low output
impedance.
 It’s possible to realize OPAMPs having higher speed and larger
signal swings than those that must also drive resistance loads.
 These improvements are obtained by having only a single high-
impedance node at the output of an OPAMP that drives only
capacitive loads.
 The admittance seen at all other nodes in these OPAMPs is on
the order of a transistor’s transconductance, and thus they have
relatively low impedance.
 By having all internal nodes of relatively low impedance, the
OPAMP speed is maximized.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-46 郭泰豪, Analog IC Design, 2018
 Folded-Cascode OPAMP (Cont.)
 These low node impedance result in reduced voltage signals at
all nodes other than the output node. However, the current
signals in the various transistors can be quite large.
 With these OPAMPs, the compensation is usually achieved by
the load capacitance.
 As the load capacitance gets larger, the OPAMP usually
becomes more stable but also slower.
 One of the most important parameters of these OPAMPs is their
transconductance value. Therefore, some designers refer to
these modern OPAMPs as transconductance OPAMPs, or
Operational Transconductance Amplifiers (OTAs).

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-47 郭泰豪, Analog IC Design, 2018
 Folded-Cascode OPAMP (Cont.)
 A folded-cascode OPAMP

M3 M4
M11 Vb1
M5 M6

M12 M13

Ibias1
M1 M2
Vout
Vin CL

Vb2
Ibias2 M7 M8

M9 M10

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-48 郭泰豪, Analog IC Design, 2018
 Folded-Cascode OPAMP (Cont.)
 Current mirrors are all wide-swing cascode
 High output impedance
 High dc gain

 Two extra transistors, M12 and M13, serve two purposes

 Increase slew rate.
 Allow OPAMP to recover more quickly following a slew rate
condition.
(Because M12 and M13 prevent the drain voltages of M1 and M2
from having large transients.)

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-49 郭泰豪, Analog IC Design, 2018
 Folded-Cascode OPAMP (Cont.)
 The compensation is realized by the load capacitor, CL, and realizes
dominant pole compensation. In applications where the load
capacitance is very small, it is necessary to add additional
compensation capacitance in parallel with the load to guarantee
stability.

 Small-signal analysis
Vout (s) g m1rout
 AV   g m1Z L (s)  g m1 (rout // C L ) 
Vin (s) 1  srout C L
 Unity-gain frequency
g m1
t 
CL

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-50 郭泰豪, Analog IC Design, 2018
 Folded-Cascode OPAMP (Cont.)
 Second pole is usually generated at the nodes of M1(or M3) drain
and M2(or M4) drain.
g m6
P2 
C total (at M1 drain )
In BiCMOS, M5(M6) is usually replaced by a
BJT to push P2 to higher frequency.
(In BiCMOS, ωt can therefore be maximized.)

 Slew rate
ID4
SR 
CL
 M12 and M13 are included to increase SR. (These two transistors
are also used to clamp the drain voltage of M12 and M13.)

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-51 郭泰豪, Analog IC Design, 2018
 Linear Settling Time
1
 Time constant for linear settling is approximately equal to if
nondominant poles are larger than t ( u ) 3dB

For closed-loop OPAMP,

3dB  t

0dB 3dB t t

 For classical two-stage CMOS OPAMP the unity-gain frequency

remains relatively constant for varying load capacitances, the unity-gain
frequencies of folded-cascode and current-mirror amplifiers are strongly
related to their load capacitance. As a result, their settling-time
performance is affected by both the feedback factor as well as the
effective load capacitance.
 For folded-cascode OPAMP
g m1
t 
CL
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-52 郭泰豪, Analog IC Design, 2018
 Linear Settling Time (Cont.)
 -3dB frequency of a closed-loop cascoded (or current mirror ) OPAMP
 Example
C2
C1

Vin Cp CC Cload

1 /[s(C1  Cp )] C2
  ; CP is parasitic capacitance
1 / s(C1  Cp )  1 / sC2 C1  Cp  C2
C2 (C1  Cp )
CL  CC  Cload 
C1  Cp  C2

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-53 郭泰豪, Analog IC Design, 2018
 Linear Settling Time (Cont.)
g m1
t  (folded-cascode)
CL
1
Time constant  
t

 Step Response
Vout (t )  Vstep (1  e  t /  )
 If 1% accuracy is required  4.6
 If 0.1% (i.e. 10-bit) accuracy is required  7
d Vstep
Vout ( t ) |t 0 
dt 
 If the slew rate of the OPAMP is larger than this value, no slew-
rate limiting would occur.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-54 郭泰豪, Analog IC Design, 2018
 Fully Differential CMOS Switched-Capacitor Circuit
 Power supply rejection is high

 Larger chip area compared with single-ended output

 Output swing is doubled

 DR is 6dB greater than single-ended OPAMPs

 The effect of clock feedthrough noise is minimized by the differential

configuration since it will appear as a common-mode signal.

+ αC C
Vin
-+ Vo+
Vin-
+- Vo-
Vin+ αC C

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-55 郭泰豪, Analog IC Design, 2018
 Fully Differential OPAMPs
 Fully differential signal paths
 Differential input
 Differential output
 Used in most modern high-performance analog ICs

 Help reject noise from the substrate as well as from switches turning off
in switched-capacitor applications.
 Ideally, noise affects both signal paths identically and will then be
rejected since only the difference between signals is important.
 In reality, this rejection only partially occurs since the mechanisms
introducing the noise are usually nonlinear with respect to voltage
levels. For example, substrate noise will usually feed in through
junction capacitances, which are nonlinear with voltage.
 Certainly, the noise rejection of a fully differential design will be
much better than that for a single-ended output design.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-56 郭泰豪, Analog IC Design, 2018
 Fully Differential OPAMPs (Cont.)
 Common-mode feedback (CMFB) circuit must be added to establish the
common-mode (i.e. average) output voltage.

 Reduced slew rate in one direction (compared to single-ended design)

 Maximum current for slewing is often limited by fixed-bias currents in
the output stages.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-57 郭泰豪, Analog IC Design, 2018
 Fully Differential Folded-Cascode OPAMP
 Cascode current source (rather than self-biased current mirror)
Vout- Vout+

VB1 R R
M3 M4 VCM
M11 M12 VB2
A CMFB
circuit
M5 M6 Vcntrl
Vout+
M1 M2
Vout-
VB3
Vin
M8 M10 CMFB
circuit
Ibias
M9 Vcntrl
M7

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-58 郭泰豪, Analog IC Design, 2018
 Fully Differential Folded-Cascode OPAMP (Cont.)
 CMFB circuit forces the average of the two outputs to a predetermined
value
 Maximum negative slew rate is limited by ID7 and ID9
 Clamp transistors M11 and M12
 Dominant pole : output node
2nd pole : node at M1 (or M2) drain
 n-channel input and p-channel for M5 and M6
 High transconductance
 High gain
 p-channel input and n-channel for M5 and M6
 Maximize 2nd pole frequency
 Unity-gain bandwidth can be maximized.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-59 郭泰豪, Analog IC Design, 2018
 Common-Mode Feedback (CMFB) Circuits
 Force output common-mode voltage to a predetermined value
 CMFB is often the most difficult part of the OPAMP to design.
 Two typical approaches
 Continuous-time
 Limited signal swing
 Switched-capacitor
 Used in switched-capacitor circuits
 Signal swings are not limited
 Becomes a source of noise
 Increases load capacitance

 By having as few nodes in the common-mode loop as is possible,

compensation is simplified without having to severely limit the speed of
the CMFB circuit. For this reason, the CMFB circuit is usually used to
control current sources in the output stage of the OPAMP.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-60 郭泰豪, Analog IC Design, 2018
 CMFB Circuits
 A continuous-time CMFB circuit

IB IB
IB/2+∆I IB/2-∆I
M1 M2 M3 M4
Vout+ Vout-
VCM
Vcntrl
IB
M5
IB/2-∆I IB/2+∆I

IB
M6

 The circuit can not operate correctly if the OPAMP output voltage is
so large that transistors in the differential pairs turn off.
 When common-mode voltage is zero
IB IB
ID2   I, I D3   I, I D5  I B
2 2
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-61 郭泰豪, Analog IC Design, 2018
 CMFB Circuits (Cont.)
 Operational principle of CMFB circuits
 When a positive common-mode signal is present
 IM2 and IM3 increase → IM5 increase → Vcntrl increase
 Vcntrl sets the current levels in the n-channel current sources at the
output of the OPAMP.
 Thus, both current sources will have larger currents pulling down to
the negative rail → the common-mode voltage decrease → bringing
the common-mode voltage back to VCM
 If the common-mode loop gain is large enough, and the differential
signals are not so large as to cause transistors in the differential
pairs to turn off, the common-mode output voltage will be kept very
close to VCM.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-62 郭泰豪, Analog IC Design, 2018
 CMFB Circuits (Cont.)
 A switched-capacitor circuit
Vout+ Vout-
ϕ1 ϕ2 ϕ2 ϕ1

VCM CS CC CC CS VCM VB4

ϕ1 ϕ2 ϕ2 ϕ1

Vcntrl

 Using larger capacitance values overloads the OPAMP

 Reducing the capacitors too much caused common-mode offset
voltages due to charge injection of the switches.
 
Vout  Vout
 Vcntr1  VCM  VVbias
B4
2

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan 5-63 郭泰豪, Analog IC Design, 2018
 Appendix
 Operational-amplifier (OPAMP)
 Cascode CMOS and BiCMOS OPAMPs
 Folded-Cascode CMOS OPAMP
 Current mirror OPAMP
 Alternative fully differential OPAMPs
 BiCMOS amplifiers

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-1

5-64 郭泰豪, Analog IC Design, 2018
 Operational-Amplifier (OPAMP)

 OPAMP design
 CMOS OPAMPs are adequate for VLSI implementation.
 Main stream
 Two-stage and folded-cascode OPAMPs will be introduced.
 Bipolar OPAMPs
 Can achieve better performance than CMOS OPAMPs.
 Less popular
 741 OPAMP will be introduced.
 BiCMOS OPAMPs
 combine the advantages of bipolar and CMOS devices.
 Less popular
 First published by H. C. Lin in 1960’s.
 ADCs and DACs are the most important analog ICs in many systems.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-2

5-65 郭泰豪, Analog IC Design, 2018
 CMOS OPAMP

 Two-stage
I guess, it is suitable for 50% of applications with OPAMPs.
 Folded-cascode
I guess, it is good for 20% applications.
 Others

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-3

5-66 郭泰豪, Analog IC Design, 2018
 Cascode CMOS and BiCMOS OPAMPs
 Cascaded two-stage CMOS OPAMP
 most popular and works well with low capacitive load
 problems
 limited slew rate due to large Cc
 limited bandwidth with large CL
 PSRR is reduced by pole-splitting
 If 1. low output resistance is not required,
2. high open-loop gain is required, and
3. large phase margin can be maintained with large CL,
then cascode configuration can provide attractive solutions
for the above problems.
 Cascode CMOS OPAMP
 Gain of two-stage OPAMP can be increased by adding
gain stage in cascade.
 phase shift is increased (i.e. PM)
 Cascode configurations can be used to increase gain in
the existing stage.
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-4
5-67 郭泰豪, Analog IC Design, 2018
 Cascode CMOS OPAMP
VDD

 Output resistance(Ro) is increased Q 7 Q8

R O 6  (g m 6 rds 6 ) rds 8
RO 4  (g m 4 rds 4 ) rds 2 Q5 Q 6
R O6
RO  RO 2 //RO 4
Vbias R O4
 Voltage gain A 1   gm 1 RO
 Gain is increased. 
Q3 Q 4

Q1 Q2
 Common-mode range is lowered and
more transistors are stacked between I
the two power supplies.
 Folded-cascode has large common-mode range
 Cascode and folded-cascode OPAMPs are also named as
“transconductance OPAMP” or
“operational transconductance amplifier (OTA)”
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-5
5-68 郭泰豪, Analog IC Design, 2018
 Folded-Cascode CMOS OPAMP
 Q3 ~ Q8 are folded and connected to GND
VDD
Cascode transistors
IB IB

VBIAS1
Q3 Q4
Vin+ Q1 Q2 Vin- Vo
Q5 Q6
I CL
Input differential
pair
Q7 Q8 Cascode current
mirror

GND
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-6
5-69 郭泰豪, Analog IC Design, 2018
 Folded-Cascode CMOS OPAMP (Cont.)
 Q9 ~ Q11 form externally-biased current sources
Q5 and Q8 form self-biased current sources
VDD
VBIAS2
Q9 Q10

VBIAS1
Q3 Q4
Vin+ Q1 Q2 Vin- Ro4
Vo
Ro6
Q5 Q6
VBIAS3 Q11 CL
I Q7 Q8

GND
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-7
5-70 郭泰豪, Analog IC Design, 2018
 Folded-Cascode CMOS OPAMP (Cont.)
 Input common-mode range
Common-mode range is increased (compared with cascode
OPAMPs). However, it is small compared with 2-stage OPAMPs
VOV 11  VOV 1  Vtn  VICM  VDD  VOV 9  Vtn

 Output voltage swing

VOV 7  VOV 5  Vtn  Vo  VDD  VOV 10  VOV 4

 Voltage gain
A = GmRo = gm1Ro
where
Ro = Ro4 // Ro6
= gm4rds4(rds2//rds10) // gm6rds6rds8
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-8
5-71 郭泰豪, Analog IC Design, 2018
 Folded-Cascode CMOS OPAMP
 Frequency response gain

 Bode plot A larger CL

1
p ≈ R C smaller CL
0 L t
g m1
t ≈ CL ωp
frequency
nondominant poles
 The
only high-impedance point is the output node.
 Dominant pole is generated at the output node
 The resistance of all other node at level of 1/gm
 Nondominant poles occur at all other nodes.
The 2nd pole is usually at the source of Q3 and Q4.
 Nondominant poles are usually at frequencies beyond t
 If CL is increased, then phase margin is increased.
 If CL is not large enough, it can be augmented.
 No frequency compensation is required
 wide bandwidth
 Slew rate SR=I/CL= 2 πf t VOV1  ω t VOV1
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-9
5-72 郭泰豪, Analog IC Design, 2018
 Folded-Cascode CMOS OPAMP(Cont.)
 High PSRR (to-VSS)
 much less susceptible to the effect of high-frequency
noise on GND
 power supply noise may be induced from
 logic circuit
 switches of SC circuit
 current switching
Low PSRR (to-VSS) in cascaded 2-stage OPAMP
 GND noise  Q6 source  Q6 gate  C,R  output
 GND noise  Q6 source  Q6 VGS amplified and
appear at output
output

A1 Q6

GND
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-10
5-73 郭泰豪, Analog IC Design, 2018
 Wide-Swing Current Mirror
 Increased output voltage range
 v Omin  VOV1  VOV 3  Vtn  v Omin  VOV1  VOV 3
VDD VDD

IREF IREF
Io Io
Vt+VOV

Q4 Q3 Q4 Q3
2Vt+2VOV
VBIAS=Vt+2VOV
Vt+VOV VOV VOV

Q2 Q1 Q2 Vt+VOV
Q1
Vt+VOV

GND GND
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-11
5-74 郭泰豪, Analog IC Design, 2018
 Wide-Swing Current Mirror (Cont.)
 Design example VDD

a varying signal Iin  Ibias Ibias Iin Vo Io

Vbias W L W L
2ID2 Q5
n2 n2
Veff2  Veff3   Veff Q4 Q1
μnCox W/L  W L
n  12 WL WL
Q2
μ C W Q3
 n ox
2
( I D 2 Veff )
2 L GND
W  W  2W  2W  2W 

Since      n  1    n    n  
  2  3
L L  5
L  1
L  L 4
Veff 1  Veff 4  nVeff for the target Iin  Ibias
VG5  VG4  VG1  (n  1)Veff  Vth
VDS2  VDS3  VG5  VGS1  VG5  (nVeff  Vth )  Veff
 Vo  Veff1  Veff2  (n  1)Veff

 A common choice, n  1, Vout  2Veff

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-12

5-75 郭泰豪, Analog IC Design, 2018
 Folded-Cascode with Wide-Swing Current Mirror

VDD
VBIAS2
Q9 Q10

VBIAS1
Q3 Q4
Vin+ Q1 Q2 Vin- Ro4
VBIAS4 Vo
Ro6
Q5 Q6
VBIAS3 Q11 CL
I Q7 Q8

GND

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-13

5-76 郭泰豪, Analog IC Design, 2018
 Folded-Cascode with Rail-to-Rail Input Operation
 Increased input common-mode range, rail-to-rail or even larger
 Voltage gain, if gm1=gm3=Gm
 A = (gm1+gm3)Ro = 2GmRo for middle VICM
 A = gm1Ro for high VICM
 A = gm3Ro for low VICM
VDD

IB IB
I
Q5 Q6
VBIAS1
Vin+ Q1 Q2 Vin-
Vo
Vin- Q4 Q3 Vin+
Q7 Q8
VBIAS2
I
IB IB

GND
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-14
5-77 郭泰豪, Analog IC Design, 2018
 BiCMOS Folded-Cascode OPAMP
 Configuration
 VDD

Q3 Q4
Vbias1
Q5
2I Q 3C Q 4C

 VO

Q1 Q2 CL
Q1C Q2C
Vbias2

IB
IB
Q6 Q7
Vbias3

 VSS

 When it is necessary to drive a resistive load, a low

resistance output buffer is needed
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-15
5-78 郭泰豪, Analog IC Design, 2018
 BiCMOS Folded-Cascode OPAMP (Cont.)

 The largest nondominant pole is usually generated at the

emitter nodes of Q1C and Q2C
1 g m1C 1
ωp2   where R1C  R e1c //rO(Q16) //rO(Q1)  R e1c 
R1CC p1 Cp1 g m1c

 The transconductance of BJT can be much larger than

that of CMOS
 P2 can be increased
 u can be increased while enough phase
margin is maintained
 Wider bandwidth than that of CMOS folded-
cascode OPAMP

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-16

5-79 郭泰豪, Analog IC Design, 2018
 Current Mirror OPAMP

 A simplified current-mirror OPAMP

1:K KID1

KID2 Vout
1:1
CL
Q1 Q2 1:K
Vin

Ib

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-17

5-80 郭泰豪, Analog IC Design, 2018
 Current Mirror OPAMP (Cont.)
 A current-mirror OPAMP with wide-swing cascode current
mirrors

Q5 Q6 Q7 Q8
VB2 VB2
Q3 Q4 Q9 Q10
VB1 Vout
Q11
Q1 Q2 Q12 CL
Vin
Q13 Q14
Ib
ID  kI1  kIb / 2
14

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-18

5-81 郭泰豪, Analog IC Design, 2018
 Current Mirror OPAMP (Cont.)
W / L 8 W / L 7 W / L 12 W / L 14
 k,  1,  k
W / L 5 W / L 6 W / L 11 W / L 13

s k gm1r out

 AV 
V out  k gm1 zL s   k gm1r out // CL  
Vin s  1  s r out CL

where k is the current gain from Q5 to Q8

 Unity-gain frequencyt

kgm1 k 2 ID1n cox W / L 1

t  
CL CL
 Total OPAMP current Itotal = (3 + K )ID1

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-19

5-82 郭泰豪, Analog IC Design, 2018
 Current Mirror OPAMP (Cont.)

 
k 2 Itotal  n Cox W / L 1
 3k k 2 Itotal n Cox W / L 1
t  
CL 3k CL

k  t  for a specified power dissipation

 The important nodes for determining the nondominant
pole are the drain of Q1, primarily, and the drains of Q2
and Q9, secondly.
Increasing K increases the capacitances of these nodes
while also increasing the equivalent resistances.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-20

5-83 郭泰豪, Analog IC Design, 2018
 Current Mirror OPAMP (Cont.)
As a result, the equivalent second pole moves to lower
frequencies. If K is increased too much, an increase in CL
will be required to keep t below the frequency of the
equivalent second pole to maintain stability. Thus,
increasing K decreases the bandwidth when the equivalent
second poles dominate. In the case where the load
capacitance is small, the equivalent second pole will limit
the unity-gain frequency of the opamp, and if it is very
important that speed is maximized, K might be taken as
small as one. From experience it has been found that a
reasonable compromise for a general-purpose opamp
might be to let K = 2.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-21

5-84 郭泰豪, Analog IC Design, 2018
 Current Mirror OPAMP (Cont.)
 Slew rate
kI b
SR     Larger compared to folded-cascode
CL
 Due primarily to the larger bandwidth and slew rate, the
current-mirror OPAMP is usually preferred over a
folded-cascode OPAMP.
However, it will suffer from larger thermal noise when
compared to a folded-cascode amplifier because its
input transistors are biased at a lower current level
and therefore have a smaller transconductance.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-22

5-85 郭泰豪, Analog IC Design, 2018
 Alternative Fully Differential OPAMPs
 A fully differential current-mirror OPAMP
1:K

1:K
Q1
Q2 Vout
Vin
VB3 CMFB
Q4 Q6 VCM
Ibias circuit

Q3 Q5
Vcntrl
 n-channel input high gain
lower thermal noise
 p-channel input wide bandwidth
low 1/f noise
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-23
5-86 郭泰豪, Analog IC Design, 2018
 Alternative Fully Differential OPAMPs (Cont.)
 A fully differential OPAMP with bidirectional output drive

K:1 1:K

1:1 1:1

Vin+ Q1 Q2 Vin-
Vout+ Vout-

Ibias

K:1 1:K

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-24

5-87 郭泰豪, Analog IC Design, 2018
 Alternative Fully Differential OPAMPs (Cont.)
 A class AB fully differential OPAMP

K:1 Q1 Q8 Q4 Q5 1:K
Vin+ Vin-

Vout+ Q2 Q6 Vout-
Q3 Q7

K:1 1:K

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-25

5-88 郭泰豪, Analog IC Design, 2018
 Alternative Fully Differential OPAMPs (Cont.)
 The advantage of the input stage in this OPAMP is that during
slew-rate limiting, one differential pair will turn off, but the total
current in the other differential pair will dynamically increase
substantially.
 The disadvantage of this design is that the level-shift circuitry
required at the input increases the noise and adds additional
parasitics, which contribute to the equivalent second pole. In
addition, the common-mode range of the input must remain at
least 2Vt + 3Veff above the lower power supply (and typically
higher for the slew-rate performance to be maintained). This is
a major problem when 5-V power supplies are being used, and
it effectively eliminates this design from consideration for use
with 3.3-V power supply voltages. However, for applications
where the power-supply voltages are large, the load
capacitances are large, and the slew rate is very important, this
approach is quite reasonable.
Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-26
5-89 郭泰豪, Analog IC Design, 2018
 Alternative Fully Differential OPAMPs (Cont.)
 A fully differential OPAMP composed of two single-ended
output current-mirror OPAMPs
Reading Assignment p.284 ~ 286
 An OPAMP having rail-to-rail common-mode voltage range

M2 I2
I1 Vb1 I1
Vsp Q9 Q 10
Q6
Q1 Q2 Vout Vout

Vin Q3 Vin
Q4
Q5 Q7 Q8
Vsn
Vb 2
I1 M1

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-27

5-90 郭泰豪, Analog IC Design, 2018
 Alternative Fully Differential OPAMPs (Cont.)
 When the input common-mode voltage range is close to
one of the power-supply voltages, one of the input
differential pairs will turn off, but the other one will remain
active.
 In an effort to keep the OPAMP gain relatively constant
during this time, the bias currents of the still-active
differential pair are dynamically increased. M1, M2, Q5, Q6
are added for this purpose.
 With careful design, it has been reported that the
transconductance of the input stage can be held constant
to within 15% of its nominal value with an input common-
mode voltage range as large as the difference between
the power-supply voltages.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-28

5-91 郭泰豪, Analog IC Design, 2018
 BiCMOS Amplifiers
 Source follower–common emitter
Vcc
 Ri = ∞ M1
vin
rπ 2 VA ; VA is Early voltage
AV  
1 Q2 vo
 rb 2  rπ 2 VT ; VT is thermal voltage
gm

 Advantages:
 Infinite input resistance
 Higher gain than MOS common source AMP
1 g
 Drawback: pole at p   m1
1
[(  rb 2 ) // r 2 ]C  2 C  2
g m1
(Assuming rb2 << 1/gm1 < rπ)

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-29

5-92 郭泰豪, Analog IC Design, 2018
 Source Follower-Emitter Follower

vcc

Vo 1
vin Q2 ;  1, R i   , R o 
vo Vi gm2
M1

GND

 Note: use PMOS input for better output swing no back-gate effect(N-
well process).
 Advantages: Infinite input resistance
Low output resistance
g m1
 Disadvantages: pole at
C2

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-30

5-93 郭泰豪, Analog IC Design, 2018
 Cascode Amplifiers
 Cascode to increase Ro
 Ri = ∞
vo
 Av = gm1(βro2)
BIAS
 Advantages:
 Infinite input resistance vin
 High gain
 Good dynamics(2nd pole at fT of NPN)
 The above circuit chooses BJT on MOSFET.
 Higher Ro
 Higher Ri
 Wider bandwidth

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-31

5-94 郭泰豪, Analog IC Design, 2018
 Double Cascode Amplifiers
VDD
M4
M3
BIAS2
vo
BIAS1 Q2
vin Q1

 Ri = rπ1
 Av=gm1(gm3ro3)(βro2)
 Advantage: extremely high gain
(gain of more than 106 achievable)
 Note: A source follower can be added
if any resistive load is to be driven.

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-32

5-95 郭泰豪, Analog IC Design, 2018
 OPAMP Circuits
 Bipolar OPAMP VDD

CC
vo

GND
 Source follower input bipolar OPAMP
VDD

vo
 Drawback:
g m ,MOS
 Additional pole at GND
C  ,PNP

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-33

5-96 郭泰豪, Analog IC Design, 2018
 BiCMOS Differential Amplifier
 For high input resistance and zero input bias current
 Use MOSFET input
 For low offset
 Use BJT input.
 Usually, the subsequent stages utilize BJT to obtain a wide bandwidth.

 BiCMOS OPAMP VDD

 Ri= ∞
G m2 CC
 Wu < P2 =
CL CL

 Advantages: high Wu GND

(higher poles at fT of NPN’s)

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-34

5-97 郭泰豪, Analog IC Design, 2018
 CMOS Folded-Cascode OPAMP
VDD
M6 M5
-
Vi
M8 M7
+
M 1 M2 +
Bias M3 M4
Vo
-

Bias M10 M9
1
P1  GND
R 0C L

 g m3
P2  ; CS is the total cap. at the source of
CS the common gate transistors
g m1
u 
CL

Prof. Tai-Haur Kuo, EE, NCKU, Tainan City, Taiwan APP5-35

5-98 郭泰豪, Analog IC Design, 2018