CH32V003DS0

CH32V003 Datasheet
V1.3
Overview
CH32V003 series is an industrial-grade general-purpose microcontroller designed based on QingKe RISC-V2A
core, which supports 48MHz system main frequency in the product function. The series features wide voltage,
single-wire serial debug interface, low-power consumption and ultra-small package. It provides commonly used
peripheral functions, built-in 1 group of DMA controller, 1 group of 10-bit analog-to-digital conversion ADC, 1
group of op-amp comparator, multiple timers, standard communication interfaces such as USART, I2C, SPI, etc.
The rated operating voltage of the product is 3.3V or 5V, and the operating temperature range is -40℃～85℃
industrial- grade.
Features
l Core l 1 group of OPA and comparator: connected
- QingKe 32-bit RISC-V core, RV32EC with ADC and TIM2
instruction set l 1 group of 10-bit ADC
- Fast programmable interrupt controller + - Analog input range: 0~VDD
hardware interrupt stack - 8 external signals + 2 internal signals
- Support 2-level interrupt nesting - Support external delayed triggering
- Support system main frequency 48MHz l Multiple timers
l Memory - 1 16-bit advanced-control timers, with dead
- 2KB volatile data storage area SRAM zone control and emergency brake; can offer
- 16KB program memory CodeFlash PWM complementary output for motor control
- 1920B BootLoader - 1 16-bit general-purpose timers, provide
- 64B non-volatile system configuration input capture/output comparison/PWM/pulse
memory counting/incremental encoder input
- 64B user-defined memory - 2 watchdog timers (independent watchdog
l Power management and low-power and window watchdog)
consumption - SysTick: 32-bit counter
- System power supply VDD: 3.3V or 5V l Communication interfaces
- Low-power mode: Sleep, Standby - 1 USART interfaces
l Clock & Reset - 1 I2C interfaces
- Built-in factory-trimmed 24MHz RC - 1 SPI interfaces
oscillator l GPIO port
- Built-in 128KHz RC oscillator - 3 groups of GPIO ports, 18 I/O ports
- High-speed external 4~25MHz oscillator - Mapping 1 external interrupt
- Power on/down reset, programmable voltage l Security features: 64-bit unique ID
detector l Debug mode: 1-wire serial debug interface
l 1 group of 1-channel general-purpose DMA (SDI)
controller l Package: SOP, TSSOP or QFN
- 7 channels, support ring buffer
- Support TIMx/ADC /USART/I2C/SPI
General- Advanced- General- System ADC
Flash Pin Package
Model SRAM purpose control purpose Watchdog clock ChannelSPI I2C USART
memory No. Form
I/O timer timer source No.
CH32V003F4P6 TSSOP20
16K 2K 20 18 1 1 2 3 8 1 1 1
CH32V003F4U6 QFN20
CH32V003A4M6 16K 2K 16 14 1 1 2 3 6 1 1 SOP16
-
CH32V003J4M6 16K 2K 8 6 1 1 2 3 6 1 1 SOP8
CH32V003 Datasheet http://wch.cn
Chapter 1 Specification
1.1 System architecture

The microcontroller is based on the RISC-V instruction set of QingKe V2A design, and its architecture
includes the core, arbitration unit, DMA module, SRAM storage and other parts of the interaction through
multiple groups of buses. The design integrates a general-purpose DMA controller to reduce CPU load and
improve access efficiency, and also has data protection mechanisms and automatic clock switching protection
to increase system stability. The following diagram shows the overall architecture of the product.
Figure 1-1 System block diagram
FLASH @VDD VDD : 2.7V~5.5V

RISC-V (V2A) I-code Bus VSS
CTRL
PFIC
RV32EC
SWIO 1-wire SDI D-code Bus
Flash
MUX
Memory
DMA 7 Channels
System Bus
Reset &
SYSCLK
MUX & DIV
MUX
SRAM
HSI-RC
AHBCLK *2
OSC_IN
HSE
OSC_OUT
WWDG GPIO
IWDG_CLK LSI-RC
IWDG PWR_CLK
EXTI
AHB Fmax = 50MHz
PWR
EXTEN
I2C SCL, SDA
AIN0~AIN7
ETR、ETR2 ADC
AFIO
Amplify
OPAPx GPIOA PA1 ~ PA2

OPAO
OPANx
(x=0,1) Compare
GPIOC PC0 ~ PC7
TIM2_CH1 GPIOD PD0 ~ PD7
4 channels, ETR TIM2

4 channels
TIM1 3 complementary Channels
ETR, BIKN
RX, TX, CTS, RTS, CK USART
SPI MOSI,MISO,SCK, NSS
V1.3 1
1.2 Memory map
Figure 1-2 Memory address map
Reserved
0x5005 0400
Reserved
0x4002 3C00
EXTEND
0x4002 3800
Reserved
0x4002 2400
Flash Interface
0x4002 2000
Reserved
0x4002 1400
RCC
0x4002 1000
Reserved
0x4002 0400
DMA
0x4002 0000
Reserved
0x4001 3C00
USART
0x4001 3800
Reserved
0x4001 3400
SPI
0x4001 3000
TIM1
0x4001 2C00
Reserved
0x4001 2800
ADC
0x4001 2400
0xFFFF FFFFF Reserved
0x4001 1800 Port D
0x4001 1400 Port C
0x1FFF FFFF Reserved 0x4001 1000
Reserved Reserved
0x4001 0C00
0x1FFF F840 Port A
Option Bytes 0x4001 0800
0x1FFF F800 0xE010 0000 EXTI
Core Private 0x4001 0400
Vendor Bytes Peripherals AFIO
0x1FFF F7C0 0x4001 0000
Reserved 0xE000 0000
0x1FFF F780 Reserved
0x4000 7400
System FLASH PWR
(BOOT_1920B) 0x4000 7000
Reserved
0x1FFF F000
Reserved
Reserved
0x4000 5800
Peripherals I2C
0x0800 4000 0x4000 5400
0x4000 0000
Reserved
Code FLASH Reserved
0x4000 3400
16KB 0x2000 0800 IWDG
2KB SRAM 0x4000 3000
0x2000 0000 WWDG
0x0800 0000 0x4000 2C00
Aliased to Flash or
system memory
depending on FLASH
Reserved
software
configuration
0x0000 0000 0x0000 0000 0x4000 0400
4G linear address space TIM2
0x4000 0000
V1.3 2
1.3 Clock tree

Three groups of clock sources are introduced into the system: internal high-frequency RC oscillator (HSI),
internal low-frequency RC oscillator (LSI), external high-frequency oscillator (HSE), and external
low-frequency oscillator (LSE). Among them, the low-frequency clock source provides the clock reference
for RTC and independent watchdog. The high-frequency clock source is directly or indirectly output as
system clock (SYSCLK) via 2X frequency. The system clock is then provided by each prescaler to provide
the AHB domain in peripheral control clock and sampling or output clock. Some modules need to be directly
provided by the PLL clock.
V1.3 3
Figure 1-3 Clock tree block diagram
to gpio(internal,to time)
128kHz IWDGCLK
LSI RC to independent watchdog
to pwr(low power clock source)
RCC_CFGR0
SW
OSC_IN 4~25MHz *2
PLLSRC
OSC_OUT HSE OSC
SYSCLK
/3 to Flash(time base)
SW
24MHz
HSI RC HSI
CSS
MCO[1:0] to Flash（register）
AHB prescaler
/1,/2.../256
HSI FCLK core free running clock
MCO
HSE
PLLCLK to Core System Timer
/8
HCLK
to SRAM/DMA
48MHz max
peripheral clock enable
to AHB peripherals
to TIM2
to TIM1
/2,/4,/6,/8,/12,/1 ADCPRE
to ADC
6…,/64,/96,/128
/4096 to WWDG
V1.3 4
1.4 Functional description

1.4.1 RISC-V2A processor
The RISC-V2A supports the EC subset of the RISC-V instruction set. The processor is managed internally in
a modular fashion and contains units such as a fast programmable interrupt controller (PFIC), extended
instruction support, and more. The bus is connected to an external unit module to enable interaction between
the external function module and the core. RV32EC instruction set, small-end data mode.
The processor with its minimal instruction set, multiple operating modes, and modular custom expansion can
be flexibly applied to different scenarios of microcontroller design, such as small area low-power embedded
scenarios.
l Support machine mode
l Fast Programmable Interrupt Controller (PFIC)
l 2-level hardware interrupt stack
l 1-wire serial debug interface (SDI)
l Custom extended commands
1.4.2 On-chip memory and boot mode

Built-in 2K bytes SRAM area for data storage, data loss after power down.
Built-in 16K bytes of program flash memory storage (Code FLASH) for user applications and constant data
storage.
Built-in 1920 bytes of system storage (System FLASH) for system bootloader storage (factory-cured
bootloader)
64 bytes are used for the system non-volatile configuration information storage area and 64 bytes are used for
the user select word storage area.
Support Boot and user code jumping to each other.
1.4.3 Power supply scheme

VDD = 2.7～5.5V: Power supply for some I/O pins and internal voltage regulator (VDD performance gradually
deteriorates if less than 2.9V when using ADC).
1.4.4 Power supply monitor

This product integrates a power-on reset (POR)/power-down reset (PDR) circuit, which is always in working
condition to ensure that the system is in supply. It works when the power exceeds 2.7V; when VDD is lower
than the set threshold (VPOR/PDR), the device is placed in the reset state without using an external reset circuit.
In addition, the system is equipped with a programmable voltage monitor (PVD), which needs to be turned
on by software to compare the voltage of VDD power supply with the set threshold VPVD.Turn on the
corresponding edge interrupt of PVD, and you can receive interrupt notification when VDD drops to the PVD
threshold or rises to the PVD threshold. Refer to Chapter 4 for the values of VPOR/PDR and VPVD.
1.4.5 Voltage regulator

After reset, the regulator is automatically turned on, and there are 3 operation modes according to the
application mode.
l ON mode: Normal operation, providing stable core power.
l Low-power mode: When the CPU enters Stop mode, system automatically enters Standby mode.
V1.3 5
1.4.6 Low-power mode

The system supports 2 low-power modes, which can be selected for low-power consumption, short start-up
time and multiple wake-up events to achieve the best balance.
l Sleep mode
In Sleep mode, only the CPU clock is stopped, but all peripheral clocks are powered normally and the
peripherals are in a working state. This mode is the shallowest low-power mode, but it is the fastest mode to
wake up the system.
Exit condition: any interrupt or wake-up event.
l Standby mode
The PDDS and SLEEPDEEP bits are set, and the WFI/WFE instruction is executed to enter. The power
supply of the kernel part is turned off, and the RC oscillator of HSI and the HSE crystal oscillator are also
turned off, and the lowest power consumption can be achieved in this mode.
Exit conditions: any external interrupt/event (EXTI signal), external reset signal on NRST, IWDG reset,
where EXTI signal includes one of 18 external I/O ports, output of PVD, AWU auto-wakeup.
1.4.7 Fast Programmable Interrupt Controller (PFIC)

The product's built-in Fast Programmable Interrupt Controller (PFIC) supports up to 255 interrupt vectors,
providing flexible interrupt management capabilities with minimal interrupt latency. The current product
manages 4 core private interrupts and 23 peripheral interrupt management, with other interrupt sources
reserved. the registers of PFIC are all accessible in machine privileged mode.
l 2 individually maskable interrupts
l Provide a non-maskable interrupt NMI
l Hardware interrupt stack (HPE) support without instruction overhead
l Provide 2-way meter-free interrupt (VTF)
l Support vector table mode for address or instruction mode
l Support 2-level interrupt nesting
l Support break tail link function
1.4.8 External interrupt/event controller (EXTI)

The external interrupt/event controller contains a total of 8 edge detectors for generating interrupt/event
requests. Each interrupt line can be independently configured with its trigger event (rising or falling edge or
double edge) and can be individually masked; the pending register maintains the status of all interrupt
requests. EXTI can detect clock cycles with pulse widths less than the internal AHB. 18 general purpose I/O
ports are optionally connected to the same external interrupt source.
1.4.9 General-purpose DMA controller

The system has built-in 1 group of general-purpose DMA controllers, manages 8 channels in total, and
flexibly handles high-speed data transmission from memory to memory, peripherals to memory, and memory
to peripherals, and supports ring buffer mode. Each channel has a dedicated hardware DMA request logic to
support one or more peripherals' access requests to the memory. The access priority, transfer length, source
address and destination address of the transfer can be configured.
The main peripherals used by DMA include: general-purpose/advanced-control/basic timers TIMx, DAC,
V1.3 6
USART, I2C and SPI.
Note: DMA and CPU access the system SRAM after arbitration by the arbiter.
1.4.10 Clock and boot

The system clock source HSI is turned on by default. After the clock is not configured or reset, the internal
24MHz RC oscillator is used as the default CPU clock, and then an external 4~25MHz clock or PLL clock
can be additionally selected. When the clock security mode is turned on, if the HSE is used as the system
clock (directly or indirectly), the system clock will automatically switch to the internal RC oscillator when
the external clock is detected to be invalid, and the HSE and PLL will be automatically turned off at the same
time; in low-power consumption mode, the system will automatically switch to the internal RC oscillator
after waking up. If the clock interrupt is enabled, the software can receive the corresponding interrupt.
1.4.11 Analog-to-digital converter (ADC)

The product is embedded with a 10-bit analog/digital converter (ADC) that shares up to eight external
channels and two internal channel samples, with programmable channel sampling times for single,
continuous, sweep or intermittent conversion. Provides analog watchdog function allows very accurate
monitoring of one or more selected channels for monitoring channel signal voltages. Supports external
event-triggered transitions with trigger sources including internal signals from the on-chip timer and external
pins. Support for using DMA operation. Supports external trigger delay function. When this function is
enabled, the controller delays the trigger signal according to the configured delay time when an external
trigger edge is generated, and the ADC conversion is triggered as soon as the delay time is reached.
1.4.12 Timer and watchdog

The timers in the system include an advanced-control timer, a general-purpose timer, two watchdog timers
and system time base timer.
l Advanced-control timer
The advanced-control timer is a 16-bit auto-loading up/down counter with a 16-bit programmable prescaler.
In addition to the complete general-purpose timer function, it can be regarded as a three-phase PWM
generator distributed to 6 channels, with a complementary PWM output function with dead zone insertion,
allowing the timer to be updated after a specified number of counter cycles to repeat counting cycle, braking
function, etc. Many functions of the advanced-control timer are the same as the general timer, and the internal
structure is also the same. Therefore, the advanced-control timer can cooperate with other TIM timers
through the timer link function to provide synchronization or event link functions.
l General-purpose timer
The general-purpose timer is a 16-bit or 32-bit auto-loading up/down counter with a programmable 16-bit
prescaler and 4 independent channels. Each channel supports input capture, output comparison, and PWM
generation and single pulse mode output. It can also work with advanced-control timers through the timer
link function to provide synchronization or event link functions. In Debug mode, the counter can be frozen
while the PWM outputs are disabled, thereby cutting off the switches controlled by these outputs. Any
general-purpose timer can be used to generate PWM output. Each timer has an independent DMA request
mechanism. These timers can also process signals from incremental encoders, as well as digital outputs from
1 to 3 Hall sensors.
V1.3 7
l Independent watchdog
The independent watchdog is a configurable 12-bit down counter that supports 7 frequency division factors.
The clock is provided by an internal independent 128 KHz RC oscillator (LSI); because the LSI is
independent of the main clock, it can run in Stop and Standby modes. IWDG is outside the main program and
can work completely independently. Therefore, it is used to reset the entire system when a problem occurs, or
as a free timer to provide timeout management for the application. It can be configured as software or
hardware to start the watchdog through the option byte. In Debug mode, the counter can be frozen.
l Window Watchdog
The window watchdog is a 7-bit down counter and can be set to free-running. It can be used to reset the entire
system when a problem occurs. It is driven by the main clock and has an early warning interrupt function; in
Debug mode, the counter can be frozen.
l SysTick Timer
This is a 32-bit optional increment or decrement counter that comes with the core controller. It is used to
generate SYSTICK anomalies (exception number: 15). It can be dedicated to the real-time operating system
(RTOS) to provide a "heartbeat" tick for the system, or it can be used as a standard 32-bit counter. It has an
automatic reload function and a programmable clock source.
1.4.13 Communication interface

1.4.13.1 Universal Synchronous/Asynchronous Receiver Transmitter (USART)
The product provides 1 group of Universal Synchronous/Asynchronous Receiver Transmitters (USART). It
supports full-duplex asynchronous communication, synchronous one-way communication and half-duplex
single-wire communication. It also supports LIN (Local Interconnect Network), compatible with ISO7816
smart card protocol and IrDA SIR ENDEC transmission codec specification, and modem (CTS/RTS
hardware flow control) operation. It also allows multi-processor communication. It uses a fractional baud rate
generator system and supports DMA operation continuous communication.
1.4.13.2 Serial Peripheral Interface (SPI)

1 serial peripherals interface (SPI) provide master or slave operation, dynamic switching. Support
multi-master mode, full-duplex or half-duplex synchronous transmission, support basic SD card and MMC
mode. Programmable clock polarity and phase, data bit width provides 8 or 16-bit selection, hardware CRC
generation/check for reliable communication, and continuous communication support for DMA operation.
1.4.14.3 I2C bus

1 I2C bus interface, able to work in multi-master mode or slave mode, complete with all I2C bus specific
timing, protocols, arbitration, etc., supporting both standard and fast communication speeds.
The I2C interface provides 7-bit or 10-bit addressing and supports dual slave address addressing in 7-bit slave
mode. A hardware CRC generator/checker is built-in.
1.4.14 General-purpose input and output (GPIO)

The system provides 3 groups of GPIO ports with a total of 18 GPIO pins. Each pin can be configured by
software as output (push-pull or open-drain), input (with or without pull-up or pull-down) or multiplexed
peripheral function port. Most GPIO pins are shared with digital or analog multiplexed peripherals. Except for
ports with analog input functions, all GPIO pins have high current passing capabilities. A locking mechanism is
provided to freeze the I/O configuration to avoid accidental writing to the I/O register.
V1.3 8
The I/O pins in the system is provided by VDD. Changing the VDD power supply will change the high
value of the I/O pin output level to adapt to the external communication interface level. Please refer to
the pin description for specific pins.
1.4.15 Operational amplifier/comparator (OPA)

The product has a built-in set of op-amps/comparators, with internal selection associated to the ADC and
TIM2 (CH1) peripherals, whose inputs and outputs can be selected by changing the configuration for
multiple channels. Support for external analog small signals are amplified and fed into the ADC to achieve
small signal ADC conversion, can also complete the signal comparator function, the comparison results from
the GPIO output or directly into the TIMx input channel.
1.4.16 1-wire serial debug interface (SDI)

The core comes with a 1-wire serial debug interface, SWIO pin (Single Wire Input Output). The default
debug interface pin function is turned on after system power on or reset.
V1.3 9
Chapter 2 Pinouts and pin definition
2.1 Pin arrangement

CH32V003F4P6
1 20
PD4/A7/UCK/T2CH1ETR/OPO/T1CH4ETR_ PD3/A4/T2CH2/AETR/UCTS/T1CH4_
2 19
PD5/A5/UTX/T2CH4_/URX_ PD2/A3/T1CH1/T2CH3_/T1CH2N_
3 18
PD6/A6/URX/T2CH3_/UTX_ PD1/SWIO/AETR2/T1CH3N/SCL_/URX_
4 17
PD7/NRST/T2CH4/OPP1/UCK_ PC7/MISO/T1CH2_/T2CH2_/URTS_
5 16
PA1/OSCI/A1/T1CH2/OPN0 PC6/MOSI/T1CH1CH3N_/UCTS_/SDA_
6 15
PA2/OSCO/A0/T1CH2N/OPP0/AETR2_ PC5/SCK/T1ETR/T2CH1ETR_/SCL_/UCK_/T1CH3_
7 14
VSS PC4/A2/T1CH4/MCO/T1CH1CH2N_
8 13
PD0/T1CH1N/OPN1/SDA_/UTX_ PC3/T1CH3/T1CH1N_/UCTS_
9 12
VDD PC2/SCL/URTS/T1BKIN/AETR_/T2CH2_/T1ETR_
10 11
PC0/T2CH3/UTX_/NSS_/T1CH3_ PC1/SDA/NSS/T2CH4_/T2CH1ETR_/T1BKIN_/URX_
CH32V003F4U6
20
19
18
17
16
PD6/A6/URX
PD5/A5/UTX
PD6/T2CH3_/UTX_
PD5/T2CH4_/URX_
PD4/OPO/T1CH4ETR_
PD2/A3/T1CH1/T2CH3_
PD2/T1CH2N_
PD4/A7/UCK/T2CH1ETR
PD3/A4/T2CH2/AETR
PD3/UCTS/T1CH4_
0
VSS
1 PD7/NRST/T2CH4 PD1/SWIO/AETR2 15
PD7/OPP1/UCK_ PD1/T1CH3N/SCL_/URX_
2 PA1/OSCI/A1 PC7/MISO/T1CH2_ 14
PA1/T1CH2/OPN0 PC7/T2CH2_/URTS_
3 PA2/OSCO/A0/T1CH2N PC6/MOSI/T1CH1CH3N_ 13
PA2/OPP0/AETR2_ PC6/UCTS_/SDA_
PC1/T2CH1ETR_/T1BKIN_/URX_
4 PC5/SCK/T1ETR/T2CH1ETR_ 12
VSS
PC5/SCL_/UCK_/T1CH3_
PC2/AETR_/T2CH2_/T1ETR_
5 PD0/T1CH1N/OPN1 PC4/A2/T1CH4/MCO 11
PC2/SCL/URTS/T1BKIN
PD0/SDA_/UTX_ PC4/T1CH1CH2N_
PC1/SDA/NSS/T2CH4_
PC3/T1CH3/T1CH1N_
PC0/NSS_/T1CH3_
PC0/T2CH3/UTX_
PC3/UCTS_
VDD
8
6
10
CH32V003A4M6
1 16
PC1/SDA/NSS/T2CH4_/T2CH1ETR_/T1BKIN_/URX_ PC0/T2CH3/UTX_/NSS_/T1CH3_
2 15
PC2/SCL/URTS/T1BKIN/AETR_/T2CH2_/T1ETR_ VDD
3 14
PC3/T1CH3/T1CH1N_/UCTS_ VSS
4 13
PC4/A2/T1CH4/MCO/T1CH1CH2N_ PA2/OSCO/A0/T1CH2N/OPP0/AETR2_
5 12
PC6/MOSI/T1CH1CH3N_/UCTS_/SDA_ PA1/OSCI/A1/T1CH2/OPN0
6 11
PC7/MISO/T1CH2_/T2CH2_/URTS_ PD7/NRST/T2CH4/OPP1/UCK_
7 10
PD1/SWIO/AETR2/T1CH3N/SCL_/URX_ PD6/A6/URX/T2CH3_/UTX_
8 9
PD4/A7/UCK/T2CH1ETR/OPO/T1CH4ETR_ PD5/A5/UTX/T2CH4_/URX_
V1.3 10
CH32V003J4M6
PD4/A7/UCK/T2CH1ETR/OPO/T1CH4ETR_
1 PD6/A6/URX/T2CH3_/UTX_ PD5/A5/UTX/T2CH4_/URX_ 8
PA1/OSCI/A1/T1CH2/OPN0 PD1/SWIO/AETR2/T1CH3N/SCL_/URX_
2 7
VSS PC4/A2/T1CH4/MCO/T1CH1CH2N_
3 PC2/SCL/URTS/T1BKIN 6
PA2/OSCO/A0/T1CH2N/OPP0/AETR2_
PC2/AETR_/T2CH2_/T1ETR_
4 5
VDD PC1/SDA/NSS/T2CH4_/T2CH1ETR_/T1BKIN_/URX_
Note: The multiplexed functions in the pin diagram are abbreviated.

Example: A: ADC, A7 (ADC_IN7)
T: TIME, T2CH4 (TIM2_CH4)
U: USART, URX (USART_RX)
OP: OPA, OPO (OPA_OUT), OPP1 (OPA_P1)
OSCI (OSCIN)
OSCO (OSCOUT)
SDA (I2C_SDA)
SCL (I2C_SCL)
SCK (SPI_SCK)
NSS (SPI_NSS)
MOSI (SPI_MOSI)
MISO (SPI_MISO)
AETR(ADC_ETR)
2.2 Pin description
Table 2-1 CH32V003xx pin definitions

Note: The pin function descriptions in the table below are for all functions and do not relate to specific model
products. Peripheral resources may vary between models, so please check the availability of this function
according to the product model resource table before viewing.
Pin No. Main
Pin Pin function
TSSOP2
QFN20
SOP16
Default alternate function Remapping function

SOP8
name type (after

0
reset)
- - 0 - VSS P VSS - -
UCK/T2CH1ETR(1)/A7/
8 1 18 8 PD4 I/O/A PD4 TIETR_2/T1CH4_3
OPO
9 2 19 8 PD5 I/O/A PD5 UTX/A5 T2CH4_3/URX_2
10 3 20 1 PD6 I/O/A PD6 URX/A6 T2CH3_3/UTX_2
11 4 1 - PD7 I/O/A PD7 NRST/T2CH4/OPP1 UCK_1/UCK_2/T2CH4_2
12 5 2 1 PA1 I/O/A PA1 T1CH2/A1/OPN0 OSCI/T1CH2_2
13 6 3 3 PA2 I/O/A PA2 TICH2N/A0/OPP0 OSCO/AETR2_1/TICH2N_2
14 7 4 2 VSS P VSS - -
- 8 5 - PD0 I/O/A PD0 TICH1N/OPN1 SDA_1/UTX_1/TICH1N_2
15 9 6 4 VDD P VDD - -
16 10 7 - PC0 I/O PC0 T2CH3 NSS_1/UTX_3/T2CH3_2
V1.3 11
/T1CH3_1
T1BKIN_1/T2CH4_1
1 11 8 5 PC1 I/O/FT PC1 SDA/NSS T2CH1ETR(1)_2/URX_3
/T2CH1ETR(1)_3/T1BKIN_3
AETR_1/T2CH2_1
2 12 9 6 PC2 I/O/FT PC2 SCL/URTS/T1BKIN /T1ETR_3/URTS_1
/T1BKIN_2
T1CH1N_1/UCTS_1
3 13 10 - PC3 I/O PC3 T1CH3
/T1CH3_2/T1CH1N_3
T1CH2N_1/T1CH4_2
4 14 11 7 PC4 I/O/A PC4 T1CH4/MCO/A2
/T1CH1_3
T2CH1ETR(1)_1/SCL_2
- 15 12 - PC5 I/O/FT PC5 SCK/T1ETR /SCL_3/UCK_3/T1ETR_1
/T1CH3_3/SCK_1
T1CH1_1/UCTS_2/SDA_2
/SDA_3/UCTS_3/T1CH3N_
5 16 13 - PC6 I/O/FT PC6 MOSI
3
/MOSI_1
T1CH2_1/URTS_2
6 17 14 - PC7 I/O PC7 MISO /T2CH2_3/URTS_3
/T1CH2_3/MISO_1
SCL_1/URX_1/T1CH3N_1
7 18 15 8 PD1 I/O/A PD1 SWIO/T1CH3N/AETR2
/T1CH3N_2
T2CH3_1/T1CH2N_3
- 19 16 - PD2 I/O/A PD2 T1CH1/A3
/T1CH1_2
- 20 17 - PD3 I/O/A PD3 A4/T2CH2/AETR/UCTS T2CH2_2/T1CH4_1
Note: 1. TIM2_CH1, TIM2_ETR;

2. The value after the underline of the remapping function indicates the configuration value of the
corresponding bit in the AFIO register. For example: T1CH4_3 indicates that the corresponding bit of the
AFIO register is configured as 11b;
3. Explanation of table abbreviations:
I = TTL/CMOS level Schmitt input.
O = CMOS level tri-state output.
P = power supply.
FT = 5V tolerant.
A = Analog signal input or output.
V1.3 12
2.3 Pin alternate functions

Note: The pin function descriptions in the table below are for all functions and do not relate to specific model products. Peripheral resources may vary between models,
so please check the availability of this function according to the product model resource table before viewing.
Table 2-2 CH32V003xx alternate function pin definitions

Alternate
Pin
ADC TIM1 TIM2 USART SYS I2C SPI SWIO OPA
PA1 A1 T1CH2/T1CH2_2 OSCI OPN0
PA2 A0/AETR2_1 T1CH2N/T1CH2N_2 OSCO OPP0
PC0 T1CH3_1 T2CH3/T2CH3_2 UTX_3 NSS_1
T2CH4_1/T2CH1ETR(1)_2
PC1 T1BKIN_1/T1BKIN_3 URX_3 SDA NSS
/T2CH1ETR(1)_3
T1BKIN/T1ETR_3
PC2 AETR_1 T2CH2_1 URTS/URTS_1 SCL
/T1BKIN_2
T1CH3/T1CH1N_1
PC3 UCTS_1
T1CH3_2/T1CH1N_3
T1CH4/T1CH2N_1
PC4 A2 MCO
/T1CH4_2/T1CH1_3
T1ETR/T1CH3_3
PC5 T2CH1ETR(1)_1 UCK_3 SCL_2/SCL_3 SCK/SCK_1
/T1ETR_1
PC6 T1CH1_1/T1CH3N_3 UCTS_2/UCTS_3 SDA_2/SDA_3 MOSI/MOSI_1
PC7 T1CH2_1/T1CH2_3 T2CH2_3 URTS_2/URTS_3 MISO/MISO_1
PD0 T1CH1N/T1CH1N_2 UTX_1 SDA_1 OPN1
T1CH3N/T1CH3N_1
PD1 AETR2 URX_1 SCL_1 SWIO
/T1CH3N_2
T1CH1/T1CH2N_3
PD2 A3 T2CH3_1
/T1CH1_2
PD3 A4/AETR T1CH4_1 T2CH2/T2CH2_2 UCTS
PD4 A7 T1ETR_2/T1CH4_3 T2CH1ETR(1) UCK OPO
PD5 A5 T2CH4_3 UTX/URX_2
PD6 A6 T2CH3_3 URX/UTX_2
PD7 T2CH4/T2CH4_2 UCK_1/UCK_2 NRST OPP1
Note: TIM2_CH1、TIM2_ETR.
V1.3 13
Chapter 3 Electrical characteristics
3.1 Test conditions

Unless otherwise specified and marked, all voltages are referenced to VSS.
All minimum and maximum values are guaranteed in the worst conditions of ambient temperature, supply voltage
and clock frequency. Typical values are based on normal temperature (25℃) and VDD = 3.3V or 5V environment,
which are given only as design guidelines.
The data based on comprehensive evaluation, design simulation or technology characteristics are not tested in
production. On the basis of comprehensive evaluation, the minimum and maximum values refer to sample tests.
Unless otherwise specified that is tested, the characteristic parameters are guaranteed by comprehensive evaluation
or design.
Power supply scheme:
Figure 3-1 Typical circuit for conventional power supply
VDD
2.7-5.5V
0.1uF VSS
3.2 Absolute maximum ratings

Stresses at or above the absolute maximum ratings listed in the table below may cause permanent damage to
the device.
Table 3-1 Absolute maximum ratings

Symbol Description Min. Max. Unit
TA Ambient temperature during operation -40 85 ℃
TS Ambient temperature during storage -40 125 ℃
VDD-VSS External main supply voltage (VDD) -0.3 5.5 V
Input voltage on the FT (5V tolerant) pin VSS-0.3 5.5 V
VIN
Input voltage on other pins VSS-0.3 VDD+0.3
|△VDD_x| Variations between different main power supply pins 50 mV
|△VSS_x| Variations between different ground pins 50 mV
V1.3 14
VESD(HBM) Electrostatic discharge voltage (human body model, non-contact) 4K V

IVDD Total current into VDD power lines (supply current) 100
IVss Total current out of VSS ground lines (outflow current) 80
Sink current on any I/O and control pin 20
II/O
Output current on any I/O and control pin -20 mA
OSC_IN pin of HSE +/-4
IINJ(PIN)
Injected current on other pins +/-4
∑IINJ(PIN) Total injected current on all I/Os and control pins +/-20
3.3 Electrical characteristics

3.3.1 Operating conditions
Table 3-2 General operating conditions
Symbol Parameter Condition Min. Max. Unit
FHCLK Internal AHB clock frequency 50 MHz
ADC not used 2.7 5.5
VDD Standard operating voltage V
Use ADC (recommended) 2.8 5.5
TA Ambient temperature -40 85 ℃
TJ Junction temperature range -40 85 ℃
Table 3-3 Power-on and power-down conditions

VDD rise time rate 0 ∞
tVDD us/V
VDD fall time rate 30 ∞
3.3.2 Embedded reset and power control block characteristics

Table 3-4 Reset and voltage monitor (For PDR, select high threshold gear)
Symbol Parameter Condition Min. Typ. Max. Unit
PLS[2:0] = 000 (rising edge) 2.85 V
PLS[2:0] = 000 (falling edge) 2.7 V
(1)
Programmable voltage
VPVD PLS[2:0] = 011 (rising edge) 3.5 V
detector level selection
V1.3 15

VPVDhyst PVD hysteresis 0.18 V
Power-on/power-down Rising edge 2.32 2.5 2.68 V
VPOR/PDR
reset threshold Falling edge 2.3 2.48 2.66 V
VPDRhyst PDR hysteresis 20 mV
Power on reset 12 17 22 mS
tRSTTEMPO
Other resets 300 uS
Note: 1. Normal temperature test value.
3.3.3 Embedded reference voltage

Table 3-5 Embedded reference voltage
VREFINT Internal reference voltage TA = -40℃~85℃ 1.17 1.2 1.23 V
ADC sampling time when
TS_vrefint reading the internal 3 500 1/fADC
reference voltage
3.3.4 Supply current characteristics

Current consumption is a comprehensive index of a variety of parameters and factors. These parameters and
factors include operating voltage, ambient temperature, I/O pin load, the software configuration of the
product, the operating frequency, flip rate of the I/O pin, the location of the program in memory and the
executed code, etc. The current consumption measurement method is as follows:
Figure 3-2 Current consumption measurement

Electric current
measurement
VDD
Electric current
measurement
The microcontroller is in the following conditions:

Normal temperature VDD = 3.3V or 5V case, when testing: all IO ports configured with pull-down inputs;
HSI on when testing HSE, HSE off when testing HSI, HSE= 24M, HIS= 24M (calibrated); system clock
source CLK*2 when FHCLK= 48MHz, 16MHz; clock on all peripherals only when turning on all peripherals.
Enables or disables power consumption of all peripheral clocks.
V1.3 16
Table 3-6-1 Typical current consumption in Run mode, data processing code runs from the internal Flash
(VDD = 3.3V)
Typ.
Symbol Parameter Condition All peripherals All peripherals Unit
enabled disabled
FHCLK = 48MHz 7.0 4.6
FHCLK = 24MHz 5.2 4.2
External clock FHCLK = 16MHz 4.6 3.8
FHCLK = 8MHz 3.1 2.7
Supply FHCLK = 750KHz 1.8 1.8
(1)
IDD current in Runs on the FHCLK = 48MHz 6.3 3.9 mA
Run mode high-speed internal FHCLK = 24MHz 4.3 3.1
RC oscillator (HSI). FHCLK = 16MHz 3.9 3.1
Uses AHB prescaler FHCLK = 8MHz 2.3 1.9
to reduce the
FHCLK = 750KHz 1.1 1.0
frequency.
Note: 1. The above are measured parameters.
2. When VDD < 3V, the current power consumption will increase.
Table 3-6-2 Typical current consumption in Run mode, data processing code runs from the internal Flash
(VDD = 5V)
Typ.
enabled disabled
FHCLK = 48MHz 8.0 5.6
FHCLK = 24MHz 6.4 5.6
Supply FHCLK = 750KHz 2.2 2.1
(1)
IDD current in Runs on the FHCLK = 48MHz 7.3 4.9 mA
Run mode high-speed internal FHCLK = 24MHz 5.3 4.1
RC oscillator (HSI). FHCLK = 16MHz 5.0 4.3
Uses AHB prescaler FHCLK = 8MHz 3.1 2.7
to reduce the
FHCLK = 750KHz 1.4 1.4
frequency.
Table 3-7-1 Typical current consumption in Sleep mode, data processing code runs from internal Flash or
SRAM (VDD = 3.3V)
Typ.
enabled disabled
IDD(1) Supply External clock FHCLK = 48MHz 4.9 2.5 mA
V1.3 17
current in FHCLK = 24MHz 2.9 1.7

Sleep mode FHCLK = 16MHz 2.5 1.7
(In this case, FHCLK = 8MHz 1.7 1.3
peripheral FHCLK = 750KHz 1.2 1.1
power supply Runs on the FHCLK = 48MHz 4.2 1.8
and clock are high-speed internal FHCLK = 24MHz 2.2 1.0
maintained) RC oscillator FHCLK = 16MHz 1.8 1.0
(HSI). Uses AHB FHCLK = 8MHz 1.0 0.6
prescaler to reduce
FHCLK = 750KHz 0.4 0.4
the frequency.
Table 3-7-2 Typical current consumption in Sleep mode, data processing code runs from internal Flash or
SRAM (VDD = 5V)
Typ.
enabled disabled
FHCLK = 48MHz 4.9 2.5
FHCLK = 24MHz 2.9 1.7
Supply
current in
Sleep mode
FHCLK = 750KHz 1.2 1.1
(1)
(In this case,
IDD Runs on the FHCLK = 48MHz 4.2 1.8 mA
peripheral
high-speed internal FHCLK = 24MHz 2.2 1.0
power supply
RC oscillator FHCLK = 16MHz 1.8 1.0
and clock are
(HSI). Uses AHB FHCLK = 8MHz 1.0 0.6
maintained)
prescaler to reduce
FHCLK = 750KHz 0.4 0.4
the frequency.
Table 3-8 Typical current consumption in Standby mode

Symbol Parameter Condition Typ. Unit
VDD = 3.3V 10.5
LSI on
Supply current in VDD = 5V 11.1
IDD uA
Standby mode VDD = 3.3V 9.0
LSI off
VDD = 5V 9.6
Note: The above are measured parameters.
3.3.5 External clock source characteristics

Table 3-9 From external high-speed clock
FHSE_ext External clock frequency 4 24 25 MHz
(1)
VHSEH OSC_IN input pin high level 0.8VDD VDD V
V1.3 18
voltage
OSC_IN input pin low-level
VHSEL(1) 0 0.2VDD V
voltage
Cin(HSE) OSC_IN input capacitance 5 pF
DuCy(HSE) Duty cycle 40 50 60 %
IL OSC_IN input leakage current ±1 uA
Note: 1. Failure to meet this condition may cause level recognition error.
Figure 3-3 External high-frequency clock source circuit

External clock source
fHS E_ext
OSC_IN
OSC_OUT
Table 3-10 High-speed external clock generated from a crystal/ceramic resonator

FOSC_IN Resonator frequency 4 24 25 MHz
RF Feedback resistance 250 kΩ
Recommended load
C capacitance and corresponding RS = 60Ω(1) 20 pF
crystal series impedance RS
I2 HSE drive current VDD = 3.3V，20p load 0.32 mA
gm Oscillator transconductance Startup 6.8 mA/V
VDD is stable, 24M
tSU(HSE) Startup time 2 ms
crystal
Note 1: It is recommended that the ESR of 25M crystal should not exceed 60 Ω, and it can be relaxed if it is
lower than 25M.
Circuit reference design and requirements:

The load capacitance of the crystal is subject to the recommendation of the crystal manufacturer, generally
CL1 = CL2.
Figure 3-4 Typical circuit of external 24M crystal
CL1
OSC_IN
24MHz
Crystal
Oscillator
OSC_OUT
CL2
V1.3 19
3.3.6 Internal clock source characteristics

Table 3-11 Internal high-speed (HSI) RC oscillator characteristics
FHSI Frequency (after calibration) 24 MHz
DuCyHSI Duty cycle 45 50 55 %
Accuracy of HSI oscillator (after TA = 0℃～70℃ -1.2 1.6 %
ACCHSI
calibration) TA = -40℃～85℃ -2.2 2.2 %
HSI oscillator startup
tSU(HSI) 10 us
stabilization time
IDD(HSI) HSI oscillator power consumption 120 180 270 uA
Table 3-12 Internal low-speed (LSI) RC oscillator characteristics

FLSI Frequency 100 128 150 KHz
DuCyLSI Duty cycle 45 50 55 %
LSI oscillator startup
tSU(LSI) 80 us
stabilization time
LSI oscillator power
IDD(LSI) 1.5 uA
consumption
3.3.7 Wakeup time from low-power mode

Table 3-13 Wakeup time from low-power mode(1)
Symbol Parameter Condition Typ. Unit
twusleep Wakeup from Sleep mode Wake up using HSI RC clock 30 us
LDO stabilization time + HSI RC
tWUSTDBY Wakeup from Standby mode clock wake up + code load time(2) 200 us
(take 128K as example)
Note: The above parameters are measured parameters.
3.3.8 Memory characteristics

Table 3-14 Flash memory characteristics
Page (64 bytes) programming
tERASE_64 TA = -20℃～85℃ 2.4 3.1 ms
time
tERASE Page (64 bytes) erase time TA = -20℃～85℃ 2.4 3.1 ms
tprog 16-bit programming time TA = -20℃～85℃ 2.4 3.1 ms
tME Whole chip erase time TA = -20℃～85℃ 2.4 3.1 ms
Vprog Programming voltage 2.8 5.5 V
Table 3-15 Flash memory endurance and data retention

NEND Endurance TA = 25℃ 10K 80K(1) times
V1.3 20
tRET Data retention 10 year

Note: The endurance parameter is actual measured, which is not guaranteed.
3.3.9 I/O port characteristics

Table 3-16 General-purpose I/O static characteristics
Standard I/O pin, input high level 0.22*(VDD-
VDD+0.3 V
voltage 2.7)+1.55
VIH
0.22*(VDD-
FT I/O pin, input high level voltage 5.5 V
2.7)+1.55
Standard I/O pin, input low-level 0.19*(VDD-
-0.3 V
voltage 2.7)+0.65
VIL
0.19*(VDD-
FT I/O pin, input low-level voltage -0.3 V
2.7)+0.65
Vhys Schmitt trigger voltage hysteresis 150 mV
Standard I/O port 1

Ilkg Input leakage current uA
FT I/O port 3
RPU Weak pull-up equivalent resistance 35 45 55 kΩ
RPD Weak pull-down equivalent resistance 35 45 55 kΩ
CI/O I/O pin capacitance 5 pF
Output drive current characteristics

GPIO (General-Purpose Input/Output Port) can sink or output up to ±8mA current, and sink or output
±20mA current (not strictly to VOL/VOH). In user applications, the total driving current of all I/O pins cannot
exceed the absolute maximum ratings given in Section 3.2:
Table 3-17 Output voltage characteristics

VOL Output low level when 8 pins are sunk TTL port, II/O = +8mA 0.4
V
VOH Output high level when 8 pins are sourced 2.7V< VDD <5.5V VDD-0.4
VOL Output low level when 8 pins are sunk CMOS port, II/O = +8mA 0.4
V
VOH Output high level when 8 pins are sourced 2.7V< VDD <5.5V 2.3
VOL Output low level when 8 pins are sunk II/O = +20mA 1.3
V
VOH Output high level when 8 pins are sourced 2.7V< VDD <5.5V VDD-1.3
Note: In the above conditions, if multiple I/O pins are driven at the same time, the total current cannot exceed
the absolute maximum ratings given in Table 3.2. In addition, when multiple I/O pins are driven at the same
time, the current on the power/ground point is very large, which will cause the voltage drop to make the
internal I/O voltage not reach the power supply voltage in the table, resulting in the drive current being less
than the nominal value.
V1.3 21
Table 3-18 Input/output AC characteristics

MODEx[1:0]
configuration
Fmax(I/O)out Maximum frequency CL = 50pF, VDD = 2.7-5.5V 2 MHz
10
tf(I/O)out Output high to low fall time 125 ns
（2MHz） CL = 50pF, VDD = 2.7-5.5V
tr(I/O)out Output low to high rise time 125 ns
01
tf(I/O)out Output high to low fall time 25 ns
（10MHz） CL = 50pF, VDD = 2.7-5.5V
tr(I/O)out Output low to high rise time 25 ns
11
tf(I/O)out Output high to low fall time CL = 50pF, VDD = 2.7-5.5V 10 ns
（30MHz）
tr(I/O)out Output low to high rise time CL = 50pF, VDD = 2.7-5.5V 10 ns
The EXTI controller detects
tEXTIpw the pulse width of the 10 ns
external signal
3.3.10 NRST pin characteristics

Table 3-19 External reset pin characteristics
NRST input low-level
VIL(NRST) -0.3 0.28*(VDD-1.8)+0.6 V
voltage
NRST input high-level
VIH(NRST) 0.41*(VDD-1.8)+1.3 VDD+0.3 V
voltage
NRST Schmitt Trigger
Vhys(NRST) 150 mV
voltage hysteresis
Weak pull-up equivalent
RPU(1) 35 45 55 kΩ
resistance
Note: 1. The pull-up resistor is a real resistor in series with a switchable PMOS implementation. The
resistance of this PMOS/NMOS switch is very small (approximately 10%).
Circuit reference design and requirements:

Figure 3-5 Typical circuit of external reset pin
VDD
RPU
NRST
0.1μF
3.3.11 TIM timer characteristics

Table 3-20 TIMx characteristics
V1.3 22
1 tTIMxCLK
tres(TIM) Timer reference clock
fTIMxCLK = 48MHz 13.9 ns
Timer external clock frequency on 0 fTIMxCLK/2 MHz
FEXT
CH1 to CH4 fTIMxCLK = 48MHz 0 36 MHz
ResTIM Timer resolution 16 位
16-bit counter clock cycle when the 1 65536 tTIMxCLK
tCOUNTER
internal clock is selected fTIMxCLK = 48MHz 0.0139 910 us
65535 tTIMxCLK
tMAX_COUNT Maximum possible count
fTIMxCLK = 48MHz 59.6 s
3.3.12 I2C interface characteristics

Figure 3-6 I2C bus timing diagram
tw(SCKH)
tr(SCL)
tw(SCKL)
SCL th(STA) tf(SCL)
tSU(STO)
tSU(SDA) th(SDA)
tf(SDA)
Repeat start condition
SDA tw(STO:STA)
tr(SDA) Stop condition
Start condition tSU(STA)
Table 3-21 I2C interface characteristics

Standard I2C Fast I2C
Symbol Parameter Unit
Min. Max. Min. Max.
tw(SCKL) SCL clock low time 4.7 1.2 us
tw(SCKH) SCL clock high time 4.0 0.6 us
tSU(SDA) SDA data setup time 250 100 ns
th(SDA) SDA data hold time 0 0 900 ns
tr(SDA)/tr(SCL) SDA and SCL rise time 1000 20 ns
tf(SDA)/tf(SCL) SDA and SCL fall time 300 ns
th(STA) Start condition hold time 4.0 0.6 us
tSU(STA) Repeated start condition setup time 4.7 0.6 us
tSU(STO) Stop condition setup time 4.0 0.6 us
Time from stop condition to start condition
tw(STO:STA) 4.7 1.2 us
(bus free)
Cb Capacitive load for each bus 400 400 pF
V1.3 23
3.3.13 SPI interface characteristics

Figure 3-7 SPI timing diagram in Master mode
tSCK tr(SCK)
tf(SCK)
SCK Output
CPHA=0
CPOL=0
CPHA=0
CPOL=1
tw(SCKH)
tw(SCKL)
SCK Output
CPHA=1
CPOL=0
CPHA=1
CPOL=1
th(MI)
tsu(MI)
MISO Input Input highest bit Input 6-1 bit Input lowest bit
tV(MO) th(MO)
MOSI Output Output highest bit Output 6-1 bit Output lowest bit
Figure 3-8 SPI timing diagram in Slave mode (CPHA = 0)

NSS Input
th(NSS)
tSCK tr(SCK)
tf(SCK)
SCK Input tsu(NSS)
CPHA=0
CPOL=0
CPHA=0
CPOL=1
ta(SO) tV(SO)
th(SO)
tdis(SO)
MISO Output Output highest bit Output 6-1 bit Output lowest bit
tsu(SI) th(SI)
MOSI Input Input highest bit Input 6-1 bit Input lowest bit
V1.3 24
Figure 3-9 SPI timing diagram in Slave mode (CPHA = 1)

NSS Input
th(NSS)
tSCK tr(SCK)
tf(SCK)
SCK Input tsu(NSS)
CPHA=1
CPOL=0
CPHA=1
CPOL=1
ta(SO) tV(SO) th(SO) tdis(SO)
MISO Output Output highest bit Output 6-1 bit Output lowest
bit
tsu(SI) th(SI)
MOSI Input Input highest bit Input 6-1 bit Input lowest bit
Table 3-22 SPI interface characteristics

Master mode 24 MHz
fSCK/tSCK SPI clock frequency
Slave mode 24 MHz
tr(SCK)/tf(SCK) SPI clock rise and fall time Load capacitance:C = 30pF 20 ns
tSU(NSS) NSS setup time Slave mode 2tPCLK ns
th(NSS) NSS hold time Slave mode 2tPCLK ns
Master mode, fPCLK = 48MHz,
tw(SCKH)/tw(SCKL) SCK high and low time 30 70 ns
Prescaler factor = 2
tSU(MI) Master mode 5 ns
Data input setup time
tSU(SI) Slave mode 5 ns
th(MI) Master mode 5 ns
Data input hold time
th(SI) Slave mode 4 ns
ta(SO) Data output access time Slave mode, fPCLK = 24MHz 0 1tPCLK ns
tdis(SO) Data output disable time Slave mode 0 10 ns
tV(SO) Slave mode (After enable edge) 5 ns
Data output valid time
tV(MO) Master mode (After enable edge) 5 ns
th(SO) Slave mode (After enable edge) 2 ns
Data output hold time
th(MO) Master mode (After enable edge) 0 ns
3.3.14 10-bit ADC characteristics

Table 3-23 ADC characteristics
VDD Supply voltage 2.8 5.5 V
IDD Supply current 370 uA
V1.3 25
VDD = 2.8 to 5.5V 1 6

fADC ADC clock frequency VDD = 3.2 to 5.5V 1 12 MHz
VDD = 4.5 to 5.5V 1 24
VAIN Conversion voltage range VSS VDD V
Internal sample and hold
CADC 3 pF
capacitor
fADC = 4 MHz 285
fADC = 6 MHz 430
fS Sampling rate KHz
fADC = 12 MHz 857
fADC = 24 MHz 1710
fADC = 4 MHz 0.75
ts Sampling time fADC = 6 MHz 0.5 us
fADC = 12 MHz 0.25
tSTAB Power-on time 7 us
fADC = 4 MHz 3.5 us
Total conversion time fADC = 6 MHz 2.33 us
tCONV
(including sampling time) fADC = 12 MHz 1.17 us
- 14 1/fADC
Note: Above parameters are guaranteed by design.
Table 3-24 ADC error (fADC = 12MHz:RAIN < 10kΩ,VDD > 2.9V)(fADC = 24MHz:RAIN < 3kΩ,VDD = 5V)
ET Total data deviation fADC = 12 MHz 2 4
ETF24 fADC = 24MHz total data deviation fADC = 24 MHz 3 6
EO Misalignment error fADC = 12 MHz 1 3
LSB
EG Gain error fADC = 12 MHz 1 2
ED Differential nonlinearity error fADC = 12 MHz 0.5 2
EL Integral nonlinearity error fADC = 12 MHz 0.6 2.5
Note: Source simulation.
Cp represents the parasitic capacitance on the PCB and the pad (about 5pF), which may be related to the
quality of the pad and PCB layout. A larger Cp value will reduce the conversion accuracy, the solution is to
reduce the fADC value.
Figure 3-10 ADC typical connection diagram
VDD
VT Sample and hold ADC converter

RAIN AINx 0.6V RADC
10-bit
converter
VT CADC
CP 0.6V
VAIN Parasitic
capacitance
V1.3 26
Figure 3-11 Analog power supply and decoupling circuit reference
VDD
0.1uF
VSS
3.3.15 OPA characteristics

Table 3-25 OPA characteristics
VDD Supply voltage 2.8 5.5 V
Common mode input
CMIR 0 VDD V
voltage
VIOFFSET Input offset voltage 3 10 mV
ILOAD Drive current 1.5 mA
IDDOPAMP Current consumption No load, static mode 273 uA
Common mode rejection 81
CMRR(1) @1KHz dB
ratio
PSRR(1) Power supply rejection ratio @1KHz 88 dB
AV(1) Open loop gain CLOAD = 50pF 105 dB
(1)
GBW Unit gain bandwidth CLOAD = 50pF 12 MHz
(1)
PM Phase margin CLOAD = 50pF 75 deg
(1)
SR Slew rate limited CLOAD = 50pF 7.7 V/us
Setup time from shutdown to
tWAKU(1) Input V DD /2, C LOAD =50pF,R LOAD =4kΩ 520 ns
wake up, 0.1%
RLOAD Resistive load 4 kΩ
CLOAD Capacitive load 50 pF
High saturation output RLOAD = 4kΩ, input VDD VDD-180
VOHSAT(2) mV
voltage RLOAD = 20kΩ, input VDD VDD-36
Low saturation output RLOAD = 4kΩ, input 0 5
VOLSAT(2) mV
voltage RLOAD = 20kΩ, input 0 5
RLOAD = 4kΩ, @1KHz 83
Equivalent input voltage
EN(1) nv
noise RLOAD = 4kΩ, @10KHz 28
Hz
Note: 1. Design parameters are guaranteed.

2. The load current limits the saturated output voltage.
V1.3 27
Chapter 4 Package and ordering information
Packages
Part No. Package Body size Lead pitch Description Packing type
Thin Shrink Small Outline
CH32V003F4P6 TSSOP20 4.4*6.5mm 0.65mm Tape & Reel
Package
CH32V003F4U6 QFN20 3.0*3.0mm 0.4mm Quad Flat No-lead Package Tape & Reel
CH32V003A4M6 SOP16 3.9*10mm 1.27mm Small Outline Package Tube
CH32V003J4M6 SOP8 3.9*5.0mm 1.27mm Small Outline Package Tape & Reel
Note: 1. The packing type of QFP/QFN is usually tray. Please confirm with the packaging factory for specific
part number.
2. Size of tray: The size of tray is generally a uniform size (322.6*135.9*7.62). There are differences in
the size of the restriction holes for different package types, and there are differences between different
packaging factories for tubes, please confirm with the manufacturer for details.
V1.3 28
Note: All dimensions are in millimeters. The pin center spacing values are nominal values, with no error.
Other than that, the dimensional error is not greater than the greater of ±0.2mm or 10%.
Figure 4-1 TSSOP20 package
Figure 4-2 QFN20 package
V1.3 29
Figure 4-3 SOP16 package
Figure 4-4 SOP8 package
V1.3 30
Series product naming rules

Example: CH32 V 3 03 R 8 T 6
Device family
F = ARM-based
V = QingKe RISC-V-based
Product type
0 = QingKe V2 core
1 = M3/ QingKe V3A core, clock speed @72M
2 = M3/ QingKe V4B_C core, clock speed @144M
3 = QingKe V4F floating-point core, clock speed @144M
Device subfamily
03 = General-purpose
05 = Connectivity (USB high-speed, SDIO, dual CAN)
07 = Interconnectivity (USB high-speed, dual CAN, Ethernet, DVP, SDIO, FSMC)
08 = Wireless (BLE5.3, CAN, USB, Ethernet)
Pin count
J = 8 pins A = 16 pins F = 20 pins
G = 28 pins K = 32 pins T = 36 pins
C = 48 pins R = 64 pins W = 68 pins
V = 100 pins Z = 144 pins
Flash memory size

4 = 16 Kbytes of Flash memory
B = 128 Kbytes of Flash memory
C = 256 Kbytes of Flash memory
Package
T = LQFP
U = QFN R = QSOP
P = TSSOP M = SOP
Temperature range
6 = -40℃～85℃ (industrial-grade)
7 = -40℃～105℃ (automotive-grade 2)
3 = -40℃～125℃ (automotive-grade 1)
D = -40℃～150℃ (automotive-grade 0)
V1.3 31

CH32V003DS0

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CH32V003 Datasheet

1.1 System architecture

Figure 1-1 System block diagram

FLASH @VDD VDD : 2.7V~5.5V

OPAPx GPIOA PA1 ~ PA2

TIM2_CH1 GPIOD PD0 ~ PD7

4 channels, ETR TIM2

1.2 Memory map

Figure 1-2 Memory address map

1.3 Clock tree

Figure 1-3 Clock tree block diagram

to pwr(low power clock source)

peripheral clock enable

peripheral clock enable

1.4 Functional description

1.4.2 On-chip memory and boot mode

1.4.3 Power supply scheme

1.4.4 Power supply monitor

1.4.5 Voltage regulator

1.4.6 Low-power mode

1.4.7 Fast Programmable Interrupt Controller (PFIC)

1.4.8 External interrupt/event controller (EXTI)

1.4.9 General-purpose DMA controller

USART, I2C and SPI.

1.4.10 Clock and boot

1.4.11 Analog-to-digital converter (ADC)

1.4.12 Timer and watchdog

1.4.13 Communication interface

1.4.13.2 Serial Peripheral Interface (SPI)

1.4.14.3 I2C bus

1.4.14 General-purpose input and output (GPIO)

1.4.15 Operational amplifier/comparator (OPA)

1.4.16 1-wire serial debug interface (SDI)

Chapter 2 Pinouts and pin definition

2.1 Pin arrangement

Note: The multiplexed functions in the pin diagram are abbreviated.

2.2 Pin description

Table 2-1 CH32V003xx pin definitions

Default alternate function Remapping function

name type (after

Note: 1. TIM2_CH1, TIM2_ETR;

2.3 Pin alternate functions

Table 2-2 CH32V003xx alternate function pin definitions

Chapter 3 Electrical characteristics

3.1 Test conditions

Power supply scheme:

Figure 3-1 Typical circuit for conventional power supply

3.2 Absolute maximum ratings

Table 3-1 Absolute maximum ratings

VESD(HBM) Electrostatic discharge voltage (human body model, non-contact) 4K V

3.3 Electrical characteristics

Table 3-3 Power-on and power-down conditions

3.3.2 Embedded reset and power control block characteristics

PLS[2:0] = 110 (falling edge) 3.9 V

3.3.3 Embedded reference voltage

3.3.4 Supply current characteristics

Figure 3-2 Current consumption measurement

The microcontroller is in the following conditions: