2.9 Problems Solved
2.9 Problems Solved
2.9 Problems Solved
2.9 Problems
Use the technology parameters for transistors, wires and other elements given in this chapter where appropriate. Q2-1. Assume that Vgs = 1V, compute the drain current through n-type transistors of these sizes at Vds values of 0.5 V, 0.75 V, and 1 V: a. b. c. d. W/L = 5/2 W/L = 8/2 W/L = 12/2 W/L = 25/2
Sol: For 90nm, Vt= 0.14 V, k`=13A/V2 a. at Vds=0.5 V, W/L=5/2 Vds = Vgs Vt 0.5 < 1 0.14 0.5 < 0.86 Hence transistor will operate in linear region
W I d = k` L 1 2 (V gs Vt )Vds 2 V ds
I d = 9.9125uA
at Vds=0.75 V, W/L=5/2
Vds = Vgs Vt 0.75 < 1 0.14
W I d = k` L
1 2 (V gs Vt )Vds 2 V ds
at Vds=1 V, W/L=5/2
Vds = Vgs Vt 1 > 1 0.14 1 > 0.86 Hence transistor will operate in saturation region
Id =
1 W k ` (V gs Vt ) 2 2 L
]
[ ]
Id =
1 (13 x 10 2
5 (1 0 . 14 ) 2 2
b. at Vds=0.5 V, W/L=8/2
Vds = Vgs Vt 0.5 < 1 0.14 0.5 < 0.86 Hence transistor will operate in linear region W I d = k` L 1 2 (V gs Vt )Vds 2 V ds
8 1 I d = (13 x10 6 )( ) (1 0.14)(0.5) (0.5) 2 2 2 I d = (5.2 x10 5 )[(0.86)(0.5) 0.125] I d = (5.2 x10 5 )[0.305] I d = 15.86uA
at Vds=0.75 V, W/L=8/2
Vds = Vgs Vt 0.75 < 1 0.14 0.75 < 0.86 Hence transistor will operate in linear region W I d = k` L 1 (V gs Vt )Vds V 2 ds 2
at Vds=1 V, W/L=8/2
Vds = Vgs Vt 1 > 1 0.14 1 > 0.86 Hence transistor will operate in saturation region Id = Id = 1 W k ` (V gs Vt ) 2 2 L
] ]
c. at Vds=0.5 V, W/L=12/2
Vds = Vgs Vt 0.5 < 1 0.14 0.5 < 0.86 Hence transistor will operate in linear region W I d = k` L 1 2 (V gs Vt )Vds 2 V ds
at Vds=0.75 V, W/L=12/2
Vds = Vgs Vt 0.75 < 1 0.14 0.75 < 0.86 Hence transistor will operate in linear region W I d = k` L 1 2 (V gs Vt )Vds 2 V ds
at Vds=1 V, W/L=12/2
Vds = Vgs Vt 1 > 1 0.14 1 > 0.86 Hence transistor will operate in saturation region Id = Id = 1 W k ` (V gs Vt ) 2 2 L
] ]
d. at Vds=0.5 V, W/L=25/2
Vds = Vgs Vt 0.5 < 1 0.14 0.5 < 0.86 Hence transistor will operate in linear region
W I d = k` L
I d = (13 x10 6 )(
at Vds=0.75 V, W/L=25/2
Vds = Vgs Vt 0.75 < 1 0.14 0.75 < 0.86 Hence transistor will operate in linear region W I d = k` L 1 2 (V gs Vt )Vds 2 V ds 25 1 ) (1 0.14)(0.75) (0.75) 2 2 2
I d = (13 x10 6 )(
at Vds=1 V, W/L=25/2
Vds = Vgs Vt 1 > 1 0.14 1 > 0.86 Hence transistor will operate in saturation region Id = Id = 1 W k ` (V gs Vt ) 2 2 L
] ]
Q2-2. Design the static complementary pullup and pulldown networks for these logic expressions: a. (a + b + c)` b. [(a + b)c]` c. (a+b)(c+d) Sol: a. (a + b + c)` = a`b`c` . For Pullup Network = a+b+c ..... For Pulldown Network
A B C Vout
VDD
b. [(a + b)c]` = (a + b)` + c` = a`b` + c` .For pullup network = (a + b)c . For pulldown network
VSS VDD cc
a c b Vout a b
Vss
c. (a+b)(c+d) = a(c + d) + b(c + d) . For pullup network = [(a + b)(c + d)]` = [(a + b)` + (c + d)`] = [a`b` + c`d`] For pulldown network VSS
d Y
VDD
Q2-3. Write the defining logic equation for each complex gate below: a. b. c. d. e. Sol: AOI-22 OAI-22 AOI-212 OAI-321 AOI-2222
a) AOI-22
b) OAI-22
c) AOI-212
d) OAI-321
e) AOI-2222
Q2-6. What is the difference in the fall time of a two input, static complementary NOR gate (assuming a minimum-size load capacitance), when one pulldown and when two pulldowns are activated? Sol: Expression for NOR gate is:
v = V max e
t D
-------------------------- (1)
Vout = Vdd .e
tf RC
------------------------ (2)
Replacing Internal Resistance of n-MOS Transistor, when any one of pulldowns are activated.
Here total resistance is: R=(Rn + RL) & C=CL eq(2) becomes
Vout = Vdd .e
tR ( Rn + RL ) C L
-------------------- (3)
Considering the falling edge, the falling time is considered to be from 90% of Vmax (i.e. VDD) to 10% of Vmax, hence we have to calculate Time required for (10% - 90%) of Vdd (i.e. 80% of Vdd).
Hence VDD
tf ( RPn + RL ) C L
0 .1 0 .9 = e
tf ( Rn + RL ) C L
ln(
0 .1 )( Rn + R L )C L = t f 0 .9
t F = 2 .2 ( R P + R L ) C L
Assuming CL = minimum =1
t F = 2 .2 ( R n + R L )
Vout = Vdd .e
tf RC
------------------------ (2)
Replacing Internal Resistance of n-MOS Transistor, when any both of pulldowns activated: are
As both transistors are same (i.e. nMOS) having same characteristics and internal structure, hence both have same internal resistance
R = Rn || Rn
1 1 1 = + R Rn Rn 1 2 = R Rn R = 0.5 Rn
Here total resistance is: R=(R + RL) & C=CL eq(2) becomes
Vout = Vdd .e
tR ( 0.5 Rn + RL ) C L
-------------------- (3)
Considering the falling edge, the falling time is considered to be from 90% of Vmax (i.e. VDD) to 10% of Vmax, hence we have to calculate Time required for (10% - 90%) of Vdd (i.e. 80% of Vdd).
Hence VDD
tf ( 0.5 RPn + RL ) C L
0 .1 0 .9 = e
tf ( 0.5 Rn + RL ) C L
ln(
0 .1 )(0.5 Rn + R L )C L = t f 0 .9
t F = 2 . 2 ( 0 . 5 R n + R L )C L
Assuming CL = minimum = no effect
t F = 2 .2 ( 0 .5 R n + R L )
Rn + RL ) 2 R + 2 RL t F = 2 .2 ( n ) 2 t F = 1.1( R n + 2 R L ) t F = 2 .2 ( t F = 1.1( R n + 2 R L )
Problem Statement2-3:
If the input to an inverter is a ramp and not a step is the fall time calculation of tf=2.2(Rn+RL) CL optimistic or pessimistic? Explain your answer.
Solution:
Since ramp is a constantly increasing test input which means it cannot give any information about delay measurement. And moreover the linearly increasing input voltage may destroy the inverter at some voltage level. Therefore from these aspects the result of above equation may lead us to pessimistic result.