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7.15 8051/8031 cycles. theand 7.17. 805A used
PSW to
When Fig.iscapacitance
7.18 whenA is
machine bus 0 the
B, in
reset.ACC,shown Figure busaddress
FF F7 EF E7 DF D7 CF C7 BE B7 AF A7 9F 97 for port
supply data of
PCON pin. moremanual 0, one-Sixth
PC, is uF
cycles. =
from this or of diagram A10 andof ALE
twoandvalues terminals. clock low-byte
address
drawn to respect
capacito. It
for reset circuit Ap- ofrate
reset 24 to
is
1W. with
current
high
power-on aboutuF thethe A, constant
TH1. the resetground10 demultiplexing
provides
bus
80S1
Microcontroller
Architecture map is
aboutspecified So delay
125-mA pin lost.power-on and
the address
a
memory is RST across
THÌ as provide 0
Port with
ratingare such be RST as
when
SFR A dissipation will The between addedformemory. usedperiodically
voltage. voltagesmicrocontroller components
TL1 DPH
7.14 only to 0007H.
register is
used is
the connected switch O
Fig, supply 8051, is external
port
powerAll is ALE activated
TLO DPL the SP These push-button 1,
supply.
the in of =
V 8051 withALE
Enable)
+5 maximumresets values content
is pin.
is
TMOD to 8.2K interfacing
SP connected for reset RST WhenALE
pin pin all theof A Latch
the ground to reset, resistance
input to circuit. D. Usually,
ACC PSW P2/ SCON P1 TCON PO and ways and Vcc
IE 0000H to
fromreset(Address
P3
RST isMicrocontroller is
is microcontroller
pin a two
microcontroller
D,
is pull-down busbus.
F8 FO E8 EO D8 DO C8 CO B8 B0 A8 A0 98 90 88 80 This This The are are manual
Connected datadata
frequency.
DPTR ALE
Vss RSTThere
Vcc and ne
A the
 Fig.7.13 Bit addressabl
Each of the
to as bits
can also be20.0-20.7 and bits 8-FH are the same as 21.0-21.7, and so on. 16-bytes im his
addressed as a byte. RAM. On the.
Scratch Pad
stack pointer hasArea
general purpose
The memory locations 30H-7FH areshould be left aside to prevent Sp
been initializedon-chip
to this area,
RAM
enough
are
bytes
used for special function registers as
dataindestFig,
shown
The upper 128 bytes of
Actually, only 25 of these the
bytes are used. The other bytes are reserved for advanced versione of
the
controller. These bytes are associated
with registers whích are used for different functions
and opera
microcontroller. ne bit ad£dressable and some of these bytes
COntroller. Some of these rerista are addressable.

74 PIN DIAGRAM OF 8051 MICROCONTROLLER

Ine s0sl microcontroller is available in DIP. OFP and LLCpackages. This is a 40pin IC. There a
O-Dtports Po, P,P, and P,. Therefore. total 32 pins are covered for 4-ports. The remain1ng 8pins at
(Power supply), Vss (ground), crystal oscillator pins XTALI and XTAL2, RST (Reset), PSEN Pr
Store Enable), ALE (Address Latch Enable), and EA(External Access) respectively. The Pin dage
8051microcontroller is depicted in Fig, 7.15 and schematic pin diagram is illustrated in Fig.7.16. Tk
discussions of all these pins are explained in this section.
 |7.43
of location asaddressed
consists one to be
0OHalso
than
Bank-3 bank
from addressed
can
more
ADDRESSABLE
R7 R6 R5 R1 RO start be 0-7
SEGMENT
17
REGISTER
R4 R3 R2
Each can
SCRATCH
5F BANKS bits
PADAREA BIT
addressable
to use thatbe Hence,
1FH 1EH 1DH1CH 1BH1AH 19H 18H 07H. oncetoorder blockcan
77 6F 67 57
4F 47 3F 37 2F 27 1F OF 07 R7-RO to incremented bits used.
00H in
...7F indirectR7 R6 R5 R4 R3 R2 R1 RO
Bank-2
&-registers RAM.aformThe
Therefore,
2FH.are
8051
Microcontroler
Architecture addresses 2OH-2FH
instructio
and 17H 16H 15H 13H is the
14H 12H 11H 10H it bank.of to
direct
of registerand location
20H
RAM
banks addressed
07Hregister contain specific
Bank-1
8BYTES
R7 R6 R5 R4 R3 R2 R1 RO Four its locationdifferent
3 2 1 of and second 16-bytes
128-bytes 7.12 selected be bits,
OFH OEH ODH 0CH 0BH 0AH 09H 08H
Fig. to can the
theato
pointer nextbytes
initialized access
7.11 of(R) The
is
Fig. Bank-0 stack The
Bank-0 registerA4rea
bits.For
R7 R6 R5 R4 R3 R2 R1 RO Rq.
the be Addressa
0. default should
to initializes 13.
individu
78 70 68 60 58 50 48 40 38
30 28 20 18 10 08 00
Ro 7.
07H 06H 05H 04H 03H 02H 01H 00H registersfirst Fjg.
By the SP in
time.
is he
Aeset
yte ch or Cted
A, S
 Operau1ons.
Out
and function o, SFRstatus
their of Space.
bit the bits
functions DPTR Counter
3
Overflow of that m Ogram
intO The a ltStatus DATA
BUS|
8-BIT
carry.contains reflect
auxiliary bit
areiven 4. abit flag Word
F0 in the the P3.0-
P3.7 DRIVERPORT 3 LATCHPORT 3
arithmetic
is
carry (OV)
current
in a Carry (PSW)
neral-DurOSe Fig. BLOCK
TIMERAND
Table bit Parity a
operations
is (CY), stateThis 7.3 SERIAL
PORT ,
7.5. used
bit the of Block
The microcontroller. in (P), is
addition Auxiliary a
diagram
bits flag special-function
and
and
RS1 bit ittwo
available also
of Carry of
anduser-definable 8051
BCDserves
RS0 (AÇ), shows7.4
Figure P1.0-P1.7
microcontroller DRIVERPORT 1 LATCHPORT 1
f
numbers.
are or register.
as
used
user th e the 7.4 DATA
&-BUSBIT PSW

applictions. accumulator status twoshows This

to This
select register
bit flags. register thtehe
the is
set for The bank PSWPSW OsCILLATOR CONTROL
GISTER
TIMING&
UCTION
register The consists
if carry which
program carry number a a seect
bank bit of
resides
bits
1s c£n the
fromstatus
generated of ((RSl RST ALEPSEN
EA
BooleanServe atterent
in
four bits nt and the
 8051 Microcontroller Architecture 7.7

CY (AC FO RS1 R$O OV

PSW 7 PSW 0
PSW 6 PSW 1
PSW 5 PSW 2User-definable flag
PSW 4 PSW 3

Fig. 74 Program Status Word (Bit Addresable)

registerbanks. depicted in Table 7.6. The overflow flag is used forsigned arithmetic operation to determine,
whetherthere_ult is out of range after signed arithnmetic operatio. When the result is greater tha+127 or
esthat- 128, bVflag bit is set.
ny bit reflects the number of ls in the accumulator. When the accumulator contains an odd number
1.I the accumulator contains an even number of Is, P=0.
ofisP=
Table 725 Program status bits and their functions
Smbol Position Address Function
PSW.:7 D7H
Carry flag
PSW.6 D6H Auxiliary carry flag.
PSW.S DSH Flag 0. Available to the user for general purpose.
RSI PSW.4 D4H Register bank selector bit 1. Set by software to select the register bank
which willbe used.
RSO PSW.3 D3H Register bank selector bit 0. Set by software to select the register bank
which will be used.
OV PSW.2 D2H Overflow flag.
PSW.1 DIH Usable asageneral-purpose flag.
P PSW.O DOH Parity flag. Set/cleared by hardware each instruction cycle to indicate
an odd/even number of1' in the accumulator.

Table Z6 Register Bank Selections

RS1 RSO Register Bank Address Range
0 0 0 00H - 07H S
1 08H- QFH
1OH - 17H
1 1 3 18H - 1FH

Sack Pointer (SP) This is an 8-bit register. SP is incremented before the data is stored onto the stack
Using PUSH/CALL instructions execution. During PUSH operation, first increment SP and then copy the
va ln the POP operation, initiallycopy the data and then decrement SP. The 8-bit address of the stack top
Ored in this register. The stack can be located anywhere in the on-chip 128-byte RAM. Initially, the stack
POmier is initialised to 07H after reset operation. Hence the stack begins at locations 08H. The stack can be
relocated by setting SP tothe upper memory area in 30Hto 7FH.
Uata Pointer (DTPR)(DTPR is 16-bitregister. It consists of a higher byte (DPH) and a lowerbyt (DPL,)
T-DteXemal ata ESAV address. Ican be accessed as two 8-bit registers ora l6-bit regi_ter. DTPR has
been given two addresses in the special-function register bank. DPTR is very useful for string operations and
 look-up 7.8
asSuppose input memoryoutput can can byte input beThe is Port therememory as in 64
r.he Serial a DPTR Kof
nsmit The alsocommunicated allotted
be ofaddresses
buffers general-purpose 0, is
port. port line used th e Port location,no off-chiptable
Port the write be
Ports used external to such through
buffer registers (P3.1 as of the
al Data port of 1, operations.
strobeinputtoutput Port instruction
latches Port MOVX program
and
ta Buffer
address are external ), as corresponding with MØV
specify
also (P3.6)
I/O memory 0 register.
and 2,
eceive port. With
e ofused Port
other are Port
DPTR,#XXXX
port in R), memory
The Pl the Interrupt and The address stored
2, ICs 38051 @DPTR To 16-bit
buffer is as
value and on-chip
er serial 90H external pins are and Latches increment
bit in to can
addressable. lines of acts
itand used the decrement DPTR.
the DPTR,
Mlicrocontrollers
Microprocessorsand
is atport in to all and be
athe SFR, bedata Port input/output I/O instrucion.
output (P3.2, an
Port inspecial and
port. MOVX
the addressed.
in data
same important accesses a
The memory have
3rolein 2 maximum
outputs functionDrivers Al l contents
buffer "The on P3.3),
@DPTR,#XX
utation. address to ports ToFor
internally first
the readalternate
external externalsignals.
specific the register
ár e of read this, of
of bit strobe higher latch
Ech
and DPTR, 54
nsmitThe functions bidirectional data16-bit Kof
PI.0 of programming timer
The
r.consists output
port (P3.7).
memory. bank. are
is byte output INC memory from off-chip
9OH has input such used
The port of Using
In
DPTR memory
buffer of and the the corresponding
drivers respectively.
or lines as of thisinputoutput data
ial two Port same read serial external these location
internal instruction
ependent is (P3.4, case, location memory
address addresses, of
ata a addressvalue input
llel-in PortPorts
P3.5), memory memory This address
fer from
portsdriver and
of line 0 is and
outputs Oand executed. can
registers P1.7 asthe external ports of a
is the (P3.0), of
address. of also write maximum
wi l
ser 8
specified
is
register. 8051.
2, bitsports
97H. the and 0-3 bedata be
sucht data serial each. 03 But, used stored
P3 PIlow the can in of
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After
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otenrs,trol eProgrammable
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rithmetic Control
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Betic CPU
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and
depicted interrupt
orThe Fig. to0
specified drivers 33MHZ
tructions. 7.2
is Accumulator
ations, in
block
Schematic ALERST
ed ROM byte4k for Fig.
in PSENEA, Control Bus
g the the 7.3
Ports diagram
ccumulator block which
P0
B instruction
result register of
ply consists
P, 8051
is Address/bata
(ACC) diagram P,
stored is by Ports
Four/O RAM byte microcontroller.
and 128 and of
B also its acts of P, ALU,
P.
.ivide ACC. inbit SFR as 8051 P, The
control
an
Pa
addressable.addressmicrocontroller
ations operand operation
and The
ter detailed
timing
OEOH. TxD TimerTimer0 1
to ACC.2 register. PortSerial
A of
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architecture
n store ACCusedfor R*D
f The
operands
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RAM/EPROM/
commonly Counter
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the
accumulato; has of
and bit been 8051
2
sion, of
ACC may
in
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controller trollers.
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tionscontr such classified 4-bit procesSors
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Microprocessors AICROPROCESSOR 7.2
microprocessors
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microcomputer
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Microprocessors RAMmanipuBations,
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ng as to
microprocessors the
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into oktside
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such illustrated used an
control, 4-bit bytes. bus,
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ICs microcontrollers are areinstructions are are world. ALU is
as
microcontrollers for data RAM is a
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are
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microcontrollers,
with 16-bit,
position in personal incorporated bus and to between
Table most for as perform
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32-bit simple from perform a CONTROLBUS
commonly control ROM
as computers control DATABUS CPU.
features.
control, 7.2. are CPU arithmetic microprocessor
ystem,
well and
applications. 4-bit
are operations in within unit.
Generally, available 64-bit the bus The
as extensively8-bit to PORTS TIMERS MierocontroerM
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and 64-bit4-bit for block
ly and chip, and
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ed
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