32-Bit Micro Controller Based On ARM Cortex M0

Datasheet
MM32F003
32-bit Micro controller based on ARM Cortex M0
Ver: 1.11_q
Reserves the right to change the relevant information without notify.

Content
1 Introduction 1
1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Product Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2 Specification 3
2.1 Device contrast . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
® TM
2.2.1 ARM Cortex -M0 and SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.2 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2.3 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.4 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.5 Extended interrupt/event controller (EXTI) . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.6 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.7 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.2.8 Power supply supervisors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.9 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.10 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.11 Direct memory access controller (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.2.12 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2.2.13 Universal asynchronous receiver/transmitter (UART) . . . . . . . . . . . . . . . . . . . . . 9
2.2.14 I2C interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.15 Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.16 General-purpose inputs/outputs (GPIO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.17 Analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.18 Hardware Dvision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.2.19 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2.20 Serial single line SWD debug port (SW-DP) . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3 Pin definition 12
4 Memory mapping 17
5 Electrical characteristics 19
5.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
5.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
5.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.3.2 Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . 23
1
5.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . . . . . . . . . 23
5.3.4 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.3.5 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
5.3.6 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.3.7 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5.3.8 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5.3.9 Absolute Maximum (Electrical Sensitivity) . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
5.3.10 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
5.3.11 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
5.3.12 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5.3.13 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.3.14 12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
5.3.15 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
6 Package information 49
6.1 QFN20 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
6.2 TSSOP20 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
7 Revision history 53
2
List of Figures
1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 TSSOP20 packet pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4 QFN20 packet pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
7 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
8 Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9 Typical current consumption in standby mode vs. temperature at VDD = 3.3V . . . . . . . . . . . . 25
10 Typical current consumption in stop mode vs. temperature at VDD = 3.3V . . . . . . . . . . . . . . 26
11 High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 28
12 Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
13 I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
14 Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
15 I2C bus AC waveform and measurement circuit(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
16 SPI timing diagram-slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
17 SPI timing diagram-slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
18 SPI timing diagram-master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
19 Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
20 Power supply and reference power supply decoupling circuit . . . . . . . . . . . . . . . . . . . . . 47
21 QFN20 - 20-pin quad flat no-leads package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
22 TSSOP20 - 20-lead thin shrink small outline package outline . . . . . . . . . . . . . . . . . . . . . 51
3
List of Tables
1 MM32F003 device features and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2 Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3 Pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4 Alternate functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
5 Additional functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
6 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
7 Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
8 Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
9 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
10 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
11 Operating conditions at power-up/power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
12 Embedded reset and power control block characteristics . . . . . . . . . . . . . . . . . . . . . . . 23
13 Typical and maximum current consumption in stop and standby modes(2) . . . . . . . . . . . . . . 25
14 Typical current consumption in Run mode, code executing from Flash . . . . . . . . . . . . . . . . 26
15 Typical current consumption in sleep mode, code executing from Flash or RAM . . . . . . . . . . 27
16 On-chip peripheral current consumption(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
17 High-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
18 HSE oscillator characteristics(1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
19 HSI oscillator characteristics(1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
20 LSI oscillator characteristics(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
21 Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
22 Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
23 Flash memory endurance and data retention(1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
24 EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
25 ESD characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
26 I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
27 Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
28 I/O AC characteristics(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
29 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
30 TIMx(1) characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
31 I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
32 SPI characteristics(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
33 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
34 Maximum RAIN at fADC = 15MHz(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
35 ADC Accuracy - Limit Test Conditions(1)(2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
36 Temperature sensor characteristics(3)(4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
37 QFN20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
38 TSSOP20 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
39 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4
Introduction
DS_MM32F003_q_Ver1.11
1 Introduction
Introduction
1.1 Description
The microcontrollers incorporate the high-performance ARM® CortexTM -M0 32-bit core
operating at 48 MHz frequency, high-speed embedded memories, and an extensive range
of enhanced I/Os and peripherals connected to two APB buses. All devices offer 1 12-bit
ADC, 2 general purpose 16-bit timers, 3 Basic timers, 1 Advanced 16-bit timer, as well as
standard communication interfaces: 1 I2C , 1 SPI , , , and 1 UART.
The device operates from a 2.0V ∼ 5.5V power supply. They are available in both the
-40◦ C ∼ +85◦ C temperature range and the -40◦ C ∼ +105◦ C extended temperature range.
A comprehensive set of power-saving mode allows the design of low-power applications.
This product is available in 2 different package types: TSSOP20 and QFN20. Depending
on the device chosen, different sets of peripherals are included.
The description below gives an overview of the complete range of peripherals proposed
in this family.
These rich peripheral configurations make this product microcontroller suitable for a wide
range of applications:
• Motor drive and application control

• Healthcare and fitness equipment
• PC peripherals, gaming, GPS equipment
• Industrial Applications: Programmable Controllers (PLCs), Inverters, Printers and Scan-
ners
• Alarm system, wired and wireless sensors, video intercom
1.2 Product Features

• Core and system
– ARM® CortexTM -M0 CPU
– Maximum operating frequency is up to 48MHz
– Single cycle 32-bit hardware multiplier
– Hardware divider(32bit)
• Memories
– 16K Bytes of Flash memory
– 2K Bytes of SRAM
– Boot loader support Chip Flash and ISP (In-System Programming)
• Clock, reset and power management
www.mm32mcu.com 1/53
Introduction
– 2.0V ∼ 5.5V application supply

– Power-on/Power-down reset (POR/PDR), Programmable voltage detector (PVD)
– External 2 ∼ 24MHz high speed crystal oscillator
– Embedded factory-tuned 48MHz high speed oscillator
• Low-power
– Sleep, Stop and Standby modes
• 1 12-bit ADC, 1μS transform time (up to 8 channels)
– Conversion range: 0 ∼ VDDA
– Support sampling time and resolution configuration
– On-chip temperature sensor
– On-chip voltage sensor
• 5 DMA controller
– Supported peripherals: Timer、UART、I2C、SPI and ADC
• Up to 16 fast I/Os:
– All mappable on 16 external interrupt vectors
– Almost all can work on 5V
• Debug mode
– Serial wire debug (SWD)
• Up to 9 timers
– 1 16-bit 4-channel advanced-control timer for 4 channels PWM output, with
deadtime generation and emergency stop
– 2 16-bit timer, with up to 4 IC/OC, usable for IR control decoding
– 2 16-bit timer, with 1 IC/OC, 1 OCN, deadtime generation and emergency stop
and modulator gate for IR control
– 1 16-bit timer, with 1 IC/OC
– 2 watchdog timers (independent and window type)
– SysTick timer: 24-bit downcounter
• Up to 3 Communication interfaces
– 1 UART
– 1 I2C
– 1 SPI
• 96-bit unique ID (UID)
• Packages TSSOP20 and QFN20
In this paper, we give the order information and the mechanical properties of this de-
vice. For more information about the complete product, refer to Section 2.2 of the data
sheet.
The relevant information about the CortexTM -M0, please refer to <CortexTM -M0 techni-
cal reference manual>.
Specification
2 Specification
Specification
2.1 Device contrast

Table 1. MM32F003 device features and peripheral counts
Peripheral MM32F003TW MM32F003NW
Flash memory -K Bytes 16
SRAM -K Bytes 2
General purpose
2
Timers (16 bit)
basic 3
Advanced control 1
UART 1
Common interfaces I2C 1
SPI 1
GPIOs 16
12-bit ADC 1
(number of channels) 8 channels
Max CPU frequency 48 MHz
Operating voltage 2.0V ∼ 5.5V
Packages TSSOP20 QFN20
2.2 Summary
2.2.1 ARM® CortexTM -M0 and SRAM

The ARM® CortexTM -M0is a generation of ARM processors for embedded systems. It has
been developed to provide a low-cost platform that meets the needs of MCU implementa-
tion, with a reduced pin count and low-power consumption, while delivering outstanding
computational performance and an advanced system response to interrupts.
The ARM® CortexTM -M0 processors feature exceptional code-efficiency, delivering the
high performance expected from an ARM core, with memory sizes usually associated
with 8- and 16-bit devices.
The devices embed ARM core and are compatible with all ARM tools and software.
2.2.2 Memory
16K Bytes of embedded Flash memory.
Specification
2.2.3 SRAM
2K Bytes of embedded SRAM.
2.2.4 Nested vectored interrupt controller (NVIC)

The device embeds a nested vectored interrupt controller able to handle up to 68 maskable
interrupt channels (not including the 16 interrupt lines of
Cortex™-M0) and 16 priority levels.
• Closely coupled NVIC gives low latency interrupt processing

• Interrupt entry vector table address passed directly to the core
• Closely coupled NVIC core interface
• Allows early processing of interrupts
• Processing of late arriving higher priority interrupts
• Support for tail-chaining
• Processor state automatically saved
• Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal inter-
rupt latency.
2.2.5 Extended interrupt/event controller (EXTI)

The extended interrupt/event controller consists of many edge detector lines used to gen-
erate interrupt/event requests and wake-up the system. Each line can be independently
configured to select the trigger event (rising edge, falling edge, both) and can be masked
independently. A pending register maintains the status of the interrupt requests. The
EXTI can detect an external line with a pulse width shorter than the internal APB2 clock
period. All GPIOs can be connected to the 16 external interrupt lines.
2.2.6 Clocks and startup

System clock selection is performed on startup, however the internal 48 MHz oscillator is
selected as default CPU clock on reset,After reset, the default is 6 division. However, when
selecting HSI in the description of the division register, the minimum must be divided by
2. An external 2 ∼ 24 MHz clock can be selected, in which case it is monitored for failure；
If failure is detected, the system automatically switches back to the internal oscillator. A
software interrupt is generated if enabled.
Several prescalers allow the application to configure the frequency of the AHB and the
APB domains. The maximum frequency of the AHB and the APB domains is 48 MHz.Refer
to figure 2 for the clock drive block diagram.
2.2.7 Power supply schemes

• VDD = 2.0V ∼ 5.5V: external power supply for I/Os and the internal regulator. Provided
externally through VDD pins.
• VSSA , VDDA = 2.0V ∼ 5.5V：external analog power supply for reset blocks and oscillators.
VDDA and VSSA must be connected to VDD and VSS .
Specification
2.2.8 Power supply supervisors

The device has integrated power-on reset (POR) and power-down reset (PDR) circuits.
They are always active, and ensure proper operation above a threshold of 1.8V. The
device remains in reset mode when the monitored supply voltage is below a specified
threshold VPOR/PDR , without the need for an external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors
the VDD /VDDA power supply and compares it to the VPVD threshold. An interrupt can be
generated when VDD drops below the VPVD threshold and/or when VDD is higher than
the VPVD threshold.The interrupt service routine can then generate a warning message
and/or put the MCU into a safe state. The PVD is enabled by software.
2.2.9 Voltage regulator

The voltage regulator converts the external voltage to the internal digital logic and it is
always enabled after reset.
2.2.10 Low-power modes

The device support three low-power modes to achieve the best compromise between low
power consumption, short startup time and available wakeup sources.
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake
up the CPU when an interrupt/event occurs.
Stop mode
Stop mode achieves very low power consumption while retaining the content of SRAM
and registers. the HSI and the HSE crystal oscillators are disabled. The voltage regulator
can also be put either in normal or in low power mode.
Standby mode
Standby mode achieves the lowest power consumption of the system. This mode turns
off the voltage regulator in CPU deep sleep mode. The entire 1.5V power supply area
is powered down. HSI and HSE oscillators are also powered down. SRAM and register
contents are missing.
2.2.11 Direct memory access controller (DMA)

The 5-channel general-purpose DMAs manage memory-to-memory, peripheral-to-memory
and memory-to-peripheral transfers. The DMA supports circular buffer management, re-
moving the need for user code intervention when the controller reaches the end of the
buffer.
Each channel is connected to dedicated hardware DMA requests, with support for soft-
ware trigger on each channel. Configuration is made by software and transfer sizes be-
tween source and destination are independent.
DMA can be used with the main peripherals: UART、I2C、SPI、ADC general-purpose
Specification
and advanced-control timers TIMx.
2.2.12 Timers and watchdogs

Medium capacity device include 1 advanced control、2 general-purpose timers 、3 base-
timer. 、2 watchdog timers and 1 SysTick timer.
The following table compares the features of the different timers:
Specification
Table 2. Timer feature comparison

Capture/- Complem
Counter Counter Prescaler DMA request
Timer type Timer compare -entary
resolution type factor generation
channels outputs
integer
Advanced Up, down,
TIM1 16-bit from 1 to Yes 4 Yes
control up/down
65536
integer
Up, down,
TIM2 16-bit from 1 to Yes 4 No
up/down
General 65536
purpose integer
Up, down,
TIM3 16-bit from 1 to Yes 4 No
up/down
65536
integer
TIM14 16-bit Up from 1 to Yes 1 No
65536
basic
integer
TIM16 /
16-bit Up from 1 to Yes 1 Yes
TIM17
65536
Advanced-control timer ( TIM1 )

The advanced-control timer can be seen as a three-phase PWM multiplexed on six chan-
nels. It has complementary PWM outputs with programmable inserted dead times. It can
also be seen as a complete general-purpose timer. The four independent channels can
be used for：
• Input capture
• Output compare
• PWM generation (edge or center-aligned modes)
• One-pulse mode output
If configured as a standard 16-bit timer, it has the same features as the TIMx timer. If
configured as the 16-bit PWM generator, it has full modulation capability (0 ∼ 100%).
In debug mode, the counter can be frozen and the PWM output is disabled to cut off the
switches controlled by these outputs.
Many features are shared with those of the standard timers which have the same archi-
tecture. The advanced control timer can therefore work together with the other timers via
the Timer Link feature for synchronization or event chaining.
General-purpose timers (TIMx)

There are 2 synchronizable general-purpose timers ( TIM2、TIM3 ).
Specification
General-purpose timers 16-bit

The timer is based on a 16-bit auto-reload up/downcounter and a 16-bit prescaler. The
feature is 4 independent channels each for input capture/output compare, PWM or one-
pulse mode output.
The timer can work together or with the TIM1 advanced-control timer via the Timer Link
feature for synchronization or event chaining. Their counter can be frozen in debug mode.
Any of the general-purpose timers can be used to generate PWM outputs. They all have
independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
Basic timer
TIM14
This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. TIM14 fea-
tures one single channel for input capture/output compare, PWM or one-pulse mode out-
put. Their counter can be frozen in debug mode.
TIM16/TIM17
Every timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler. They each
have a single channel for input capture/output compare, PWM or one-pulse mode output.
TIM16 and TIM17 have a complementary output with dead-time generation and indepen-
dent DMA request generation. Their counters can be frozen in debug mode.
Independent watchdog (IWDG)

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with
user-defined refresh window. It is clocked from an independent 40 KHz internal oscillator
and as it operates independently from the main clock, it can operate in Stop and Standby
modes. It can be used either as a watchdog to reset the device when a problem occurs,
or as a free running timer for application timeout management. It is hardware or software
configurable through the option bytes. The counter can be frozen in debug mode.
System window watchdog (WWDG)

The system window watchdog is based on a 7-bit downcounter that can be set as free
running. It can be used as a watchdog to reset the device when a problem occurs. It is
clocked from the APB clock (PCLK). It has an early warning interrupt capability and the
counter can be frozen in debug mode.
SysTick timer
This timer is dedicated to real-time operating systems, but could also be used as a stan-
dard down counter. It features:
• A 24-bit down counter

• Autoreload capability
• Maskable system interrupt generation when the counter reaches 0
• Programmable clock source
Specification
2.2.13 Universal asynchronous receiver/transmitter (UART)

UART provides hardware management of the CTS, RTS.
Compatible with ISO7816 smart card mode. The UART interface supports output data
lengths of 5 bits, 6 bits, 7 bits, 8 bits, and 9 bits.
All UART interface can be served by the DMA controller.
2.2.14 I2C interface

The I2C interface can operate in multimaster or slave modes. It can support Standard
mode,and Fast Mode.
It supports 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (two ad-
dresses, one with configurable mask).
2.2.15 Serial peripheral interface (SPI)

The SPI interface, in slave or master mode, can be configured to 1 ∼ 32 bits per frame.
All SPI interface can be served by the DMA controller.
2.2.16 General-purpose inputs/outputs (GPIO)

Each of the GPIO pins can be configured by software as output (push-pull or open-drain),
as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of
the GPIO pins are shared with digital or analog alternate functions. The I/O configuration
can be locked if needed following a specific sequence in order to avoid spurious writing
to the I/Os registers.
2.2.17 Analog-to-digital converter (ADC)

The one 12-bit analog-to-digital converters is embedded into microcontrollers and the ADC
shares up to 10 external channels, performing conversions in single-shot or scan modes.
In scan mode, automatic conversion is performed on a selected group of analog inputs.
The ADC can be served by the DMA controller.
The analog watchdog function allows very precise monitoring of all the way, multiple or
all selected channels, and an interruption occurs when the monitored signal exceeds the
preset threshold. The events generated by the general-purpose timers (TIMx) and the
advanced-control timer (TIM1) can be internally connected to the ADC start trigger to
allow the application to synchronize A/D conversion and timers.
2.2.18 Hardware Dvision

The hardware division unit consists of four 32-bit data registers, which are dividend, divi-
sor, quotient and remainder, and can be done with signed or unsigned 32-bit division. The
hardware division control register USIGN can choose whether to have signed division or
unsigned division.
Each time the divisor register is written, the division operation is automatically triggered.
After the operation is completed, the result is written to the quotient and remainder regis-
Specification
ters. If the reader register, remainder register, or status register is read before the end,
the read operation is suspended until the end of the operation.
If the divisor is zero, an overflow interrupt flag will be generated.
2.2.19 Temperature sensor

The temperature sensor has to generate a voltage that varies linearly with temperature.
The temperature sensor is internally connected to the input channel which is used to con-
vert the sensor output voltage into a digital value.
2.2.20 Serial single line SWD debug port (SW-DP)

Built-in ARM two-wire serial debug port (SW-DP) .
An ARM SW-DP interface is provided to allow a serial wire debugging tool to be connected
to the MCU.
AHB Flash Flash

interface
System
CPU
AHB SRAM
Bus Matrix
AHB CRC
DMA
DMA
AHB APB1 APB1
AHB APB2 APB2

AHB
ADC1 PWR TIM3

RCC TIM1 I2C1 TIM2
TIM14 UART2
TIM16 SPI2
TIM17 WWDG
GPIOA/B/C/D SYSCFG
DMA request
709574
Figure 1. Block diagram
Specification
HSI / 6 HCLK
HSI to AHB bus, core
48 MHz
Clock memory and DMA
Enable (3 bits)
SW /8 to Cortex System !mer
HSI / 6 FCLK Cortex
Free running clock
HSI AHB APB1
SYSCLK
Prescaler Prescaler PCLK1
to APB1
OSC_OUT HSE OSC HSE /1,2..512 /1,2,4,8,16 peripherals
Peripheral Clock
OSC_IN 2 - 24 MHz LSI Enable (10 bits)
If (APB1 Prescaler=1) x 1 TIMXCLK

CSS
else x2 to TIM2,3
Peripheral Clock
Enable (2 bits)
APB2
PCLK2
Prescaler to APB2
/1,2,4,8,16
Peripheral Clock peripherals
Enable (5bits)
If (APB2 Prescaler=1) x 1 TIMXCLK

else x2 to TIM1,14,16,17
Peripheral Clock
Enable (4 bit)
LSI LSI IWDGCLK ADC
ADCCLK
40kHz to Independent Prescaler to ADC
Watchdog (IWDG) /2,4,6,8
If (APB2 Prescaler!=1) TIM.ADV

APB x 2 to TIM1
Main else if (AHB Prescale!=1) Peripheral Clock
HSI/6 Enable
Clock Output AHB x 2
MCO HSE
else
SYSCLK
AHB CLK
LSICLK
Legend:
MCO HSE = high-speed external clock signal
HSI = high-speed internal clock signal
LSI = low-speed internal clock signal
280409
Figure 2. Clock tree
Pin definition
3 Pin definition
Pin definition
PB6 PB4
PB7 PB3
PA6 PA14
nNRST PA13
PD0-OSC_IN PB14
TSSOP20
PD1-OSC_OUT PB13
VSSA-VSS PB1
VCap PB0
VDD-VDDA PA5
PA0 PA4
415138
Figure 3. TSSOP20 packet pinout

PB7
PB6
PB4
PB3
PA6
20
19
18
17
16
nNRST 1 15 PA14
PD0-OSC_IN 2 14 PA13
QFN20 13
PD1-OSC_OUT 3 PB14
VSSA-VSS
- 4 12 PB13
VCap 5 11 PB1
10
6
9
PA0
PA5
VDD-VDDA
PA4
PB0
451975
Figure 4. QFN20 packet pinout
annotate: VCap should be setted to float or connect to ground with 0.1uF-0.01uF capacitor.
Pin definition
Table 3. Pin definitions

Pin number I/O Main Alternate Additional
Pin name Type(1)
QFN20 TSSOP20 structure (2)
function functions functions
1 4 nNRST I/O FT Reset - -
2 5 PD0/OSC_IN I/O FT PD0 I2C1_SDA -
3 6 PD1/OSC_OUT I/O FT PD1 I2C1_SCL -
4 7 VSSA/VSS S - ground - -
1.5V
5 8 VCap S - regulator - -
capacitor
power
6 9 VDD/VDDA S - - -
supply
UART2_CTS/
PA0- TIM2_CH1_ETR/
7 10 I/O TC PA0 ADC1_VIN[0]
WAKEUP SPI2_NSS/
TIM2_CH3
TIM1_BKIN /
8 11 PA4 I/O TC PA4 TIM14_CH1 / ADC1_VIN[4]
I2C1_SDA
TIM2_CH1_ETR /
TIM1_ETR /
9 12 PA5 I/O TC PA5 ADC1_VIN[5]
I2C1_SCL /
TIM1_CH3N
TIM3_CH3 /
TIM1_CH2N /
10 13 PB0 I/O TC PB0 -
TIM1_CH1N /
TIM1_CH3
TIM14_CH1 /
TIM3_CH4 /
TIM1_CH3N /
TIM1_CH4 /
11 14 PB1 I/O TC PB1 ADC1_VIN[9]
TIM1_CH2N /
MCO/
TIM1_CH2 /
TIM1_CH1N
Pin definition

Pin name Type(1)
SPI2_SCK /
SPI2_MISO /
TIM1_CH1N /
SPI2_NSS /
12 15 PB13 I/O FT PB13 -
SPI2_MOSI /
I2C1_SCL /
TIM1_CH3N /
TIM2_CH1
SPI2_MISO /
SPI2_MOSI /
TIM1_CH2N /
SPI2_SCK /
13 16 PB14 I/O FT PB14 -
SPI2_NSS /
I2C1_SDA /
TIM1_CH3 /
TIM1_CH1
SWDIO /
SPI2_MISO /
14 17 PA13 I/O FT PA13 MCO / -
TIM1_CH2 /
TIM1_BKIN
SWDCLK /
15 18 PA14 I/O FT PA14 -
UART2_TX
TIM2_CH2 /
TIM2_CH3 /
TIM1_CH1 /
TIM2_CH1
TIM3_CH1 /
TIM17_BKIN /
TIM1_CH2 /
TIM2_CH2
I2C1_SCL /
18 1 PB6 I/O FT PB6 TIM16_CH1N / -
TIM2_CH1
I2C1_SDA /
19 2 PB7 I/O TC PB7 TIM17_CH1N / ADC1_VIN[12]
UART2_TX
Pin definition

Pin name Type(1)
TIM3_CH1 /
TIM1_BKIN /
UART2_RX /
20 3 PA6 I/O TC PA6 ADC1_VIN[6]
TIM1_ETR /
TIM16_CH1 /
TIM1_CH3
1. I = input, O = output, S = power supply, HiZ = high resistance.

2. FT: 5V tolerant, Input signal should be between VDD and 5V.
TC: Standard I/O, Input signal does not exceed VDD.
Table 4. Alternate functions

Pin
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
Name
TIM2_CH1
PA0 - - SPI2_NSS TIM2_CH3 - - -
_ETR
TIM14_
PA4 - - - TIM1_BKIN I2C1_SDA - -
CH1
TIM2_CH1_ TIM1_
PA5 - - TIM1_ETR - I2C1_SCL -
ETR CH3N
TIM1_ TIM1_
PA6 - TIM3_CH1 TIM1_BKIN UART2_RX TIM16_CH1 -
ETR CH3
SPI2_ TIM1_ TIM1_
PA13 SWDIO - - - MCO
MISO CH2 BKIN
PA14 SWDCLK UART2_TX - - - - - -
TIM1_ TIM1_
PB0 - TIM3_CH3 TIM1_CH3 - - -
CH2N CH1N
TIM14_ TIM1_ TIM1_ TIM1_
PB1 TIM3_CH4 TIM1_CH4 MCO TIM1_CH2
CH1 CH3N CH2N CH1N
TIM2_
PB3 - - - TIM2_CH3 - TIM1_CH1 TIM2_CH1
CH2
TIM17_
PB4 - TIM3_CH1 - - - TIM1_CH2 TIM2_CH2
BKIN
TIM16_
PB6 - I2C1_SCL - TIM2_CH1 - - -
CH1N
TIM17_
PB7 - I2C1_SDA - UART2_TX - - -
CH1N
TIM1_ TIM1_
PB13 - SPI2_MISO SPI2_NSS SPI2_MOSI I2C1_SCL TIM2_CH1
CH1N CH3N
Pin definition
Pin
AF0 AF1 AF2 AF3 AF4 AF5 AF6 AF7
Name
TIM1_
PB14 - SPI2_MOSI SPI2_SCK SPI2_NSS I2C1_SDA TIM1_CH3 TIM1_CH1
CH2N
PD0 - I2C1_SDA - - - - - -
PD1 - I2C1_SCL - - - - - -
Table 5. Additional functions

Pin Name Additional Functions
PA0 ADC1_VIN[0]
PA4 ADC1_VIN[4]
PA5 ADC1_VIN[5]
PA6 ADC1_VIN[6]
PB1 ADC1_VIN[9]
PB3 ADC1_VIN[10]
PB4 ADC1_VIN[11]
PB7 ADC1_VIN[12]
Memory mapping
4 Memory mapping
Memory mapping
Table 6. Memory mapping

Bus Boundaryaddress Size Peripheral Notes
Main flash memory, system
0x0000 0000 - 0x0000 3FFF 16 KB memory, or SRAM, depends on
the configuration of BOOT
0x0000 4000 - 0x07FF FFFF ∼ 128 MB Reserved
0x0800 0000 - 0x0800 3FFF 16 KB Main Flash memory
0x0802 0000 - 0x1FFD FFFF ∼ 256 MB Reserved
Flash
0x1FFE 0000 - 0x1FFE 01FF 0.5 KB Reserved
0x1FFE 0200 - 0x1FFE 0FFF 3 KB Reserved
0x1FFE 1000 - 0x1FFE 1BFF 3 KB Reserved
0x1FFE 1C00 - 0x1FFF F3FF ∼ 256 MB Reserved
0x1FFF F400 - 0x1FFF F7FF 1 KB Sysem memory
0x1FFF F800 - 0x1FFF F80F 16 B Option bytes
0x1FFF F810 - 0x1FFF FFFF ∼ 2 KB Reserved
0x2000 0000 - 0x2000 07FF 2 KB SRAM
SRAM
0x2000 0800 - 0x2FFF FFFF ∼ 512 MB Reserved
0x4000 0000 - 0x4000 03FF 1 KB TIM2
0x4000 0400 - 0x4000 07FF 1 KB TIM3
0x4000 0800 - 0x4000 0BFF 8 KB Reserved
0x4000 2C00 - 0x4000 2FFF 1 KB WWDG
0x4000 3000 - 0x4000 33FF 1 KB IWDG
0x4000 3400 - 0x4000 37FF 1 KB Reserved
0x4000 3800 - 0x4000 3BFF 1 KB SPI2
APB1
0x4000 4000 - 0x4000 43FF 1 KB Reserved
0x4000 4400 - 0x4000 47FF 1 KB UART2
0x4000 5400 - 0x4000 57FF 1 KB I2C1
0x4000 5C00 - 0x4000 5FFF 1 KB Reserved
0x4000 6000 - 0x4000 63FF 1 KB Reserved
0x4000 6400 - 0x4000 67FF 1 KB Reserved
Memory mapping
Bus Boundaryaddress Size Peripheral Notes

APB1 0x4000 7000 - 0x4000 73FF 1 KB PWR
0x4000 7400 - 0x4000 FFFF 35 KB Reserved
0x4001 0000 - 0x4001 03FF 1 KB SYSCFG
0x4001 0400 - 0x4001 07FF 1 KB EXTI
0x4001 0800 - 0x4001 23FF 7 KB Reserved
0x4001 2400 - 0x4001 27FF 1 KB ADC1
0x4001 2C00 - 0x4001 2FFF 1 KB TIM1
APB2 0x4001 3800 - 0x4001 3BFF 1 KB Reserved
0x4001 3000 - 0x4001 33FF 1 KB Reserved
0x4001 3400 - 0x4001 37FF 1 KB DBGMCU
0x4001 4000 - 0x4001 43FF 1 KB TIM14
0x4001 4400 - 0x4001 47FF 1 KB TIM16
0x4001 4800 - 0x4001 4BFF 1 KB TIM17
0x4001 4C00 - 0x4001 63FF 7 KB Reserved
0x4001 6400 - 0x4001 67FF 1 KB Pwm Ctrl
0x4001 6800 - 0x4001 7FFF 6 KB Reserved
0x4002 0000 - 0x4002 03FF 1 KB DMA
0x4002 1000 - 0x4002 13FF 1 KB RCC
0x4002 2000 - 0x4002 23FF 1 KB Flash interface
AHB 0x4002 6000 - 0x4002 63FF 1 KB Reserved
0x4002 6400 - 0x47FF FFFF ∼ 128 MB Reserved
0x4800 0000 - 0x4800 03FF 1 KB GPIOA
0x4800 0400 - 0x4800 07FF 1 KB GPIOB
0x4800 0800 - 0x4800 0BFF 1 KB GPIOC
0x4800 0C00 - 0x4800 0FFF 1 KB GPIOD
0x4800 1000 - 0x5FFF FFFF ∼ 384 MB Reserved
Electrical characteristics
5 Electrical characteristics
5.1 Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS .
5.1.1 Minimum and maximum values

Unless otherwise specified, the minimum and maximum values are guaranteed with an
ambient temperature at TA = 25◦ C, VDD = 3.3V.
5.1.2 Typical values

Unless otherwise specified, typical data are based on TA = 25◦ C and VDD = 3.3V. They
are given only as design guidelines and are not tested.
5.1.3 Typical curves

Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
5.1.4 Loading capacitor

The load conditions used for pin parameter measurement are shown in the figure below.
C = 50 pF
230907
Figure 5. Pin loading conditions
5.1.5 Pin input voltage

The input voltage measurement on a pin of the device is shown in the figure below.
VIN
984785
Figure 6. Pin input voltage
5.1.6 Power supply scheme
VCAP
VDD
VDD
1/2/3
Regulator
OUT Kernel logic

Level shifter
IO (CPU, Digital
GP I/Os & Memories)
IN Logic
5x100nF VSS
+1x4.7µF 1/2/3
VDD
VDDA
10nF Analog:
+1µF $'& RC, PLL, COMP ...
VSSA
782609
Figure 7. Power supply scheme
5.1.7 Current consumption measurement
I DD_VBAT
VBAT
I DD
VDD
VDDA
738329
Figure 8. Current consumption measurement scheme
5.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Tables(Table 7、Table 8、Table 9)
may cause permanent damage to the device. These are stress ratings only and functional
operation of the device at these conditions is not implied. Exposure to maximum rating
conditions for extended periods may affect device reliability.
Table 7. Voltage characteristics
Symbol Definition Min Max Unit
External main supply

VDD - VSS - 0.3 5.5
voltage(including VDDA and VSSA )(1)
V
Input voltage on FT and FTf pins(2) VSS - 0.3 5.5
VIN
Input voltage on TTa pins(2) VSS - 0.3 5.5
Variations between different VDD
| △ VDDx | 50
power pins
mV
Variations between all the different
|VSSx − VSS | 50
ground pins
1. All main power (VDD , VDDA ) and ground (VSS , VSSA ) pins must always be connected to
the external power supply, in the permitted range.
2. VIN maximum must always be respected. Refer to Table below for maximum allowed
injected current values.
Table 8. Current characteristics
Symbol Definition Max Unit
Total current into sum of all VDD /VDDA power

IVDD 120
lines(source)(1)
IVSS Total current out of sum of all VSS ground lines(sink)(1) 120 mA
Output current sunk by any I/O and control pin 20

IIO
Output current source by any I/O and control pin -18
(2)(3)
IINJ(PIN) Injected current on NRST pins ±5 mA
Injected current on OSC_IN pin of HSE and OSC_IN pin
IINJ(PIN) (2)(3) ±5 mA
of LSE
IINJ(PIN) (2)(3) Injected current on other pins(4) ±5 mA
(2) (5)
Σ IINJ(PIN) Total injected current(sum of all I/O and control pins) ±25 mA
1. All main power(VDD , VDDA ) and ground(VSS , VSSA ) pins must always be connected to
the external power supply, in the permitted range.
2. This current consumption must be properly distributed to all I/O and control pins. The
total output current must not be poured/pulled between the two consecutive power
supply pins of the reference high pin count LQFP package.
3. Negative injection disturbs the analog performance of the device.
4. When VIN > VDD , there is a forward injection current; when VIN < VSS , there is a reverse
injection current.Do not exceed IINJ(PIN) .
5. When several inputs are submitted to a current injection, the maximum IINJ(PIN) is the
absolute sum of the positive and negative injected currents (instantaneous values).
Table 9. Thermal characteristics
◦
TSTG Storage temperature range - 45 ∼ + 150 C
Maximum junction
◦
TJ 125 C
temperature
5.3 Operating conditions
5.3.1 General operating conditions

Table 10. General operating conditions
Symbol Parameter Conditions Min Max Unit
Internal AHB clock

fHCLK 0 48
frequency
MHz
Internal APB1 clock
fPCLK1 0 fHCLK
frequency
Internal APB2 clock
fPCLK2 0 fHCLK
frequency
Standard operating
VDD 2.0 5.5 V
voltage
Analog operating voltage

2.0 5.5
VDDA (1) (ADC not used) Must be the same voltage as VDD V
Analog operating voltage

2.5 5.5
(ADC used)
Maximum power dissipation -25 85

TA Ambient temperature：TA =85◦ C(2) ◦
C
Low power dissipation(3) -25 105
1. It is recommended to use the same power supply for VDD and VDDA , the maximum
permissible difference between VDD and VDDA is 300mVduring power up and normal
operation.
2. If TA is low, higher PD values are allowed as long as TJ does not exceed TJmax (See
subsec 5.1).
3. In low power dissipation state, TA can be extended to this range as long as TJ does
not exceed TJmax (See subsec 5.1).
5.3.2 Operating conditions at power-up/power-down

The parameters given in the table below are based on tests under normal operating con-
ditions.
Table 11. Operating conditions at power-up/power-down
VVDD rise time rate 300 ∞

tVDD TA = 27◦ C µS/V
VVDD fall time rate 300 ∞
5.3.3 Embedded reset and power control block characteristics

The parameters given in the table below are based on the ambient temperature and the
VDD supply voltage listed in Table 10.
Table 12. Embedded reset and power control block characteristics
Symbol Parameter Conditions Min Typ Max Unit
PLS[3：0]=0000 (Rising edge) 1.82 V

PLS[3：0]=0000 (Falling edge) 1.71 V
VPVD Level selection of programmable voltage detectors

(2)
VPVDhyst PVD hysteresis 110 mV
Power on/down Falling edge 1.63(1) 1.66 1.68 V
VPOR/PDR
reset threshold Rising edge 1.75 V
VPDRhys (2) PDR hysteresis 90.9 mV
(2)
TRSTTEMPO Reset duration 0.61 ms
1. The product behavior is guaranteed by design down to the minimum value VPOR/PDR .
2. Guaranteed by design, not tested in production.
Note: The reset duration is measured from power-on (POR reset) to the time when the user appli-
cation code reads the first instruction.
5.3.4 Supply current characteristics

The current consumption is a function of several parameters and factors such as the op-
erating voltage, temperature, I/O pin loading, device software configuration, operating fre-
quencies, I/O pin switching rate, program location in memory and executed binary code.
All Run-mode current consumption measurements given in this section are performed with
a reduced code.
Maximum current consumption

The MCU is placed under the following conditions:
• All I/O pins are in analog input mode, and are connected to a static level —- VDD or VSS
(no load)
• All peripherals are disabled except when explicitly mentioned
• The Flash memory access time is adjusted to the fHCLK (0 ∼ 24 MHz is 0 waiting period
, 24 ∼ 48 MHz is 1 waiting period ).
• The instruction prefetching function is on. When the peripherals are enabled：fPCLK1 =
fHCLK .
Note：The instruction prefetching function must be set before setting the clock and bus divider.
Table 13. Typical and maximum current consumption in stop and standby modes(2)
Max(1)
Symbol Parameter Conditions Unit
TA =25◦ C
Supply current in Stop mode Enter the stop mode after reset 6
IDD Supply current in Standby µA
Enter the standby mode after reset 0.4
mode
1. Maximum values are tested at TA = 25◦ C.

2. Data based on characterization results, not tested in production.The IO state is an
analog input.
90
80
70
60
50
40
30
20
10
0
TA = - 40°C TA = 25°C TA = 70°C TA = 105°C
6XSSO\FXUUHQWLQVWDQGE\PRGH X$
148491
Figure 9. Typical current consumption in standby mode vs. temperature at VDD = 3.3V
90
80
70
60
50
40
30
20
10
0
TA = - 40°C TA = 25°C TA = 70°C TA = 105°C
6XSSO\FXUUHQWLQVWRSPRGH X$
577187
Figure 10. Typical current consumption in stop mode vs. temperature at VDD = 3.3V
Typical current consumption

The MCU is placed under the following conditions:
• All I/O pins are in analog input configuration, and are connected to a static level —- VDD
or VSS (no load).
• All the peripherals are closed, unless otherwise specified.
• The Flash memory access time is adjusted to the fHCLK (0 ∼ 24 MHz is 0 waiting period
, 24 ∼ 48 MHz is 1 waiting period ).
• The ambient temperature and VDD supply voltage conditions are summarized in Ta-
ble 10.
• The instruction prefetching function is on (Note：this parameter must be set before
setting the clock and bus divider). When the peripherals are enabled：fPCLK1 = fHCLK .
Table 14. Typical current consumption in Run mode, code executing from Flash
Typ(1)
Symbol Parameter Conditions fHCLK All peripherals All peripherals Unit
enabled disabled
48MHz 14.71 9.13

36MHz 11.76 7.58
IDD Supply current in operating
Internal
mode
clock mA
24MHz 6.158 1.544
8MHz 2.176 0.962
1. The typical value is tested at TA = 25◦ Cand VDD = 3.3V.
Table 15. Typical current consumption in sleep mode, code executing from Flash or RAM
Typ(1)
Symbol Parameter Conditions fHCLK (2) All peripherals All peripherals Unit
enabled disabled
48MHz 9.84 6.12

IDD Supply current in sleep
Internal
mode clock mA
8MHz 2.17 1.55
1. The typical value is tested at TA = 25◦ Cand VDD = 3.3V.

2. External clock is 8MHz, when fHCLK > 8MHz choose HSI48.
On-chip peripheral current consumption

The current consumption of the on-chip peripherals is given in Table 16. The MCU is
placed under the following conditions:
• all I/O pins are in analog input mode, and are connected to a static level —- VDD or VSS
(no load)
• all peripherals are disabled except when explicitly mentioned
• the given value is calculated by measuring the current consumption
– with all peripherals clocked OFF
– with only one peripheral clocked on
• ambient operating temperature and supply voltage conditions VDD summarized in Ta-
ble 10
Table 16. On-chip peripheral current consumption(1)
Peripheral 25 ◦ C
Unit
Typical consumption at Peripheral 25 ◦ C
Unit
Typical consumption at
HIVEN 2.17 SPI 7.92

GPIOD 0.75 TIM1 17.04
GPIOC 0.58 APB2 ADC 1.54
AHB GPIOB 0.71 SYSCFG 0.37
GPIOA 0.71 uA/MHz UART 5.38 uA/MHz
CRC 1.00 PWR 0.79

DMA 4.38 I2C 9.58
APB1
PWM 1.75 WWDG 5.96
APB2
TIM17 3.29 TIM3 8.83
TIM16 3.17 TIM2 0.50
APB2 TIM14 3.17 uA/MHz APB1 uA/MHz
CPT 0.58
1. fHCLK = 48MHz, fAPB1 = fHCLK /2, fAPB2 = fHCLK , the prescale coefficient for each device
is the default value.
5.3.5 External clock source characteristics

High-speed external user clock generated from an external source
The characteristic parameters given in the following table are measured using a high-
speed external clock source, ambient temperature and power supply voltage meet the
conditions of General operating conditions.
Table 17. High-speed external user clock characteristics
User external clock source

fHSE_ext 2 8 24 MHz
frequency(1)
OSC_IN input pin high level
VHSEH 0.7VDD VDD
voltage
V
OSC_IN input pin low level
VHSEL VSS 0.3VDD
voltage
tw(HSE) OSC_IN high or low time(1) 16
tr(HSE) nS
OSC_IN rise or fall time(1) 20
tf(HSE)
Cin(HSE) OSC_IN input capacitance(1) 5 pF
DuCy(HSE) Duty cycle 45 55 %
IL OSC_IN input leakage current VSS ≤ VIN ≤ VDD ±1 uA
VHSEH
90%
10%
VHSEL
tr(HSE) tf(HSE) tw(HSE) tw(HSE) t
THSE
External Clock IL
Source fHSE_ext OSC_IN
474122
Figure 11. High-speed external clock source AC timing diagram
High-speed external clock generated from a crystal/ceramic

resonator
The high-speed external (HSE) clock can be supplied with an 2 to 24 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on design simu-
lation results obtained with typical external components specified in the table below. In the
application, the resonator and the load capacitors have to be placed as close as possible
to the oscillator pins in order to minimize output distortion and startup stabilization time.
Refer to the crystal resonator manufacturer for more details on the resonator characteris-
tics (frequency, package, accuracy...).
Table 18. HSE oscillator characteristics(1)(2)
fOSC_IN Oscillator frequency 2 8 24 MHz

RF Feedback resistor RS = 30Ω 1000 kΩ
The proposed load
VDD = 3.3V
CL1 capacitance corresponds to
VIN = VSS 30 pF
CL2 (3) the crystal serial impedance
30pF load
(RS ) (4)
I2 HSE current consumption Startup 4.5 mA
gm Oscillator transconductance VDD is stabilized 8.5 mA/V
tSU(HSE) (5) Startup time RS = 30Ω 2 mS
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer char-

acteristics Parameter.
3. For CL1 and CL2 , it is recommended to use high-quality external ceramic capacitors in
the 5 pF to 25 pF range (Typ.) , designed for high-frequency applications, and selected
to match the requirements of the crystal or resonator. CL1 and CL2 are usually the same
size. The crystal manufacturer typically specifies a load capacitance which is the series
combination of CL1 and CL2 . PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when
sizing CL1 and CL2 .
4. The relatively low value of the RF resistance can be used to avoid problems arising
from the use of wet conditions to provide protection, this environment resulting in leak-
age and bias conditions have changed. However, if the MCU is applied in bad wet
conditions, the design needs to take this parameter into account.
5. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a
stabilized 8 MHz oscillation is reached. This value is measured for a standard crystal
resonator and it can vary significantly with the crystal manufacturer.
䳶ᡀҶ⭥ᇩಘ
Ⲵ䉀ᥟಘ
CL1
OSC_IN fHSE
8MHz ໎⳺
RF ᧗ࡦ
䉀ᥟಘ
OSC_OUT
REXT:
CL2
095788
Figure 12. Typical application with an 8 MHz crystal
5.3.6 Internal clock source characteristics

The characteristic parameters given in the table below are measured using ambient tem-
perature and supply voltage in accordance with general operating conditions.
High-speed internal (HSI) oscillator

Table 19. HSI oscillator characteristics(1)(2)
fHSI Frequency 48 MHz

◦
TA = -40 C ∼
ACCHSI Accuracy of the HSI oscillator -3 3 %
105◦ C
ACCHSI Accuracy of the HSI oscillator TA = -10◦ C ∼ 85◦ C -2 2 %
◦ ◦
ACCHSI Accuracy of the HSI oscillator TA = 0 C ∼ 70 C -1 1 %
ACCHSI Accuracy of the HSI oscillator TA = 25 -1 1 %
tSU(HSI) HSI oscillator startup time 10 μS
HSI oscillator power
IDD(HSI) 200 μA
consumption
1. VDD = 3.3V, TA = - 40◦ C ∼ 105◦ C, unless otherwise specified.

Low-speed internal (LSI) oscillator

Table 20. LSI oscillator characteristics(1)
fLSI (2) Frequency 31 40 75 KHz

(2)
tSU(LSI) LSI oscillator startup time 100 μS
LSI oscillator power
IDD(LSI) (3) 1.1 1.7 μA
consumption
1. VDD = 3.3V, TA = -40◦ C ∼ 105◦ C, Unless otherwise stated

2. Comprehensive assessment, not tested in production.
Wake-up times from low power mode

The wake-up times listed in the table below are measured during the wake-up phase of
the internal clock HSI. The clock source used when waking up depends on the current
operating mode:
• Stop or Standby mode: The clock source is the oscillator

• Sleep mode: The clock source is the clock used when entering sleep mode
All times are measured using ambient temperature and supply voltage in accordance with
common operating conditions.
Table 21. Low-power mode wakeup timings
Symbol Parameter Conditions Max Unit
Wakeup from Sleep

tWUSLEEP (1) HSI clock wakeup 4.2 μS
mode
Wakeup from Stop
tWUSTOP (1) HSI clock wakeup < 2μS 12 μS
mode
HSI clock wakeup < 2μS
Wakeup from Standby
tWUSTDBY (1) The regulator wakes up 230 μS
mode
from the off mode < 30μS
1. The wake-up time is measured from the start of the wake-up event to the user program
to read the first instruction.
5.3.7 Memory characteristics

Flash memory
The characteristics are given at TA = - 40◦ C ∼ 105◦ Cunless otherwise specified.
Table 22. Flash memory characteristics
tprog 8-bit programming time 6 7.5 μS

tERASE Page (512K bytes) erase time 4 5 mS
tME Mass erase time 30 40 mS
Read mode 9 mA
IDD Supply current Write mode 7 mA
Erase mode 2 mA
Vprog Programming voltage 1.5 V
Table 23. Flash memory endurance and data retention(1)(2)
Endurance
(Annotation:
NEND Erase 20 K cycle
number of
times)
Data TA = 105◦ C 20
tRET Year
◦
retention TA = 25 C 100

2. Cycle tests are carried out in the whole temperature range.
5.3.8 EMC characteristics

Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)

While a simple application is executed on the device (toggling 2 LEDs through I/O ports) ,
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
• Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until a
functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
• FTB：A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 1000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in the following table. They are based on the EMS levels and
classes defined in application note.
Table 24. EMS characteristics
Symbol Parameter Conditions Level/Class
Fast transientvoltage burst

limits to be applied through VDD = 3.3V,TA =+25◦ C,
VEFT 100 pF on VDD and VSS fHCLK =96MHz.Conformingto 2A
pinsto induce a functional IEC 1000-4-4
disturbance
Designing hardened software to avoid noise problems

EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and pre-
qualification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
• Corrupted program counter

• Unexpected reset
• Critical Data corruption (for example control registers)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress can be applied directly on the device, over the range
of specification values. When unexpected behavior is detected, the software can be hard-
ened to prevent unrecoverable errors.
5.3.9 Absolute Maximum (Electrical Sensitivity)

Based on three different tests (ESD, LU) using specific measurement methods, the device
is stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)

Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This
test conforms to the JESD22-A114/C101 standard.
Static latch-up
Two complementary static tests are required on six parts to assess the latch-up perfor-
mance：
• A supply overvoltage is applied to each power supply pin

• A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD78A IC latch-up standard.
Table 25. ESD characteristics
Symbol Parameter Conditions Max(1) Unit
Electrostatic discharge voltage TA = +25◦ C, Conforming to

VESD(HBM) 6000
(Human body model) JESD22-A114
V
Electrostatic discharge voltage TA = +25◦ C, Conforming to
VESD(CDM) 500
(Charging device model) JESD22-C101
TA = +25◦ C, Conforming to
ILU Latch-up current 200 mA
JESD78A
5.3.10 I/O port characteristics

General input/output characteristics
Unless otherwise specified, the parameters given in Table 7 are derived from tests.
Table 26. I/O static characteristics
VIL (Hysteresis open) Low level input voltage CMOS Port 0.16VDD 0.2VDD V
VIH (Hysteresis open) High level input voltage CMOS Port 0.8VDD 0.84VDD V
VIL (Hysteresis close) Low level input voltage CMOS Port 0.33VDD 0.37VDD V
VIH (Hysteresis close) High level input voltage CMOS Port 0.58VDD 0.62VDD V
Vhys (Hysteresis open) Schmitt trigger hysteresis(1) 1.2 3 3.3 V
Vhys (Hysteresis close) (1)
Schmitt trigger hysteresis 0.5 1.2 1.4 V
Ilkg Input leakage current (2)
±1 µA
Weak pull-up equivalent
RPU VIN = VSS 28.7 36 47.9 kΩ
resistor(3)
Weak pull-down equivalent
RPD VIN = VDD 25 31.2 40 kΩ
resistor(3)
CIO I/O pin capacitance 5 pF
1. Schmitt Trigger switching hysteresis voltage level.Data based on design simulation

only. Not tested in production.
2. The leakage could be higher than the maximum value, if negative current is injected
on adjacent pins.
3. Pull-up and pull-down resistors are designed with a true resistance in series with a
switchable PMOS/NMOS. This PMOS/NMOS contribution to the series resistance is
minimal (10% order).
All I/Os are CMOS (no software configuration required). Their characteristics cover more
than the strict CMOS-technology.
• For VIH ：
– If VDD is between [2.50V∼ 3.08V]; use CMOS features.
– If VDD is between [3.08V∼ 3.60V]; include CMOS.
• For VIL ：
– Use CMOS features.
Output driving current

The GPIOs (general purpose input/outputs) can sink or source up to ±20mA.
n the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in 5.2：
• The sum of the currents obtained from VDD for all I/O ports, plus the maximum operating
current that the MCU obtains on VDD , cannot exceed the absolute maximum rating IVDD .
• The sum of the currents drawn by all I/O ports and flowing out of VSS , plus the maximum
operating current of the MCU flowing out on VSS , cannot exceed the absolute maximum
rating IVSS .
Output voltage levels

Unless otherwise stated, the parameters listed in the table below are measured using the
ambient temperature and VDD supply voltage in accordance with the condition of Table 10.
All I/O ports are CMOS compatible.
Table 27. Output voltage characteristics
Output low level voltage for an

CMOS Port,IIO = +8mA
VOL I/O pin,when 8 pins absorb 0.4 V
2V < VDD < 5.5V
current
Output high level voltage for an
CMOS Port,IIO = +8mA
VOH I/O pin,when 8 pins output VDD -0.4 V
2V < VDD < 5.5V
current
Output low level voltage for an
IIO = +20mA
VOL I/O pin,when 8 pins absorb 0.4 V
2V < VDD < 5.5V
current
Output high level voltage for an
IIO = +20mA
VOH I/O pin,when 8 pins output VDD -0.4 V
2V < VDD < 5.5V
current
Input/output AC characteristics
The definitions and values of the input and output AC characteristics are given in figure 13
and Table 28, respectively.
Unless otherwise stated, the parameters listed in Table 28 are measured using the ambient
temperature and supply voltage in accordance with the condition Table 7.
Table 28. I/O AC characteristics(1)
OSPEEDRy
[1:0] value (1)
Maximum CL = 50pF,
00 fmax(IO)out 2 MHz
frequency(2) VDD = 2V ∼ 5.5V
CL = 50pF,
00 tf(IO)out Output fall time 125 nS
VDD = 2V ∼ 5.5V
CL = 50pF,
00 tr(IO)out Output rise time 125 nS
VDD = 2V ∼ 5.5V
Maximum CL = 50pF,
10 fmax(IO)out 20 MHz
frequency (2)
VDD = 2V ∼ 5.5V
OSPEEDRy
[1:0] value (1)
CL = 50pF,
10 tf(IO)out Output fall time 25 nS
VDD = 2V ∼ 5.5
CL = 50pF,
10 tr(IO)out Output rise time 25 nS
VDD = 2V ∼ 5.5
CL = 30pF,
11 fmax(IO)out Maximum frequency(2) 50 MHz
VDD = 2V ∼ 5.5V
CL = 50pF,
11 fmax(IO)out Maximum frequency(2) 30 MHz
VDD = 2V ∼ 5.5V
CL = 30pF,
11 5 nS
VDD = 2V ∼ 5.5V
tf(IO)out Output fall time
CL = 50pF,
11 8 nS
VDD = 2V ∼ 5.5V
CL = 30pF,
11 5 nS
VDD = 2V ∼ 5.5V
tr(IO)out Output rise time
CL = 50pF,
11 8 nS
VDD = 2V ∼ 5.5V
Pulse width of external

tEXTIpw signals detected by the 10 nS
EXTI controller
1. The speed of the I/O port can be configured via MODEx[1:0]. See the description of
the GPIO Port Configuration Register in this chip reference manual.
2. The maximum frequency is defined in figure 13.
90% 10%
50% 50%
90%
10%
The external output
load is 50 pF tr (IO)out tr (IO)out
Maximum frequency is achieved if ((tr + tf) ≤ 2/3)T, and if the duty cycle is (45 ~ 55%)
when loaded by C/(see the i/O AC characteristics definition)
868304
Figure 13. I/O AC characteristics
5.3.11 NRST pin characteristics

The NRST pin input driver uses the CMOS technology. It is connected to a permanent
pullup resistor, RPU .
Unless otherwise stated, the parameters listed in the table below are measured using the
ambient temperature and VDD supply voltage in accordance with the condition of Table 10.
Table 29. NRST pin characteristics
VIL(NRST) (1) NRST input low level voltage -0.5 0.8

V
NRST input high level
(1)
VIH(NRST) 2 VDD
voltage
NRST Schmitt trigger voltage
Vhys(NRST) 0.2VDD V
hysteresis
Weak pull-up equivalent
RPU VIN = VSS 50 kΩ
resistor(2)
VNF(NRST) (1) NRST input not filtered pulse 300 ns
1. Data based on design simulation only. Not tested in production.

2. The pull-up is designed with a true resistance in series with a switchable PMOS. This
PMOS contribution to the series resistance is minimal (10% order).
External
reset circuit VDD
RPU Internal
NRST(2) reset
Filter
0.1µF
368560
Figure 14. Recommended NRST pin protection
1. The reset network is to prevent parasitic reset

2. The user must ensure that the potential of the NRST pin is below the maximum VIL(NRST)
listed in Table 29, otherwise the MCU cannot be reset.
5.3.12 Timer characteristics

The parameters given in the following tables are guaranteed by design.
For details on the characteristics of the I/O multiplexing function pins (output compare,
input capture, external clock, PWM output) , see subsubsec 5.3.10.
Table 30. TIMx(1) characteristics
tres(TIM) Timer resolution time 1 tTIMxCLK

fTIMxCLK =
tres(TIM) Timer resolution time 20.8 nS
48MHz
Timer external clock 0 fTIMxCLK
fEXT MHz
frequency on CH1 to CH4 fTIMxCLK =
0 48
48MHz
ResTIM Timer resolution 16 Bit
16-bit timer 1 65536 tTIMxCLK
tCOUNTER
maximum period fTIMxCLK 48MHz 0.02085 1633 µS
65536 × 65536 tTIMxCLK
tMAX_COUNT The maximum possible count
fTIMxCLK 48MHz 69.6 S
1. TIMx is a generic name, representing TIM1,2,3,14,16,17.
5.3.13 Communication interfaces

I2C interface characteristics
Unless otherwise specified, the parameters given in Table 31 are derived from tests per-
formed under the ambient temperature, fPCLK1 frequency and supply voltage conditions
summarized in Table 10: General operating conditions.
The I2C interface conforms to the standard I2C communication protocol, but has the fol-
lowing limitations: SDA and SCL are not true pins. When configured as open-drain output,
the PMOS transistor between the pin and VDD Was closed but still exists.
The I2C I/Os characteristics are listed in Table 31, the alternate function characteristics of
I/Os (SDA and SCL) refer to subsubsec 5.3.10.
Table 31. I2C characteristics
Standard I2C(1) Fast I2C (1)(2)
Symbol Parameter Unit
Min Max Min Max
tw(SCLL) SCL clock fall time 4.7 1.3 µs
tw(SCLH) SCL clock rise time 4.0 0.6 µs
tsu(SDA) SDA setup time 250 100
th(SDA) SDA data hold time 0(3) 0(4) 900(3)
ns
tr(SDA) tr(SDL) SDA and SCL rise time 1000 2.0+0.1Cb 300
tf(SDA) tf(SDL) SDA and SCL fall time 300 300
th(STA) Start condition hold time 4.0 0.6
tsu(STA) Start condition setup time 4.7 0.6
tsu(STO) Stop condition setup time 4.0 0.6 µs
Time from Stop condition to
tw(STO:STA) 4.7 1.3
Start condition
Cb Capacitive load of each bus 400 400 pF

2. fPCLK1 must be at least 3MHz to achieve standard mode I2C frequencies. It must be at
least 12MHz to achieve fast mode I2C frequencies.
3. The maximum Data hold time has only to be met if the interface does not stretch the
low period of SCL signal.
4. In order to span the undefined area of the falling edge of SCL, it must ensure that the
SDA signal has a hold time of at least 300nS.
VDD VDD
4.7KΩ 4.7KΩ
100 Ω
SDA
,&EXV 100 Ω
SCL
Start repeated
Start
t su(STA) Start
SDA
t f(SDA) t r(SDA) t su(SDA) t su(STA:STO)
Stop
t h(STA) t w (SCKL) t h(SDA)
SCL
t w (SCKH) t r(SCK) t f(SCK) t su(STO)
澳
130244
Figure 15. I2C bus AC waveform and measurement circuit(1)
1. Measurement point is set to the CMOS level：0.3VDD and 0.7VDD .
SPI characteristics
Unless otherwise specified, the parameters given in Table 32 are derived from tests per-
formed under the ambient temperature, fPCLKx frequency and VDD supply voltage condi-
tions summarized in Table 10.
Refer to subsubsec 5.3.10 for more details on the input/output alternate function charac-
teristics (NSS, SCK, MOSI, MISO).
Table 32. SPI characteristics(1)
Master mode 0 36
fSCK 1/tc(SCK) SPI clock frequency MHz
Slave mode 0 18
tr(SCK) SPI clock rise and fall
Load capacitance: C = 30pF 8 ns
tf(SCK) time
tsu(NSS) (2) NSS setup time Slave mode 4tPCLK ns
th(NSS) (2) NSS hold time Slave mode 73 ns
tw(SCKH) (2) Master mode，fPCLK = 36MHz，
SCK high and low time 50 60 ns
(2)
tw(SCKL) prescale coefficient = 4
Data input setup time,

tsu(SI) (2) 1 ns
Slave mode
Data input hold time,
th(SI) (2) 3 ns
Slave mode
Slave mode，fPCLK = 36MHz，
0 55
(2)(3)
ta(SO) Data output access time prescale coefficient = 4
Slave mode，fPCLK = 24MHz 4tPCLK
(2)
tdis(SO) Data output disable time Slave mode 10
tv(SO) (2)(1)
Data output valid time Slave mode (after enable edge) 25 ns
Master mode (after enable

tv(MO) (2)(1) Data output valid time 3
edge)
th(SO) (2) Slave mode (after enable edge) 25
Data output hold time
Master mode (after enable
th(MO) (2) 4
edge)
1. Data based on characterization results. Not tested in production.

2. Min time is for the minimum time to drive the output and the max time is for the maxi-
mum time to validate the data.
3. Min time is for the minimum time to invalidate the output and the max time is for the
maximum time to put the data in Hi-Z.
CPHA =0
CPOL = 1
CPOL = 0
MISO MSBit LSBit

(from master)
MOSI MSBit LSBit

(from slave)
NSS
(to slave)
CAPTURE STROBE
679527
Figure 16. SPI timing diagram-slave mode and CPHA = 0
CPHA=1
CPOL = 1
CPOL = 0
MISO
MSBit LSBit
(from master)
MOSI
MSBit LSBit
(from slave)
NSS
(to slave)
CAPTURE STROBE
429658
Figure 17. SPI timing diagram-slave mode and CPHA = 1(1)
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD .
High
NSS INPUT
t c(SCK)
CPHA = 0
SCK Output
CPOL = 0
CPHA = 0
CPOL = 1
CPHA = 1
SCK Output
CPOL = 0
CPHA = 1
CPOL = 1
t w (SCKH) t r (SCK)
t su(MI ) t w (SCKL) t f (SCK)
MISO INPUT MSB IN BIT6 IN LSB IN
t h(M )
MOSI OUTPUT MSB OUT BIT6 OUT LSB OUT
t v(MO ) t h(MO )
184118
Figure 18. SPI timing diagram-master mode(1)
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD .
5.3.14 12-bit ADC characteristics

Unless otherwise specified, The parameters in the table below are measured using the
ambient temperature, fPCLK2 frequency and VDDA supply voltage in accordance with the
conditions of Table 10.
Note: It is recommended to perform a calibration after each power-up
Table 33. ADC characteristics

Symbol Parameter Conditions Min Type Max Unit
VDDA Supply voltage 2.5 3.3 5.5 V

Positive reference
VREF+ 2.5 VDDA V
voltage
ADC clock
fADC 15(1) MHz
frequency
Symbol Parameter Conditions Min Type Max Unit
fS (2) Sampling rate 1 MHz

External trigger fADC = 15MHz 823 KHz
fTRIG (2)
frequency 1/17 1/fADC
0 (VSSA or
Conversion voltage
(2)
VAIN VREF− connected VREF+ V
range(3)
to ground)
External sample
RAIN (2) See Formulas 1 and Table 34 kΩ
and hold capactor
Sampling switch
RADC (2) 1 kΩ
resistance
Internal sample and
CADC (2) 10 pF
hold capacitor
fADC = 15MHz 0.1 16 µs
tS (2) Sampling time
1.5 239.5 1/fADC
(2)
tSTAB Stabilization time 1 µs
Total conversion fADC = 15MHz 1 16.9 µs

tconv (2)
time 15 ∼ 253 (sampling tS+ ) stepwise
1/fADC
(including Sampling approximation 13.5
time)
1. Guaranteed based on test during characterization. Not tested in production.
2. Guaranteed by design. Not tested in production.
3. In this series of products, VREF+ is internally connected to DDA ，VREF− is internally
connected to SSA .
TS
RAIN < − RADC
fADC × C ADC × In(2N+2 )
The formula above (Equation 1) is used to determine the maximum external impedance
allowed for an error below 1/4 of LSB. Here N = 12 (from 12-bit resolution) .
Table 34. Maximum RAIN at fADC = 15MHz(1)

TS (cycles) tS (µs) RAIN max (kΩ)
1.5 0.1 1.2

7.5 0.5 30
13.5 0.9 57
28.5 1.9 123
41.5 2.76 180
55.5 3.7 240
71.5 4.77 312
239.5 16.0 1050
Table 35. ADC Accuracy - Limit Test Conditions(1)(2)

Symbol Parameter Test Conditions Type Max(3) Unit
ET Comprehensive error ±10 ±14

EO Offset error fPCLK2 = 60MHz,fADC = ±4 ±10
EG Gain error 15MHz,RAIN < 10KΩ,VDDA ±6 ±8 LSB
ED Differential linearity error = 5V，TA = 25◦ C ±2 ±4
EL Integral linearity error ±4 ±6
1. ADC Accuracy vs. Negative Injection Current: Injecting negative current on any of
the standard (non-robust) analog input pins should be avoided as this significantly
reduces the accuracy of the conversion being performed on another analog input. It is
recommended to add a Schottky diode (pin to ground) to standard analog pins which
may potentially inject negative current.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in
subsubsec 5.3.11 does not affect the ADC accuracy.
ET = Total unadjusted error: The maximum deviation between the actual and ideal trans-
mission curves.
EO = Offset error: The deviation between the first actual conversion and the first ideal
conversion.
EG = Gain error: The deviation between the last ideal transition and the last actual transi-
tion.
ED = Differential linearity error: The maximum deviation between the actual step and the
ideal value.
EL = Integral linearity error: The maximum deviation between any actual conversion and
the associated line of the endpoint.
Sanple and hold

ADC converter
RAIN(1) AINx RADC(1) 12-bit
converter
Cparasi c(2)
VAIN
CADC(1)
Parasi c
capacitance
439454
Figure 19. Typical connection diagram using the ADC
1. See Table 35 for the values of RAIN , RADC and CADC .

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB
layout quality) plus the pad capacitance (roughly 7pF) . A high Cparasitic value will
downgrade conversion accuracy. To remedy this, fADC should be reduced.
PCB design recommendations

The power supply must be connected as shown below. The 10nFcapacitor in the figure
must be a ceramic capacitor (good quality) , and they should be as close as possible to
the MCU chip.
VDDA
VDDA
1 µF // 10 nF
VSSA
澳
326818
Figure 20. Power supply and reference power supply decoupling circuit
5.3.15 Temperature sensor characteristics

Table 36. Temperature sensor characteristics(3)(4)
Symbol Parameter Min Type Max Unit
VSENSE linearity with respect to

◦
TL (1) ±5 C
temperature
Avg_Slope(1) Average slope 4.571 4.801 5.984 mV/◦ C
V25 (1) Voltage at 25◦ C 1.433 1.451 1.467 V
(2)
tstart Setup time 10 µs
ADC sampling time when
TS_temp (2) 10 µs
reading temperature

3. The shortest Sampling time can be determined by the application through multiple
iterations.
4. VDD = 3.3V.
Package information
6 Package information
Package information
6.1 QFN20 Package information
A2
D
A
e A1
A3
K
b
C2
R c1
E2
E
b H
1
L
20
L
PIN 1 Identifier
D2
926545
Figure 21. QFN20 - 20-pin quad flat no-leads package outline
1. Drawing is not to scale.

2. Dimensions are expressed in millimeters.
Package information
Table 37. QFN20 mechanical data

Millimeters
Symbol
Min Typ Max
A 0.70 0.75 0.80
A1 0.00 0.02 0.05
A2 0.50 0.55 0.60
A3 0.20REF
b 0.15 0.20 0.25
D 2.90 3.00 3.10
E 2.90 3.00 3.10
D2 1.40 1.50 1.60
E2 1.40 1.50 1.60
e 0.30 0.40 0.50
H 0.35REF
K 0.35REF
L 0.35 0.40 0.45
R 0.085
C1 0.07
C2 0.07
N Number of pins = 20
Package information
6.2 TSSOP20 Package information
20 11
E1
c
1 10
PIN1
IDENTIFICATION
SEATING
PLANE
aaa C 0.25 mm
C GAUGE PLANE
A A2
k
b e L
A1
L1
618013
Figure 22. TSSOP20 - 20-lead thin shrink small outline package outline
1. Drawing is not to scale.

2. Dimensions are expressed in millimeters.
Table 38. TSSOP20 mechanical data

Millimeters
Symbol
Min Typ Max
A 1.20
A1 0.05 0.15
A2 0.08 1.00 1.05
b 0.19 0.30
c 0.09 0.20
D 6.40 6.50 6.60
E 6.25 6.40 6.55
E1 4.30 4.40 4.50
Package information
Millimeters
Symbol
Min Typ Max
e 0.65
L 0.45 0.60 0.75
L1 1.00
N Number of pins = 20
Revision history
7 Revision history
Revision history
Table 39. Document revision history

Revision Changes Date
Rev1.00 Initial release. 2018/8/24
Rev1.06 Modify pin definition. 2018/8/26
Rev1.07 Modify electrical parameters. 2018/9/6

32-Bit Micro Controller Based On ARM Cortex M0

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Datasheet

32-bit Micro controller based on ARM Cortex M0

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• Motor drive and application control

1.2 Product Features

– 2.0V ∼ 5.5V application supply

2.1 Device contrast

2.2.1 ARM® CortexTM -M0 and SRAM

2.2.4 Nested vectored interrupt controller (NVIC)

• Closely coupled NVIC gives low latency interrupt processing

2.2.5 Extended interrupt/event controller (EXTI)

2.2.6 Clocks and startup

2.2.7 Power supply schemes

2.2.8 Power supply supervisors

2.2.9 Voltage regulator

2.2.10 Low-power modes

2.2.11 Direct memory access controller (DMA)

DMA can be used with the main peripherals: UART、I2C、SPI、ADC general-purpose

and advanced-control timers TIMx.

2.2.12 Timers and watchdogs

The following table compares the features of the different timers:

Table 2. Timer feature comparison

Advanced-control timer ( TIM1 )

General-purpose timers (TIMx)

General-purpose timers 16-bit

Independent watchdog (IWDG)

System window watchdog (WWDG)

• A 24-bit down counter

2.2.13 Universal asynchronous receiver/transmitter (UART)

All UART interface can be served by the DMA controller.

2.2.14 I2C interface

2.2.15 Serial peripheral interface (SPI)

All SPI interface can be served by the DMA controller.

2.2.16 General-purpose inputs/outputs (GPIO)

2.2.17 Analog-to-digital converter (ADC)

2.2.18 Hardware Dvision

If the divisor is zero, an overflow interrupt flag will be generated.

2.2.19 Temperature sensor

2.2.20 Serial single line SWD debug port (SW-DP)

AHB Flash Flash

AHB APB1 APB1

AHB APB2 APB2

ADC1 PWR TIM3

Figure 1. Block diagram

If (APB1 Prescaler=1) x 1 TIMXCLK

If (APB2 Prescaler=1) x 1 TIMXCLK

If (APB2 Prescaler!=1) TIM.ADV

Figure 2. Clock tree

Figure 3. TSSOP20 packet pinout

Figure 4. QFN20 packet pinout

Table 3. Pin definitions

Pin number I/O Main Alternate Additional

Pin number I/O Main Alternate Additional

1. I = input, O = output, S = power supply, HiZ = high resistance.

Table 4. Alternate functions

Table 5. Additional functions

Table 6. Memory mapping

Bus Boundaryaddress Size Peripheral Notes

5.1 Parameter conditions