Memory Systems

LECTURE 3
 Memory Systems
• Memory systems in computing refer to the
hierarchical structure of memory devices and
their organization within a computer system.
• These systems store and manage data and
instructions used by the CPU and other
components during the execution of
programs.
• Memory is one of the four basic components of a
computer system. This unit stores programs and
data on which the computer operates.
• The performance (operation speed) of a
computer system is dependent on how fast
programs and data are transferred between the
memory and the Central Processing Unit (C P U).
It is important to have a memory that is large
enough to facilitate the execution of programs
that are large and also to deal with large amounts
of data.
Ideally a user would prefer a memory that is fast,
large and less expensive.
It is however not possible to meet these three
requirements simultaneously.
Increased speed and size of memory is achieved
at increased cost.
Memory designers have done a lot of work in
developing clever structures that improve the
speed and size of memory, but still keeping the
cost reasonable(affordable).
 Basic concepts
Just like in any other field, there are some basic
concepts and terminologies that must be
known or used in order to understand better
that particular field.
Byte = 8 bits (Character) is a standard used to
measure memory capacity.
 Basic concepts
Word is not standard as it depends very much on
the computer being used.
In a 16- bit address machine, the word size would
be 16 bits (2 bytes) while on a 32-bit address
machine the word size would be 32 bits (4 bytes).
It is however simple to calculate the memory
capacity in bytes or words as the case may be
since the byte is standard.
• The maximum size of memory that can be used
on any computer is determined by the addressing
scheme of that particular computer, for example
a 16-bit computer generates 16-bit addresses up
to 216 = 64 K memory locations.
• Similarly, machines whose instructions generate
32-bit addresses can utilize a memory that
contains up to 232 = 4 G (gigabytes). The numbers
of memory locations represent the address space
of the computer.
Memory is designed to store and retrieve data in
word length quantities.
The idea is to reduce the frequency of memory
access by the processor.
A computer that retrieves a byte at a time would
be slower that a computer that retrieve a
word at a time.
• Memory speed is a useful measure of memory
performance and it can be memory access
time – the time that lapses between the
initiation of an operation and the completion
of that operation as indicated by the memory
function complete (MFC) control signal, for
example the time between the initiation of a
Read operation and the MFC, or it can be
memory cycle time.
• Memory cycle time is the minimum time delay
required between the initiation of two successive
memory operations, for example minimum time
delay between two Read operations and the
MFC. Memory cycle time is slightly longer than
memory access time.
• This is due to the fact that when memory is
organized in blocks of data, it takes more time to
fetch the first word in the block and less time to
fetch the following (next) word in the block.
It is necessary to note here that memory cycle
time is used to measure performance when
data is organized in blocks, say 8 words per
block, 16 words per block, 32 words per block
excetra excetra.
The figures, for example 8, 16, and 32 are known
as blocking factors.
Processor Memory Organization
MAR is short for memory address register.
This register has its output connected to the
address bus. This register makes it possible for
the CPU to communicate with the address bus.
The MAR can hold two different kinds of addresses:
• It can either store the address of an instruction,
or it can store the address of data, which means
all addresses whether of instructions or
operational data must pass through this register.
As can be observed from the diagram above, the
flow of addresses is uni-directional.
MDR is short for memory data register. The
MDR is used with the data bus.
The MDR has more operations than just placing
the data on the data bus. Data can go both
ways. For example, for a load operation, data
is read from the data bus into the MDR and
then loaded into one of the CPU registers and
for a store operation data is placed onto the
data bus.
This means that the MDR can (parallel) load its
data from one of two places:
the data bus (for a load operation) and some
where else in the CPU (for a store operation).
• The control lines constitute the control bus
which is used by the CPU for communicating
with other devices within the computer.
• The number and type of lines in a control bus
varies but there are basic lines common to all
microprocessors, such as: Read (R), a single
line that when active (logic 1) indicates the
device is being read by the CPU, Write ( W), a
single line that when active (logic 0) indicates
the device is being written to by the CPU,
Then Byte enable (E ), a group of lines that
indicate the size of the data (8, 16, 32, 64
bytes), MFC, a single line used by a device to
communicate with the CPU, for example
assume a memory has been assigned a read
operation. After finishing the read operation,
memory sends an MFC (memory function
complete) to alert the CPU that the assigned
operation has been completed
RAM stands for Random Access Memory. A
memory unit is called random access memory
(RAM) if any of its memory locations can be
accessed for a read or write operation in some
fixed amount of time that is independent of the
location’s address.
The RAM memory is distinguished from sequential
or partial sequential access storage devices such
as magnetic tapes and disks. Access times on
magnetic tapes or disks depend on the address or
position of the data.
 Memory Hierarchy
• Memory hierarchy refers to the arrangement
of different types of memory storage in a
computer system, organized in levels based on
their speed, capacity, and cost.
• This hierarchy includes various levels such as
registers, cache, main memory, secondary
storage (e.g., hard disks), and tertiary storage
(e.g., tape)
• The memory hierarchy is designed to optimize
speed, capacity, cost, and accessibility.
• The problems faced by memory designers can
be summed up by three questions:
• How much capacity?
• How fast?
• How expensive?
• The capacity, speed and cost cannot be met
simultaneously. Ideally a user needs a large
memory capacity that is fast and inexpensive.
Since the three cannot be met simultaneously,
there is always a trade-off (compromise)
among these three key characteristics of
memory.
 A variety of technologies are used to implement
memory systems, and across the spectrum of
these technologies, the following relationships
hold:
• Faster access time, greater cost per bit
• Greater capacity, smaller cost per bit
• Greater capacity, slower access time.
The memory system designer wants to use
memory technologies that provide large
memory capacity because it is needed and
cost per bit is small or low.
The designer’s problem is solved by not relying
on one or a single memory technology but
employing a memory hierarchy
As one goes down the hierarchy the following
occur:
• Decreasing cost per bit
• Increasing capacity
• Increasing access time
• Decreasing frequency of access of memory by
the Processor
This means that the smaller, more expensive,
faster memories are supplemented by larger,
cheaper and slower memories.
The key to success of this organization
(memory hierarchy) is decreasing frequency of
access.
 1. Registers
• Registers are the fastest and smallest storage
units within the CPU.
• Functionality: They store data and
instructions that the CPU is currently
processing or about to process.
• Access Time: Extremely fast access times,
typically in nanoseconds.
• Capacity: Very limited capacity, usually a few
dozen or hundred bytes.
 2. Cache Memory
• Cache memory is a small-sized type of volatile
computer memory that provides high-speed data
access to a processor and stores frequently used
computer programs, applications, and data.
• Functionality: It acts as a buffer between the CPU
and the main memory (RAM), storing frequently
accessed data to speed up CPU operations.
• Access Time: Faster than main memory but
slower than registers, typically in a few
nanoseconds.
• Capacity: Limited capacity compared to main
memory, usually in the range of a few MB.
 3. Main Memory (RAM - Random
Access Memory)
• Main memory is the primary volatile memory in a
computer system, providing space for the
operating system, applications, and data in use.
• Functionality: It holds data and instructions that
are actively being used or processed by the CPU.
• Access Time: Slower than cache memory but
faster than secondary storage, typically measured
in nanoseconds.
• Capacity: Considerably larger than cache
memory, ranging from a few gigabytes to several
gigabytes.
 4. Secondary Storage (Hard Disk
Drives, Solid State Drives, etc.):
• Secondary storage consists of non-volatile
memory devices used for long-term data storage.
• Functionality: It stores data that is not
immediately needed for processing and provides
a means for permanent data storage.
• Access Time: Significantly slower than main
memory, usually measured in milliseconds or
even longer.
• Capacity: Large capacity, often in terabytes (TB)
or more.
 5. Tertiary Storage (Tape Drives,
Optical Discs, etc.):
• Tertiary storage is used for archival purposes
and long-term backup.
• Functionality: It provides a very large storage
capacity but with slower access times
compared to secondary storage.
• Access Time: Slower than secondary storage,
often measured in seconds or longer.
• Capacity: Extremely large capacity, ranging
from hundreds of terabytes to petabytes
Semi-Conductor RAM memories are available in
a range of speeds and their cycle times range
from 100 nanoseconds to less than 10
nanoseconds.
These were expensive at first but with the
introduction of very large scale integrated
circuits(VLSI) the prices have gown down
considerably.
 Speed Imbalance
• Speed imbalance occurs within the memory
hierarchy due to the disparity in access times
between different levels of memory.
• Registers and cache have very low access
times, whereas main memory (RAM) and
secondary storage devices like hard drives
have higher access times.
• This speed difference creates challenges in
optimizing memory usage and access
patterns.
Need for Optimization of memory
• Optimization of memory usage is essential to
minimize the impact of the speed imbalance
in the memory hierarchy.
• This involves efficient algorithms, data
structures, and access patterns to maximize
the use of faster, smaller memory (e.g., cache)
and minimize the need for slower, larger
memory (e.g., RAM, secondary storage).
Structure and Characteristics of Memory Types

Static RAM (SRAM)

Static Random Access memories are capable of
retaining theirs state as long as power supply
is not interrupted
• Its fast, expensive, and used for cache
memory.
• It also utilizes flip-flops for storage and does
not require refreshing.
1-bit RAM cell
• SRAM cell is made up of 2 inverters that are
cross-connected to form a latch. The latch is
connected to 2 bit lines by transistors T1 and
T2. The transistors, T1 and T2 can be switch
opened or closed under control of word line.
When word line is ground level, the transistors
are turned off and the latch retains its state.
 RAM operation
Read operation
During the read operation, word line is
activated to close transistors T1 and T2.
If the cell is in binary state 1, the signal on b
line is high and the signal on line is low. The
opposite is true if the cell is in binary state
0.Thus, b and are always complements of
each other.
The sense /write circuit at the end of the two
bit line monitors their state and sets the
 Writing to a RAM cell
Write operation
During the write operation, the Sense/Write
circuit drives bit lines b and , instead of sensing
their state. It places the appropriate value on bit
line b and its complement on and activates the
word line. This forces the cell into the
corresponding state, which the cell retains when
the word line is deactivated.
The SRAMs are accessed very quickly. SRAMS
with access times of a few nanoseconds are
found in commercially available chips.
 Circuit diagram operation
When a binary o is applied at the Read/Write control line,
the input line is connected to the RS latch. Select line is
set always set to high.
The appropriate voltage to be stored in the latch is
supplied at the input line. R is 0 and S is 1. This means
that the value is stored at Q is 0. For a Read operation,
a binary 1 is applied at the Read/Write.
This separates the input line from the RS latch. Select line
is set to 1 and value stored at Q is transferred to the
AND gate where the output is collected.
Asynchronous Dynamic Random
Access Memory (DRAM)
DRAM stores each bit in a storage cell consisting
of a capacitor and a transistor.
Capacitors tend to lose their charge rather
quickly; thus, the need for recharging.
The presence or absence of charge in the
capacitor determines whether the cell
contains a binary 1 or 0.
• DRAM (Dynamic Random Access Memory) is
slower than SRAM but more cost-effective and
used for main memory.
• It requires periodic refreshing to maintain data
integrity.
DRAM cell
Read operation

• During the read operation, the bit line is

charged to an intermediate value, VDD / 2. The
word line is raised to a high potential and the
charge stored on capacitor is shared with VDD /
2 that is on the bit line. The change in the bit
line voltage is given by the change on the bit
line capacitor when the charge stored on
capacitor C is shared with the bit line. The
voltage in the capacitor is sensed by an
amplifier circuit through the bit line.
The sense circuit is able to determine whether a
binary zero (0) or a binary one(1) is stored in the
cell by comparing the sensed capacitor voltage
against a threshold, for example 50% of the full
charge voltage(charged capacitor) represents a
binary 1 and less 50%(discharged capacitor),
represents a binary 0.
The DRAMs are the predominant choice for
implementing computer main memories.
The high densities achievable in these chips make
large RAM memories feasible
Read Only Memories

Both SRAM and DRAM are volatile, that is, they lose
the stored information when power supply is
interrupted or turned off. Many applications
require devices that retain data or information
even after power has been turned off and later
supplied. Examples include a computer’s hard
disk drive used to store large volumes of
information, including operating system software.
When a computer is turned on, operating system
software has to be loaded from the disk into
memory (RAM).
This requires the execution of a program
that ‘boots’ the operating system.
The boot program is large, so it must be
stored on a disk.
The processor (CPU) executes some
instructions that load the boot program
into memory (RAM).
 ROM circuit operation
The switch (P) operates as follows:
Connect to the ground to store a binary zero (0)
in the cell.
Disconnect to store a binary one (1).
To store a value 0 (binary zero) in the cell, the
transistor (T) is connected to the ground at
point P (switch). If the transistor is
disconnected from the ground at point P,
a value of binary one (1) is stored in the cell.
The binary value to be stored is applied at the
bit line.
 Reading cell contents
To read the contents of the cell, the word line is
activated.
The transistor switch is closed (connected to the
ground) and the voltage on the bit line drops to
near zero. If there is no connection to the ground
at point P, the bit line remains high indicating a
binary one (1).
A sense circuit which is connected at the end of the
bit line generates the proper output value. Data is
written to a ROM when it is manufactured.
 Direct Memory Access (DMA)
• This is a technique that allows peripheral devices to access
the system's main memory (RAM) directly without
involving the CPU.
• Purpose:
– Reduces the load on the CPU by letting peripheral devices
transfer data to and from memory without CPU intervention.
– Enhances system performance by optimizing data transfer
between memory and I/O devices.
• Working:
– A DMA controller manages data transfers between memory
and devices.
– The CPU sets up the DMA controller with the source,
destination, and transfer size.
– DMA controller transfers data directly between memory and
the device without CPU involvement once configured.
 Halt Mode
• This refers to a state in which a processor
temporarily stops its execution, often to save power
or reduce unnecessary processing.
• Purpose:
– Conserves energy by reducing power consumption when
the system is idle or not processing tasks.
– Extends the lifespan of electronic components by
reducing their usage when not required.
• Activation:
– Triggered by hardware or software, putting the CPU into a
low-power state.
– Can be exited by specific events, like an external interrupt
or a certain time delay.
 Interleaved
• This is a method to improve memory access time
by distributing data across multiple memory
modules.
• Purpose:
– Enhances memory access speed by allowing multiple
memory accesses simultaneously.
– Reduces memory bottlenecks, especially in systems
with high memory demands.
• Working:
– Data is divided and stored across multiple memory
modules in an interleaved manner.
– When the CPU requests data, it can be retrieved in
parallel from multiple memory modules.
 Transparent Mode
• This is a state where a device operates without
requiring user intervention or configuration.
• Purpose:
– Simplifies user experience by minimizing the need for
manual configuration.
– Enhances device usability and ease of operation.
• Usage:
– Commonly used in networking and communication
devices, where they automatically adapt to network
changes without user input.
 Alternative Memory Types
• These refer to different forms of memory other than
traditional RAM (Random Access Memory).
• Examples:
– Cache Memory:
• Faster than main memory, used to store frequently accessed data to
speed up CPU operations.
– ROM (Read-Only Memory):
• Non-volatile memory containing permanent data that cannot be
modified.
– Flash Memory:
• Non-volatile and rewritable memory used in various devices like USB
drives, memory cards, and SSDs.
– Virtual Memory:
• A portion of the hard disk used as an extension of RAM to increase
available memory for the operating system and applications
 Revision questions
• List and briefly explain three alternative
memory types.
• Describe what Transparent mode is and
provide an example of a device or system that
operates in this mode.
• Define interleaved memory and explain how it
enhances memory access speed.
• Describe what Halt mode is and why it is used
in computing systems.
• Explain the purpose of Direct Memory Access
(DMA) and how it reduces the CPU's workload
during data transfers.
• Explain the need for optimizing memory and the
strategies involved.
• Elaborate on the speed imbalance in the memory
hierarchy and its implications.
• Describe the characteristics and differences
between SRAM and DRAM.
• Explain the concept of the memory hierarchy and
its significance in computer systems.
• Explain the purpose of secondary storage in a
computer system and discuss its
characteristics.
• Describe the role of cache memory in the
memory hierarchy and how it impacts CPU
performance.
• Compare and contrast registers and main
memory (RAM) in terms of their capacity and
access times.