8-bit Time-Interleaved ADC Simulation and INL (all done in LSB units) as the difference between each

Characterization measured current code and the ideal code (for every step):
V ' [current_code]
INL= −ideal_code=V ' [current_code]LSB −ideal_code
V LSB
1. Preparation: As required the chapter 17 of the textbook and
the course slides were reviewed for this assignment. Note there Now the definition of the cadence INL measurement block from
was an error in the INL formula described for the previous our previous assignment is precisely equivalent but here the LSB
assignment corrected here. voltage is the “measured” LSB voltage (INL Cadence
measurement block definition):
2. 8-bit ADC Simulation and Characterization:
V [current_code]
First, the 8-bit ADC test-bench was put together as required in the INL= −ideal_code=V ' [current_code ]LSB −ideal_code
V ' LSB
assignment write-up, with a 1.1V reference and clock signal at
Fs=8GHz (in my case) with 5pS rise and fall times. Subsequently Having the INL measurement, calculating the DNL equates to just
an ideal 8-bit DAC was used to convert the binary code generated taking the difference from adjacent INL measurements.
by the ADC back to the analog domain for taking measurements. Alternatively one can compute the DNL – as the difference in the
(see figure 2 for ADC test-bench) step size from the ideal step size – directly from the offset-free
gain-free values as follows (equivalent book definition and
2a. INL and DNL measurements (0% mismatch factor) Cadence DNL measurement block definition respectively):
Initially a modified version of the adc_inl and adc_dnl (V ' [next_code ]−V ' [current_code ])−V LSB
DNL= =Vstep LSB−1 LSB
measurement blocks from the ahdl library were used, however the V LSB
measured ideal ADC INL and DNL results were incorrect (when (V [next_code ]−V [current_code ])−V ' LSB
compared to both by-hand post-processing and expectations from DNL= =Vstep LSB −1 LSB
V ' LSB
the reference textbook and on-line sources). Hence, we opted for
manual post-processing of the DAC analog output data using (It was this DNL formula that was mislabeled as INL in
spreadsheet software (LibreOffice Calc) to compute the INL and assignment 5)
DNL measurements for our ADC. For our ideal ADC with 0 mismatch, we can see our INL is below
The normal set-up to measure INL and DNL is to provide a ramp +/- 0.5 LSB and the DNL is below 1 LSB indicating ideal
input to the ADC under test, here with a clock of 8GHz (or 1 performance. (see figures 2a2 and 2a3 for the measured INL and
sample converted every 125pS) and given 8 bits of resolution, we DNL respectively).
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have to cover 2 or 256 samples. Therefore, the rise time for 2b. INL and DNL Measurements (1% mismatch factor)
our input waveform t rise≥125 pS x 256=32 nS to cover every In this next question we are asked to provide a 1% mismatch factor
digital code or conversion step. (See figure 2a1 for the input ramp to the ADC block. Inspecting the source for the cell we can see
and DAC output steps waveform) first that the implementation of the ADC block is of an algorithmic
We then exported the raw DAC output data to a CSV file through type:
the results explorer and post-processed the data with spreadsheet • If Vin is greater than half Vref: the bit is set to 1 and half
software , basically: (1) Flag and copy only a single sample from
Vref is subtracted from the input then doubled, the result
each DAC output step and (2) enumerate the copied samples with
is then re-applied to the input.
appropriate digital codes from 0 to 255. (this manual cleanup
process was made simple by appropriately choosing the ramp • If Vin is lower than half Vref: the bit is unset to 0 and the
properties above) input voltage is doubled, the result then is re-applied to
Calculating INL and DNL (based on book definition) the input.
(INL definition from previous assignment corrected here) We can also see that the mismatch factor represents a small
random error in the comparator reference voltage proportional to
The Integral Non-linearity (INL) is the output response deviation
the percent of mismatch provided as a parameter to the block. This
from a straight line (after both offset and gain errors have been
effect is analogous to random offset present in a comparator, which
removed). Here the difference between the straight line and the
if significant enough can lead to the comparator outputting a 0
DAC output voltage at every digital code (in LSBs) is the INL.
when it should have been a 1 for the LSBs (the smallest input
Hence for our data, to be able to compute the INL, we have to
amplitudes), giving rise to missing codes for the ADC.
remove gain and offset errors, then we would be able to compare
with the ideal (straight line) response. Thus removing gain and Subsequently we plotted the response of the non-ideal ADC to the
offset errors for each sample (Here V LSB is the ideal value): same input ramp as before (see figure 2b1 for the input ramp and
DAC output steps waveform and figures 2b2 and 2b3 for the
V [current_code] current_code
V [current_code] LSB= −E offset −( )x E gain measured INL and DNL respectively), from our transient response
V LSB 2N −1 we can see there are some missing steps or missing codes due to
where in our case (ideal ADC with no mismatch): the 1% mismatch factor, equivalently we can see the INL and DNL
Eoffset =V [0]/V LSB=0 LSB measurements are lower than -0.5 LSB and equal to -1 LSB
V [last_code ]−V [0] respectively at 3 digital codes: 3, 104 and 205.
E gain= −last_code=0 LSB
V LSB 2c. SNDR and ENOB vs. Input Amplitude
Hence, for our ideal ADC case our offset-free gain-free values are For this section we vary the input signal amplitude from 2.5 mV to
the same as our measured values. Therefore we can calculate our 550mV (steps chosen: 2.5mV, 25mV, 250mV and 550mV) keeping
the input frequency at 100MHz. Then we compute the SNDR as
for previous assignments (fundamental minus largest harmonic in performance comparison of both ADCs is to compare the SNDR
dB) and the ENOB as: ENOB=( SNDR−1.76 dB)/ 6.02 (see and ENOB figures of merit at each test frequency.
figure 2c1 for the transient response and DFT at the output at a In the case of the single ADC for example the SNDR drops below
550mV input amplitude, see figures 2c2 and 2c3 for the SNDR 0dB at 4.1GHz (which means the input signal can not be recovered
and ENOB vs. input amplitude). The ENOB at full scale for our and it is indistinguishable from the distortion harmonics) as
ADC with the 1% mismatch factor is 5.829 bits. expected given Fs/2 is 4GHz, and even looking at 1.1GHz we can
2d. SNDR and ENOB vs. Input Frequency start to see some aliasing in the transient response with the ENOB
Next, we vary the input frequency from 100MHz to 6.1GHz figure dropping below 2.5 bits; at the greater frequencies of 2.1
keeping the input amplitude at full scale 550mV, then we compute and 3.1GHz aliasing becomes very prominent with the ENOB
the SNDR and ENOB as before (See figures 2d1 and 2d2 for the figure nearing 1.5 bits.
SNDR and ENOB vs. input frequency). Lastly we compute the For the 2x time-interleaved ADC on the other hand the SNDR
effective resolution bandwidth: frequency over which a converter’s remains positive (11.787dB) all the way up to 6.1GHz as expected
peak SNDR is within 3db (or ENOB within 0.5 bits) of it’s peak given that our effective Nyquist frequency is now 8GHz, our
value. From the slope of the first two frequency points taken, the ENOB figure drops below 2.5 bits only after 3.1GHz where we
point at which the ENOB is 0.5 bits less than that the peak is: start to see some aliasing in the transient response and aliasing
BW eff =244.134 MHz becomes more prominent only after 4.1GHz.
3. 2x Time-int. 8bit ADC Simulation and Characterization Compared to the output of a single DAC, the combined output of
the two DACs (the time-interleaved ADC) is effectively as if we
For this section the setup was exactly as before with a couple of
had a single ADC clocked at twice the actual sampling frequency
added components: an additional ADC channel (and test DAC),
or Fs = 2Fs = 16GHz, this is because each interleaved ADC
non-overlapping clock signals – 5pS rise and fall times, 25% duty
samples the input signal half a period after the other ADC, together
cycles (31.25pS) and a delay of half a period (62.5pS) for the
taking two samples per sampling period: effectively doubling the
second interleaved channel – and finally an ideal analog
sampling clock or equivalently the bandwidth of analog input
multiplexer (analog_mux from ahdlLib) was used to combine both
signals that can be converted to a digital representation.
DAC analog outputs. (See figure 3 for the ADC testbench)
Hence to conclude, with our 2x time interleaved ADC, we have
3a. INL and DNL measurements (1% mismatch factor)
effectively doubled sampling rate – the bandwidth of input
Here to provide a ramp input to the ADC under test, we have to frequencies our ADC can process – the ENOB at full-scale and
remember that a 2x interleaved ADC can convert two samples low frequencies (100MHz) is only 0.5 bits below the 8bits on-
every Fs = 8GHz clock cycle (i.e. 2 samples for every 125pS), this paper-spec, and the SNDR and ENOB FoMs are much superior at
is equivalent to a single ADC with Fs = 16GHz (or 1 sample every every test frequency than those measured from our single ADC;
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62.5pS). Now given 8 bits of resolution, we have to cover 2 or here our results match our expectation for a 2x time-interleaved
256 samples. Therefore, the rise time for our input waveform converter.
t rise≥62.5 pS x 256=16 nS to cover every digital code or
conversion step. (See figure 3a1 for the input ramp and DAC
output steps waveform)
Then, we exported the raw DAC output data to a CSV file and
post-processed the data with spreadsheet software to calculate the
INL and DNL error measurements (same procedure as section 2a)
for our time-interleaved ADC (See figures 3a2 and 3a3 for the
measured INL and DNL respectively). Here as before, we can see
there are some missing steps or missing codes due to the 1%
mismatch factor, or equivalently we can see the INL and DNL
measurements lower than -0.5 LSB and equal to -1 LSB
respectively at 3 digital codes. It is worth nothing however that
while we have some missing codes as before, we are operating at
effectively twice the input frequency for our ramp.
3b. SNDR and ENOB vs. Input Frequency
Next we are asked to calculate the SNDR and ENOB vs frequency
from 100MHz to 6.1GHz keeping the input amplitude at full scale
550mV (See figure 3b1 for the transient response and DFT of the
output at a 550mV input amplitude, see figures 3b2 and 3b3 for the
SNDR and ENOB vs. input frequency). Then, from the slope of
the first two frequency points, the point at which the ENOB is 0.5
bits less than that the peak is: BW eff =231.856 MHz . This result
can be misleading however, for instance it does not take into
account that the starting ENOB (or equivalently SNDR) at
100MHz for the time-interleaved ADC is 7.477 bits as compared
to 5.829 bits for the single ADC. A better measure to assess the
 Figure 2: Single ADC simple test-bench

Figure 2a1: Input ramp and DAC output steps waveform (no mismatch)
0.5000
0.4000
0.3000
0.2000
0.1000
LSB

0.0000
-0.1000 0 50 100 150 200 250 INL
-0.2000
-0.3000
-0.4000
-0.5000
Digital Code

Figure 2a2: Measured INL for single ADC (no mismatch)

 0.500
0.400
0.300
0.200
LSB 0.100
0.000
-0.100 0 50 100 150 200 250 DNL
-0.200
-0.300
-0.400
-0.500
Digital Code

Figure 2a3: Measured DNL for single ADC (no mismatch)

Figure 2b1: Input ramp and DAC output steps waveform (1% mismatch)
1
0.8
0.6
0.4
0.2
LSB

0
-0.2 0 50 100 150 200 250 INL
-0.4
-0.6
-0.8
-1
Digital Code

Figure 2b2: Measured INL for single ADC (1% mismatch)

 0.2

0
0 50 100 150 200 250
-0.2

LSB -0.4

-0.6 DNL

-0.8

-1

-1.2
Digital Code

Figure 2b3: Measured DNL for single ADC (1% Mismatch)

Figure 2c1: Transient response and DFT at the output at 100MHz and a 550mV input amplitude (for reference)
40
35
30
25
SNDR (dB)

20
15 SNDR (dB)
10
5
0
0 100 200 300 400 500 600
Amplitude (mV)

Figure 2c2: SNDR vs. input amplitude

 7

ENOB (bits)
4

3
ENOB (bits)
2

0
0 100 200 300 400 500 600
Amplitude (mV)

Figure 2c3: ENOB vs. input amplitude

40
35
30
25
SNDR (dB)

20
15 SNDR (dB)
10
5
0
0 1000 2000 3000 4000 5000 6000 7000
Frequency (MHz)

Figure 2d1: SNDR vs. input frequency

7

5
ENOB (bits)

3
ENOB (bits)
2

0
0 1000 2000 3000 4000 5000 6000 7000
Frequency (Hz)

Figure 2d2: ENOB vs. input frequency

 Figure 3: 2x time-interleaved ADC test-bench

Figure 3a1: DAC output steps waveform (note the time-scale is half as compared to before, mismatch 1%)
0.6

0.4

0.2

0
0 50 100 150 200 250
LSB

-0.2
INL
-0.4

-0.6

-0.8

-1
Digital Code

Figure 3a2: Measured INL for time-interleaved ADC (1% mismatch)

 0.2

0
0 50 100 150 200 250
-0.2

LSB -0.4

-0.6 DNL

-0.8

-1

-1.2
Digital Code

Figure 3a3: Measured DNL for time-interleaved ADC (1% mismatch)

Figure 3b1: Transient response and DFT at the output at 100MHz and a 550mV input amplitude (for reference)
50
45
40
35
30
SNDR (dB)

25
20 SNDR (dB)
15
10
5
0
0 1000 2000 3000 4000 5000 6000 7000
Frequency (MHz)

Figure 3b2: SNDR vs. input frequency

 8
7
6
5
ENOB (bits)
4
3 ENOB (bits)
2
1
0
0 1000 2000 3000 4000 5000 6000 7000
Frequency (MHz)

Figure 3b3: ENOB vs. input frequency