Voltage Transfer Characteristic Matching by Different Nanosheet

Layer Numbers of Vertically Stacked Junctionless CMOS Inverter

for SoP/3D-ICs applications
P.-J. Sung1, 2, C.-Y. Chang2, L.-Y. Chen3, K.-H. Kao3, C.-J. Su1, T.-H. Liao4, C.-C. Fang4, C.-J. Wang1, T.-C. Hong2, C.-Y.
Jao4, H.-S. Hsu4, S.-X. Luo3, Y.-S. Wang3, H.-F. Huang3, J.-H. Li3, Y.-C. Huang2, F.-K.Hsueh1,2, C.-T.Wu1, Y.-M.Huang1,F.-J.
Hou1, G.-L. Luo1,Y.-C. Huang1,Y.-L. Shen1,W. C.-Y. Ma4, K.-P. Huang5, K.-L.Lin1, S. Samukawa6, Y. Li7, G.-W Huang1, Y.-
J. Lee1,*, J. -Y. Li1, 8, W.-F. Wu1, J.-M.Shieh1, T.-S. Chao2, W. -K. Yeh1, Y.-H. Wang3,9
1
National Nano Device Laboratories, Hsinchu, Taiwan; 2Dept. of Electrophysics, National Chiao Tung University, Hsinchu,
Taiwan; 3Dept. of Electrical Engineering, National Cheng Kung University, Tainan, Taiwan; 4Dept. of Electrical Engineering,
National Sun Yat-sen University, Kaohsiung, Taiwan; 5Mechanical and Systems Research Laboratories, Industrial Technology
Research Institute, Hsinchu, Taiwan; 6Institute of Fluid Science, Tohoku University, Sendai, Japan; 7Dept. of Electrical and
Computer Engineering, National Chiao Tung University, Hsinchu, Taiwan; 8Dept. of Electrical Engineering and Graduate
Institute of Electronics Engineering, National Taiwan University, Taipei, Taiwan; 9National Applied Research Laboratories,
Taipei, Taiwan; Tel: +886,-3-5726100-7793, Fax: +886-3-5722715, *Email: yjlee@narlabs.org.tw

Abstract penalty, a CMOS inverter of gain ~18 V/V is achieved by

For the first time, CMOS inverters with different stacking different NS layer numbers for nFETs and pFETs.
numbers of vertically stacked junctionless (JL) nanosheets
(NSs) are demonstrated. All fabrication steps were below 600 Device Fabrication
°C, and 8-nm thick poly-Si NSs with smooth surface Figs. 1 and 2 illustrate the process flow and schematic of
roughness were formed by a dry etching process. Compared vertically stacked NSs poly-Si CMOS fabrication. (a) First, a
to single channel devices, stacked n/p-channel FETs exhibit 45-nm amorphous-Si layer was deposited on SiO2 followed
higher on-current with low leakage current. Furthermore, a by ion implantation and thin-down steps. After the film
common-gate process was performed for the fabrication of thinned down to 8 nm by dry etching steps with 30 nm
CMOS inverters. By adjusting the NS layer numbers for
PECVD oxide for interlayers isolation, top layer was prepared
n/pFETs, respectively, the voltage transfer characteristics
by repeating Fig. 2(a). Since surface roughness and grain
(VTCs) of the CMOS inverter can be matched much better to
sizes are very critical for the electrical performance of poly-Si
reduce the noise margin due to on-current matching without
area penalty. This work experimentally demonstrates a new FETs, the etching-back step was carried out to form NSs
configuration of CMOS inverters on stacked NSs, which is below 600 °C. After the hard mask deposition, vertically
promising for System-on-Panel (SoP) and 3D-ICs stacked NSs were defined by lithography and dry etching
applications. processes. After the interlayer oxide removed by dilute HF,
gate stacks were defined with high k/metal gate, as shown in
Introduction Fig. 2(e), followed by oxide passivation and metallization
For the applications of SoP and 3D-ICs, high- (Fig. 2(f) and 2(g)). While the gate always controls the two
performance transistors are fabricated on a glass substrate or stacked channels at the same time, the S/D contacts are
buried oxide at low temperatures [1-2]. Although a fin defined such that the stacked devices can be operated together
structure can offer better gate controllability, fin pitch and or only the top one is contributing the drain current (bottom
width restrict the FinFET scaling. To further improve the channel floating, see Fig. 2(h) and 2(i)). Fig. 2 (j) shows the
device performance, Gate-all-around (GAA) nanowire or NS cross-sectional SEM image for a contact hole. Contact area of
FETs are promising candidates to outperform FinFETs to the top layer would influence the performance of stacked NSs
continue the device scaling for the N5 logic technology or FETs, and isotropic wet etching process was used after the
beyond [3-5]. A vertically stacked NS structure can enhance dry etching step to increase the contact area.
the device performance by increasing the effective device Fig. 3 shows the cross-sectional TEM image the stacked
width compared GAA and FinFETs in a given footprint [4]. NSs. The sheet thickness is 8 nm and 30 /40 nm for
Moreover, compared to enhance-mode FETs, JL FETs are top/bottom sheets width. Narrow top sheet width is due to dry
attractive due to the possess simplicity and immunity of etching process.
mobility degradation of carriers scattering at the
channel/oxide interface [6]. Results and Discussion
In this work, we demonstrated a novel design for CMOS Dopant Diffusion and Surface Roughness:
inverters with the stacked NS devices with different channel After solid-phase crystallization (SPC) and activation at
numbers to achieve a better noise margin. The NS devices 600 °C, the SIMS profiles show no significant diffusion of
were fabricated at low temperature ( 600 °C). Without area phosphorus (31P) and boron (Fig. 4) for one or two annealing

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978-1-7281-1987-8/18/$31.00 ©2018 IEEE 21.4.1 IEDM18-504
 cycles (one cycle : 24-hr SPC and 4-hr dopant activation). In is too long and the gap between two sheets is too narrow.
Fig. 5, the AFM images of (a) 45-nm and (b) 10-nm poly-Si Therefore, it is needed to further investigate the impact of the
films by SPC process, and (c) 10-nm poly-Si by dry etching distance between NSs on the device performance. Self-
thin-down process from 45-nm poly-Si are illustrated. RMS consistent numerical simulations solving Poission and current
roughness reveals that the thinned-down poly-Si in Fig. 5(c) equations have been carried out to investigate the electrical
is smoother and better for device fabrication. Fig. 5(d) shows characteristics of devices with different S/D contact
the XRD of different poly-Si films. Both XRD and the configurations (Fig. 17). The employed models include Fermi
diffraction pattern (inset in Fig. 3) confirm the statistic, doping-dependent mobility and bandgap narrowing,
recrystallization of the poly-Si film. SRH and nonlocal BTBT [7].
Fig. 18 shows more pronounced enhancement of on-
Comparison between Top and Stacked Channels: currents for the device (A) when increasing the distance
Figs. 6 and 7 show the transfer curves of JL poly-Si NS between two channels. It is attributed to the weakened the
n/pFETs, respectively, with two channels (2-ch) and one electrostatic coupling of the stacked channels as shown in Fig.
channel (1-ch). Higher on-current is achieved for the stacked 19. Simulations hint that stacked devices should not leave
NS JL FETs without a trade-off in leakage current and DIBL.  
 
 
 

  

In addition, the inset in Fig. 6 is the champion device performance by electrostatic coupling. And coupling is
exhibiting a subthreshold swing of 68 mV/dec and an Ion/Ioff stronger when channels are closer.
ratio of 107. Output characteristics in Figs. 8 and 9 present
70% and 50% current enhancement for nFET and pFETs, Conclusion
respectively, due to the stacked NSs of two layers. Figs. 10 For the first time, a CMOS inverter is demonstrated on
and 11 display the relation between Ion and Ioff for n/pFETs vertically stacked JL nanosheets with different sheet numbers
respectively, with a single top channel and stacked NSs with for n/p FETs. Even though the recrystallized poly Si layer is
2 channels. The latter shows an average Ion improvement thinned down to 8 nm, the grain size and surface roughness of
about 50% without Ioff degradation. In addition, high-energy poly-Si can still be retained. Compared to the device with a
31
P implantation could increase Ion significantly (up to about single channel, the stacked n/pFETs show higher on-current
160% as compared to low-energy 31P implantation) due to without leakage current degradation. This is due to a larger
higher conductivity in the channel (Fig. 10). effective width of the vertically stacked nanosheets. While
Fig. 12 presents the VTCs of a stacked JL poly-Si NSs single metal gate electrode for a CMOS inverter could
CMOS inverter at various drain-to-source voltages from 0.8 simplify the process, the asymmetry of |VTH| between
to 1.2 V. Higher 31P implanted energy for nFETs improves n/pFETs can degrade the VTC. In addition, from simulation
the noise margin of the inverter with an increased gain from results, stacked devices should not leave floating channel due
5.5 to 11 V/V, as shown in the inset. to the coupling effect. By adjusting the nanosheet layer
numbers for n/pFETs, the ideal VTCs of CMOS inverter can
Different NS layer numbers in n/pFETs for CMOS Inverter: be achieved to much reduce the noise margin without area
To simplify the process flow, single gate electrode for a penalty, which is beneficial for SoP/3D ICs applications.
CMOS inverter is needed, but the asymmetric behavior of
|VTH| between the n/pFET would degrade the voltage transfer ACKNOWLEDGMENT
characteristics (VTCs) under operation. To overcome this This work was performed by the National Nano Device Laboratories
facilities and supported by the Ministry of Science and Technology
issue, the effect of different NS layer numbers for the n/pFET
under grant numbers 107-2636-E-006-004, 105-2628-E-492-002-
on the inverter performance are investigated. Fig. 13(a) shows MY3, 105-2221-E-492-029-MY2, 106-2221-E-492-034, 107-2628-
the top-view SEM image of the vertically stacked poly-Si E-492-001-MY3 and-107-2633-E-009-003. The authors are grateful
CMOS and the zoom-in images (b) a one-channel pFET and for the support by National Center for High-performance Computing
(c) a two-channel stacked nFET. Fig. 14 shows the transfer (NCHC), Taiwan and Hitachi High-Technologies Corp. Japan.
and output curves of the one-channel pFET and two-channel
REFERENCES
nFET in a CMOS inverter. Fig. 15 presents the VTCs of the
[1] C.-C. Yang et al., IEDM Tech. Dig., 2014, pp.410-413. [2] K.
inverter, at VD from 0.6 to 1.2 V. with a maximum gain up to Ota et al., Proc. Symp. VLSI Tech., 2015, pp. 214-215. [3] H.
18 V/V (inset). In Table 1, the performance of the stacked Mertens et al., IEDM Tech. Dig., 2017, pp.828-831. [4] N. Loubet et
devices in this work is benchmarked with the prior works. al., Proc. Symp. VLSI Tech., 2017, pp. 230-231. [5] S. Barraud1 et
The CMOS inverter
 is improved due to on-current al., IEDM Tech. Dig., 2016, pp.464-467.[6] J.-P. Colinge et al.,
matching without area penalty. Nature Nanotechnology, 2010, pp.225-229. [7] Sentaurus TCAD,
Synopsys, 2017. [8] L.-C. Chen et al., IEEE Electron Device Lett.,
2017, pp. 1256-1258.[9] C. C.-C. Chung et al., IEEE Trans. Electron
Numerical Simulation for Stacked Structure Device, 2018, pp.756-762. [10] P.-Y. Kuo et al., Proc. Symp. VLSI
Fig. 16 shows the SEM images of non-optimized NS Tech., 2018, pp. 21-22. [11] M.-S. Yeh et al., IEDM Tech. Dig.,
structure. The top-sheet may collapse after the interlayer 2014, pp.618-621.
oxide removal when the separation between two contact pads

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IEDM18-505 21.4.2
 (a) (b) (c)
1. Bottom-layer a-Si deposition (45 nm)
2. Solid phase crystallization at 600
C
3. CMOS lithography & Implantation
dry etching
4. Bottom-channel JL-pFETs : stacked define (d)
-2

BF2, 5×14 cm , 30 KeV. Nano-Sheets Active region
5. Bottom-channel JL-nFETs:

31P, 5×14 cm-2, 16 KeV/20 KeV. Vin
(g) Vout
(f) (e)
6. Dopant activation (600
C /4 hrs)
7. Poly-Si thinning down to 8 nm by dry
etching.
8. TEOS deposition for isolation metallization contact holes
9. Top-layer a-Si deposition (45 nm)
10. Repeating steps 2 to 7 for top-layer (j)
11. Define active region by lithography (h)
Metal
(i)
Metal
12. HF dip to release nanosheets Top ch.
Gate
OX
TiN

13. Gate stacks formation: High K metal Top ch. 1st L

Al2O3 deposition by ALD. Bottom ch.
Al2O3

TiN deposition Bottom ch.
14. Gate patterning Fig. 2. Schematic flow. (a) 45 nm a-Si was deposited on SiO2 30 nm

15. Passivation followed by implantation and thin-down steps. (b) After film Poly-Si 8 nm
16. Contact holes formation thinned down to 8 nm by dry etching process, top- and bottom-
40 nm
17. Metallization for CMOS channels were prepared repeatedly. (c) & (d) Vertically stacked
NSs were released by interlayer oxide removal. (e) Gate stack
Fig. 1. Process flow of vertically
formation with high k/metal gate deposition. (f) & (g) Oxide Fig. 3. TEM image of vertically
stacked poly-Si JL NSs CMOS
passivation and metallization. (h) & (i) illustrate the S/D contacts stacked nanosheets. The sheet
fabrication. All process temperature
are deliberately connected to the top channel only (bottom thickness is 8 nm and 30 /40 nm
are below 600
C
channel floating) and two channels, respectively. (j) SEM cross- for top/bottom sheets width. The
section image for a contact hole. inset is the diffraction pattern.
21 -5
10 (SPC+anneal) x1 (SPC+anneal) x2 (a) 10 W =40 nm Open
V =1V
polySi ~45 nm(dep.) 1-ch 2-ch
P Concentration (atoms/cm3)

-6 M D
polySi ~10 nm(dep.) (d) 10
20 polySi ~10 nm(etch.) -7 LG=80 nm Solid
V =0.1V
10 10 D
Open
20 KeV


RMS=1.2 nm Si (111) Drain Current (A) 10

-8
Solid
16 KeV
Intensity(a.u.)

-5
-9 10
10
19
(b) 10 W =40 nm
Boron Concentration (atoms/cm )

21
3

-6
10 10 M
-10 10
-7

10 L =80 nm

Drain Current(A)
20 -8
10 10 G

 -11 10
-9

10
18
10
19 10 10
-10

Si (220)  -12 10
-11

10
18
RMS=1.6 nm Si (222) 10 10
-12
2-ch V =0.1V
(SPC+anneal)x1 -13 -13 D
17 10 10
10 (c)
-14
10
17 10 2-ch V =1V D
-14 -15

16
(SPC+anneal)x2 10 10
-1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5
10 -15 Gate Voltage(V)
16
0 10 20 30
Depth (nm)
40
10
10 -0.5 0.0 0.5 1.0 1.5 2.0 2.5
0 10 20 30 40 50 60 RMS=0.9 nm 20 30 40 50 60 Gate Voltage (V)
Depth (nm) 2 Theta (degree) Fig. 6. Transfer curves of nFETs. Higher on
Fig.4. After SPC and activation anneal at Fig. 5. AFM images of (a) 45 nm and (b) 10 nm currents could be achieved with stacked (2
600 °C, SIMS profiles show no significant poly-Si after SPC process, (c) poly-Si thinned channels) NSs. WM denotes bottom-channel
diffusion of 31P and boron (inset) between down by dry etching process from 45 to 10 nm. width. The inset is the champion device,
one and two thermal cycles. (d) XRD of poly-Si 45 nm, 10 nm, and etched which shows 68 mV/dec. S.S. and 7 orders
-5
poly-Si. of Ion/Ioff.
10 LG=80 nm 1-ch W =40 nm 0.5 1.6
10
-6 M
WM=40 nm, LG=80 nm WM=40 nm, LG=80 nm
2-ch W =40 nm
-7 M
10 VG-Vth=0~-1.2 V, step=-0.4 V
Drain Current (
A)

0.4 VG-Vth=0~1.2 V, step=0.4 V

Drain Current (
A)

1-ch W =20 nm M
1.2
Drain Current (A)

-8
10 1-ch JL-nFET
10
-9 1-ch JL-pFET
0.3 2-ch JL-nFET
-10
~1.7 X ~1.5 X 2-ch JL-pFET
10 W =40 nm
10
-6 M
0.8
Drain Current (A)

-11 L =80 nm -7

10
10 G

-12
10
-8
0.2
10
-9
10
-10
10

10
-13 2-ch V =-0.1V Solid
VD=0.1 V
-11
0.4
0.1
10 D

-14 2-ch V =-1V 10

-12

10 Open
VD= 1 V
10
-13

-2 -1
D
0 1
-15 Gate Voltage (V)
10 0.0 0.0
-2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 0.0 0.2 0.4 0.6 0.8 1.0 -1.0 -0.8 -0.6 -0.4 -0.2 0.0
Gate Voltage (V) Drain Voltage (V) Drain Voltage (V)
Fig. 7. Transfer curves of the stacked NSs Fig. 8. Comparisons of ID-VD curves of Fig. 9. Comparisons of ID-VD curves of
pFETs with one and two channels. S.S. and nFETs with one and two channels. 70 % stacked NS pFETs with one and two
on/off ratio are improved significantly as WM on-current improvement is achieved due to channels. 50 % on current improvement
shrinks down to 20 nm. The inset is the the stacked 2 channels. is achieved due to the stacked 2
champion device, which shows 117 mV/dec. channels.
with 5 orders of Ion/Ioff.

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21.4.3 IEDM18-506
 2
10 10
3 2.0
1-ch JL-nFET 31 15

Voltage Gain(V/V)
VD=1 V 1-ch JL-pFET VD=1 V Imp. P 16 KeV 12
Max gain~ 11 V/V
31
P 16 KeV
2-ch JL-nFET(16 KeV) 2-ch JL-pFET 31
Imp. P 20 KeV
WM=40 nm
31
1 9 P 20 KeV
10
2-ch JL-nFET(20 KeV) 10
2 WM=40 nm 1.6
2-ch JL-pFET 6

LG=100 nm LG=100 nm 3

0
2-ch JL-nFET
10 10
1 1.2 0
0.0 0.4 0.8 1.2 1.6 2.0
Ioff (nA)

Vin(V)

Vout(V)
Ioff (nA)
-1
10 10
0 0.8

LG=150 nm
10
-2 ave~2.6 X -1 0.4
10 WM=40 nm

-3 ave~1.5 X ave~1.5 X V =0.8~1.2 V, step=0.2 V

10 10
-2 0.0 D
0.0 0.5 1.0 1.5 2.0 0.0 0.5 1.0 1.5 2.0 0.0 0.4 0.8 1.2 1.6 2.0
Ion (
A) Ion (
A) Vin(V)
Fig. 10. Relation between Ion and Ioff for
Fig. 11. Relation between Ion and Ioff for Fig. 12. VOUT versus VIN of the stacked JL
nFETs with single top-channel and stacked
pFETs with single top-channel and poly-Si NS CMOS inverter, at VD from
NSs (2-ch), and the later shows the average Ion
stacked NSs, and the later shows the 0.8 to 1.2 V. Higher implanted energy for
improvement about 50 % without Ioff
average Ion improvement about 50% nFETs improves the CMOS inverter
degradation. Higher energy 31P implantation
without Ioff degradation. performance with increased gain, as
increases Ion significantly (up to 160 %) due
to higher dopant concentration in the channel. shown in the inset.
-4
10 JL-pFET 1.2 2.0
(a) (b) JL-nFET JL-pFET JL-nFET LG=150 nm 20
Max gain~ 18V/V
-5 WM=40 nm
10 WM=20 nm

Voltage Gain(V/V)
Open
1 V 1.0 WM=20 nm WM=40 nm
1.6 V =0.6~1.2 V
15

10
-6
Drain Current (
A) D
Solid
0.1 V
Drain Current (A)

-7 VG-Vth=0~1.2 V step=0.2 V
10
10 0.8

Vout(V)
-8 1.2 5
JL-pFET 10 step=0.4 V
-9 0.6 0
10 0.8
0.0 0.4 0.8 1.2 1.6 2.0
Vin(V)
JL-nFET 10
-10
0.4
(c) 10
-11 1-ch JL-pFET WM=20 nm
0.4
-12 (a) 0.2 (b) 2-ch JL-nFET WM=40 nm
10
-13
10 0.0 0.0
-2 -1 0 1 2 -1.2 -0.8 -0.4 0.0 0.4 0.8 1.2 0.0 0.4 0.8 1.2 1.6 2.0
Gate Voltage (V) Drain Voltage (V) Vin(V)
Fig. 13. (a) Top-view SEM image
of the vertically stacked poly-Si Fig. 14. (a) Transfer characteristics and (b) output Fig. 15 VOUT versus VIN of the stacked
CMOS. Zoom-in images of (b) a curves of the one-channel p-and two-channel nFETs in JL poly-Si NS CMOS inverter, at
one-channel pFET and (c) a a CMOS inverter. various VD from 0.8 V to 1.2 V with
stacked NSs nFET. max. gain up to 18 V/V in the inset.
(a) (b)

collapsed

Top ch.

(c)
bottom ch. Fig. 17. The simulated NS JLFETs with (a) top
TiN
channel (device A) and (b) stacked channels
(device A+B) for current flow. All channels
Fig. 16. The top-channel may have the same body thickness Tb (10 nm) and
collapse after the oxide removal for uniform doping concentration (1×1019 cm-3).
a long pads distance and a narrow The grid regions represent the contact terminals. Fig. 18. Simulated transfer characteristics
gap between NSs. The gate workfunction of 4 eV and EOT of 1 of devices (A) and (A+B) with different
nm are defined in all simulations. (W1 = 55 nm, distance D.
W2 = 60 nm, Lg = 15 nm.)
Table I. Performance comparison of stacked NS JLFFTs in this work with
other publications.
Ref. This Work [8] [9] [10] [11] [1]

Structure stacked NS stacked NS stacked JL a-IWO NS Trench JL Tri-gate

JL NW JL
Fin Height 8 nm 17 nm 12 nm 4 nm 2.4 nm 14 nm
CMOS Y N N N N Y
W/L(
m/
m) 0.03/0.08 0.084/1 0.04/0.35 80/40 0.07/0.5 0.02/0.03
(N-type) 68 168 150 150 99 96
Fig. 19. Simulated cross sectional electrostatic S.S.
(P-type) 117 N N N N 127
potential (V) contour of devices (A) and (A+B)
obtained at Vds 








(N-type) >107 >107 >105 >108 >107 >105
Ion/Ioff
with distance D = 3 nm and Lg = 15 nm. (P-type) >105 N N N N >105

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IEDM18-507 21.4.4