TTUChapter_4_Combinational_Logic
TTUChapter_4_Combinational_Logic
TTUChapter_4_Combinational_Logic
Combinational Logic
Mustafa Mustafa
Lecturer Kemal Uyguroğlu
Al-Dmour
Combinational Circuits
Combinational
n inputs • • m outputs
• Circuits •
• •
When input changes, output may change (after a delay)
Analysis
● Given a circuit, find out its function
A
B
C
A
F1
?
B
C
A
B
?
● Function may be expressed as:
A
F2
C
B
C
♦ Boolean function
♦ Truth table
Design
● Given a desired function, determine its circuit
● Function may be expressed as:
♦ Boolean function
?
♦ Truth table
A
F2
C
F2=AB+AC+BC
B
C
F1=AB'C'+A'BC'+A'B'C+ABC
F2=AB+AC+BC
Tafilah Technical University 3 / 65
Analysis Procedure
A =0 0 0
F2
C =0
B =0 0
C =0
A =0 0 0
F2
C =1
B =0 0
C =1
A =0 0 0
F2
C =0
B =1 0
C =0
A =0 0 1
F2
C =1
B =1 1
C =1
A =1 0 0
F2
C =0
B =0 0
C =0
A =1 1 1
F2
C =1
B =0 0
C =1
B =1 0
C =0
F1=AB'C'+A'BC'+A'B'C+ABC F2=AB+AC+BC
Tafilah Technical University 11 / 65
Design Procedure
Example:
Design a circuit to convert a “BCD” code to “Excess 3” code
➢ 4-bits ➢ 4-bits
➢ 0-9 values
? ➢ Value+3
BCD-to-Excess 3 Converter
C C
A B C D w x y z
1 1 1
0 0 0 0 0 0 1 1
1 1 1 1
0 0 0 1 0 1 0 0 B B
x x x x x x x x
0 0 1 0 0 1 0 1 A A
1 1 x x 1 x x
0 0 1 1 0 1 1 0
D D
0 1 0 0 0 1 1 1
0 1 0 1 1 0 0 0 w = A+BC+BD x = B’C+B’D+BC’D’
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0 C C
1 0 0 0 1 0 1 1 1 1 1 1
1 0 0 1 1 1 0 0 1 1 1 1
1 0 1 0 x x x x x x x x
B x x x x
B
A 1 x x
A 1 x x
1 0 1 1 x x x x
1 1 0 0 x x x x D D
1 1 0 1 x x x x
1 1 1 0 x x x x y = C’D’+CD z = D’
1 1 1 1 x x x x Tafilah Technical University 13 / 65
Design Procedure
BCD-to-Excess 3 Converter
A B C D w x y z A
0 0 0 0 0 0 1 1 w
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1 x
B
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1 C y
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
D z
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x w = A + B(C+D) y = (C+D)’ + CD
1 1 1 0 x x x x x = B’(C+D) + B(C+D)’ z = D’
1 1 1 1 x x x x Tafilah Technical University 14 / 65
Seven-Segment Decoder
a
w x y z abcdefg
w a
0 0 0 0 1111110 b
0 0 0 1 0110000 x c f b
? d g
0 0 1 0 1101101 y e
0 0 1 1 1111001 z f
g
0 1 0 0 0110011 e c
0 1 0 1 1011011 BCD code
0 1 1 0 1011111
0 1 1 1 1110000 y d
1 0 0 0 1111111 1 1 1
1 0 0 1 1111011 1 1 1
1 0 1 0 xxxxxxx x x x x
x
1 0 1 1 xxxxxxx w 1 1 x x
1 1 0 0 xxxxxxx z
1 1 0 1 xxxxxxx
1 1 1 0 xxxxxxx a = w + y + xz + x’z’ b=...
c=...
1 1 1 1 xxxxxxx
d=...
Tafilah Technical University 15 / 65
Binary Adder
Half Adder x S
y HA
C
● Adds 1-bit plus 1-bit
● Produces Sum and Carry x
+ y
───
x y C S C S
0 0 0 0
0 1 0 1 x S
1 0 0 1
1 1 1 0
y C
Full Adder x S
y FA
z C
● Adds 1-bit plus 1-bit plus 1-bit
● Produces Sum and Carry x
+ y
y + z
x y z C S ───
0 1 0 1
0 0 0 0 0 C S
0 0 1 0 1 x 1 0 1 0
z
0 1 0 0 1
S = xy'z'+x'yz'+x'y'z+xyz = x y z
0 1 1 1 0
y
1 0 0 0 1
0 0 1 0
1 0 1 1 0
x 0 1 1 1
1 1 0 1 0
z
1 1 1 1 1 C = xy + xz + yz
Tafilah Technical University 17 / 65
Binary Adder
Full Adder
x S
y HA HA
z C
x
S
y
C
x3 x2 x1 x0
y3 y2 y1 y0
0
FA FA FA FA
C4 C3 C2 C1
S3 S2 S1 S0
Tafilah Technical University 20 / 65
Binary Adder
x7 x6 x5 x4 x3 x2 x1 x0
y7 y6 y5 y4 y3 y2 y1 y0
A3 A2 A1 A0 B3 B2 B1 B0 A3 A2 A1 A0 B3 B2 B1 B0
Cy CPA C0 Cy CPA C0 0
S3 S2 S1 S0 S3 S2 S1 S0
S7 S6 S5 S4 S3 S2 S1 S0
Logic diagram
4-bit carry-look
ahead adder
● Propagation delay
of C3, C2 and C1 are
equal.
0+9 0 0 0 0 1 0 0 1 =9 0 1 0 0 1
1+0 0 0 0 1 0 0 0 0 =1 0 0 0 0 1
1+1 0 0 0 1 0 0 0 1 =2 0 0 0 1 0
1+8 0 0 0 1 1 0 0 0 =9 0 1 0 0 1
1+9 0 0 0 1 1 0 0 1 =A 0 1 0 1 0 Invalid Code
2+0 0 0 1 0 0 0 0 0 =2 0 0 0 1 0
9+0 1 0 0 1 0 0 0 0 =9 0 1 0 0 1 0 0 0 0 1 0 0 1 =9
9+1 1 0 0 1 0 0 0 1 = 10 0 1 0 1 0 0 0 0 1 0 0 0 0 = 16
9+2 1 0 0 1 0 0 1 0 = 11 0 1 0 1 1 0 0 0 1 0 0 0 1 = 17
9+3 1 0 0 1 0 0 1 1 = 12 0 1 1 0 0 0 0 0 1 0 0 1 0 = 18
9+4 1 0 0 1 0 1 0 0 = 13 0 1 1 0 1 0 0 0 1 0 0 1 1 = 19
9+5 1 0 0 1 0 1 0 1 = 14 0 1 1 1 0 0 0 0 1 0 1 0 0 = 20
9+6 1 0 0 1 0 1 1 0 = 15 0 1 1 1 1 0 0 0 1 0 1 0 1 = 21
9+7 1 0 0 1 0 1 1 1 = 16 1 0 0 0 0 0 0 0 1 0 1 1 0 = 22
9+8 1 0 0 1 1 0 0 0 = 17 1 0 0 0 1 0 0 0 1 0 1 1 1 = 23
9+9 1 0 0 1 1 0 0 1 = 18 1 0 0 1 0 0 0 0 1 1 0 0 0 = 24
+6
S3 S2 S1 S0 Err
S1
0 0 0 0 0
1 0 0 0 0 1 1 1 1
S2
1 0 0 1 0 S3 1 1
1 0 1 0 1 S0
1 0 1 1 1
1 1 0 0 1
Err = S3 S2 + S3 S1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 1
Tafilah Technical University 28 / 65
BCD Adder
x3 x2 x1 x0 y3 y2 y1 y0
A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 0
S3 S2 S1 S0
Err
0 0
A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 0
S3 S2 S1 S0
Cy S3 S2 S1 S0
Tafilah Technical University 29 / 65
Binary Subtractor
x3 x2 x1 x0 y3 y2 y1 y0
A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 1
S3 S2 S1 S0
F3 F2 F1 F0
A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci
S3 S2 S1 S0
F3 F2 F1 F0
FA FA FA FA
Carry C4 C3 C2 C1
S3 S2 S1 S0
2’s Complement Numbers
x3 x2 x1 x0
y3 y2 y1 y0
0
FA FA FA FA
Overflow C4 C3 C2 C1
S3 S2 S1 S0
x3 = A3 B3 + A3 B3 A3A2A1A0 B3B2B1B0
x2 = A2 B2 + A2 B2
Magnitude
x1 = A1 B1 + A1 B1 Comparator
x0 = A0 B0 + A0 B0
A<B A=B A>B
( A = B) = x3 x2 x1 x0
( A B) = A3 B3 + x3 A2 B2 + x3 x2 A1 B1 + x3 x2 x1 A0 B0
( A B) = A3 B3 + x3 A2 B2 + x3 x2 A1 B1 + x3 x2 x1 A0 B0
Tafilah Technical University 33 / 65
Magnitude Comparator
A3
x3
B3
A2
x2
B2
A1 (A<B)
x1
B1
A0
x0 (A>B)
B0
(A=B)
x7 x6 x5 x4 x3 x 2 x1 x0
y7 y6 y5 y4 y3 y2 y1 y0
A3 A2 A1 A0 B3 B2 B1 B0 A3 A2 A1 A0 B3 B2 B1 B0
0 I(A>B) I(A>B)
1
Magnitude Magnitude
I(A=B) I(A=B)
I(A<B)
Comparator I(A<B)
Comparator
0
A<B A=B A>B A<B A=B A>B
0 1 2 3
0 1
x1 0
Binary
x0 0 Decoder 0
0
y3 Y2
Decoder
I1 Binary
y2
y1 Y1
I0 y0
Y0
I1 I0 Y3 Y2 Y1 Y0
I1
0 0 0 0 0 1 I0
0 1 0 0 1 0
Y3 = I1 I 0 Y2 = I1 I 0
1 0 0 1 0 0
1 1 1 0 0 0 Y1 = I1 I 0 Y0 = I1 I 0
Tafilah Technical University 37 / 65
Decoders
Y6 = I 2 I1 I 0
Y7 Y5 = I 2 I1 I 0
Y6
Y5 Y4 = I 2 I1 I 0
Decoder
Binary
I2 Y4 Y3 = I 2 I1 I 0
I1 Y3
I0 Y2 Y2 = I 2 I1 I 0
Y1 Y1 = I 2 I1 I 0
Y0
Y0 = I 2 I1 I 0
I2
I1
I0
Tafilah Technical University 38 / 65
Decoders
“Enable” Control Y3
Y3
Decoder
I1 Y2
Binary Y2
I0 Y1
E Y1
Y0
Y0
E I1 I0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0
I1
1 0 0 0 0 0 1 I0
E
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
Tafilah Technical University 39 / 65
Decoders
Expansion I2 I1 I0
I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0 Y3 Y7
Decoder
I0
Binary
0 1 0 0 0 0 0 0 1 0 0 Y2 Y6
I1 Y1 Y5
0 1 1 0 0 0 0 1 0 0 0 E
1 0 0 0 0 0 1 0 0 0 0 Y0 Y4
1 0 1 0 0 1 0 0 0 0 0
1 1 0 0 1 0 0 0 0 0 0 Y3 Y3
Decoder
I0
Binary
1 1 1 1 0 0 0 0 0 0 0 Y2 Y2
I1 Y1 Y1
E Y0 Y0
Active-High / Active-Low
I1 I0 Y 3 Y 2 Y 1 Y 0 I1 I0 Y 3 Y 2 Y 1 Y 0
0 0 0 0 0 1 0 0 1 1 1 0
0 1 0 0 1 0 0 1 1 1 0 1
1 0 0 1 0 0 1 0 1 0 1 1
Y3
1 1 1 0 0 0 1 1 0 1 1 1
Y2
Y1
Y3 Y3
Decoder
Decoder
I1 I1
Binary
Binary
Y2 Y2 Y0
Y1 Y1
I0 Y0 I0 Y0 I1
I0
Y7 Y7
Y6 Y6
Y5 Y5
x I2 Y4 x I2 Y4
y I1 Y3 y I1 Y3
z I0 Y2 z I0 Y2
Y1 Y1
Y0 Y0
S C
S C
Tafilah Technical University 43 / 65
Encoders
x1
1 x3 x2 x1 y 1 y0
x2 y1 0 0 0 0 0
2 Binary
Encoder 0 0 1 0 1
y0 0 1 0 1 0
x3
3 1 0 0 1 1
Encoder
0 0 0 0 0 0 0 1 0 0 0 Y2
Binary
0 0 0 0 0 0 1 0 0 0 1 I4 Y1
0 0 0 0 0 1 0 0 0 1 0 I3 Y0
0 0 0 0 1 0 0 0 0 1 1 I2
0 0 0 1 0 0 0 0 1 0 0 I1
0 0 1 0 0 0 0 0 1 0 1 I0
0 1 0 0 0 0 0 0 1 1 0 I7
1 0 0 0 0 0 0 0 1 1 1 I6 Y2
I5
Y2 = I 7 + I 6 + I 5 + I 4 I4
I3 Y1
Y1 = I 7 + I 6 + I 3 + I 2 I2
I1
Y0 = I 7 + I 5 + I 3 + I1 I0 Y0
Tafilah Technical University 45 / 65
Priority Encoders
Encoder
V
Priority
I3 I2 I1 I0 Y1 Y0 V I2 Y1
0 0 0 0 0 0 0 I1 Y0
0 0 0 1 0 0 1 I0
0 0 1 x 0 1 1
0 1 x x 1 0 1
I3 Y0
1 x x x 1 1 1
I2
Y1 I1 I1
Y1 = I 3 + I 2 Y1
1 1 1 1
1 1 1 1
I2 Y0 = I 3 + I 2 I1
I3 I0 V
1 1 1 1
I0
V = I 3 + I 2 + I1 + I 0
Binary Binary
Encoder Decoder
7 I7 Y7
7
6 I6 Y6
6
5 I5 Y2
Y5
5
4 I4 Y1
I2 Y4
4
3 I3 Y0
I1 Y3
3
2 I2
I0 Y2
2
1 I1 Y1
1
0 I0 Y0
0
S1 S0 Y I0
0 0 I0 I1
MUX Y
0 1 I1 I2
1 0 I2 I3
S1 S0
1 1 I3
Tafilah Technical University 48 / 65
Multiplexers
2-to-1 MUX
I0
I0 Y
MUX Y
I1 I1
S
S
I0
4-to-1 MUX I1
Y
I0 I2
I1 I3
MUX Y
I2
I3
S1 S0
S1 S0
Tafilah Technical University 49 / 65
Multiplexers
S
Tafilah Technical University 50 / 65
Multiplexers
Example
F(x, y) = ∑(0, 1, 3)
x y F I0
1
0 0 1 1 I1
MUX Y F
0 1 1 0 I2
1 0 0 1 I3
S1 S0
1 1 1
x y
Example
F(x, y, z) = ∑(1, 2, 6, 7)
0 I0
x y z F 1 I1
0 0 0 0 1 I2
0 0 1 1 0 I3
Y F
0 1 0 1 0 I4 MUX
0 1 1 0 0 I5
1 I6
1 0 0 0
1 I7
1 0 1 0 S2 S1 S0
1 1 0 1
1 1 1 1 x y z
Example
F(x, y, z) = ∑(1, 2, 6, 7)
x y z F
0 0 0 0 z I0
F=z z I1 F
0 0 1 1
MUX Y
0 1 0 1 0 I2
F=z 1 I3
0 1 1 0 S1 S0
1 0 0 0
F=0 x y
1 0 1 0
1 1 0 1
F=1
1 1 1 1
Tafilah Technical University 54 / 65
Implementation Using Multiplexers
Example
F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)
A B C D F
0 0 0 0 0
F=D
D I0
0 0 0 1 1
0 0 1 0 0
D I1
F=D
0 0 1 1 1 D I2
0 1 0 0 1
0 1 0 1 0
F=D 0 I3
0 MUX Y F
0 1 1 0 0
F=0 I4
0 1 1 1 0 D
1 0 0 0 0
I5
1 0 0 1 0 F=0 1 I6
1 0 1 0 0
1 0 1 1 1
F=D 1 I7
1 1 0 0 1 S2 S1 S0
F=1
1 1 0 1 1
1 1 1 0 1 F=1
1 1 1 1 1 A B C
Tafilah Technical University 55 / 65
Multiplexer Expansion
I0 I0
I1 I1
MUX Y
I2 I2
I3 I3
S1 S0 I0
MUX Y Y
I1
I0 S
I4
I5 I1
MUX Y
I6 I2
I7 I3
S1 S0
1 0 0
S2 S1 S0 Tafilah Technical University 56 / 65
DeMultiplexers
Y3
Y2
I DeMUX Y
1
S S Y0
1 0
Y3
Y2 S1 S0 Y3 Y2 Y1 Y0
I
Y1 0 0 0 0 0 I
Y0
0 1 0 0 I 0
1 0 0 I 0 0
S1 1 1 I 0 0 0
S0
Tafilah Technical University 57 / 65
Multiplexer / DeMultiplexer Pairs
MUX DeMUX
7 I7 Y7
7
6 I6 Y6
6
5 I5 Y5
5
4 I4 Y4
4
3 I3
Y I Y3
3
2 I2 Y2
2
1 I1 Y1
1
0 I0 Y0
0
S2 S1 S0 S2 S1 S0
Synchronize
x2 x1 x0 y2 y1 y0
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DeMultiplexers / Decoders
Y3 Y3
Decoder
I1
Binary
Y2 Y2
I DeMUX Y I0 Y1
1
E Y0
S S Y0
1 0
E I1 I0 Y3 Y2 Y1 Y0
S1 S0 Y3 Y2 Y1 Y0 0 x x 0 0 0 0
0 0 0 0 0 I 1 0 0 0 0 0 1
0 1 0 0 I 0 1 0 1 0 0 1 0
1 0 0 I 0 0 1 1 0 0 1 0 0
1 1 I 0 0 0 1 1 1 1 0 0 0
Tri-State Buffer
C A Y
A Y 0 x Hi-Z
1 0 0
1 1 1
C
A Y
Tri-State Inverter
C
A C D Y
0 0 Hi-Z
Y 0 1 B
C
1 0 A
B 1 1 ?
Not Allowed
D
A
C A if C = 1
Y=
B if C = 0
B
Tafilah Technical University 61 / 65
Three-State Gates
I3
I2
Y
I1
I0
Y3
Decoder
S1 I1
Binary
Y2
S0 I0 Y1
E E Y0
Tafilah Technical University 62 / 65