Digital Logic and Design

Chapter 4
Combinational Logic
Chapter 4 Combinational Logic
4-1 Combinational Circuits
4-2 Analysis Procedure
4-3 Design Procedure
4-4 Binary Adder-Subtractor
4-5 Decimal Adder
4-6 Binary Multiplier
4-7 Magnitude Comparator
4-8 Decoders
4-9 Encoders
4-10 Multiplexers
Logic Circuits
Combinational Circuits
Analysis Procedure
Obtaining Boolean Functions
Boolean Expression Approach

A
B
F1
C T2=ABC
A T1=A+B+C
B T3=AB'C'+A'BC'+A'B'C
C
A
B F’2=(A’+B’)(A’+C’)(B’+C’)

A
F2
C
F2=AB+AC+BC
B
C
F1=AB'C'+A'BC'+A'B'C+ABC
F2=AB+AC+BC
Analysis Procedure
Truth Table Approach

A B C F1 F2
A =0 0 0 0 0 0
0 0
B =0
F1
C =0
A =0 0
B =0 0
C =0
1
A =0 0
B =0

A =0 0 0
F2
C =0

B =0 0
C =0
Analysis Procedure
Truth Table Approach

A B C F1 F2
A =0 0 0 0 0 0
0 1
B =0 0 0 1 1 0
F1
C =1
A =0 1
B =0 1
C =1
1
A =0 0
B =0

A =0 0 0
F2
C =1

B =0 0
C =1
Analysis Procedure
Truth Table Approach

A B C F1 F2
A =0 0 0 0 0 0
0 1
B =1 0 0 1 1 0
F1
C =0
0 1 0 1 0
A =0 1
B =1 1
C =0
1
A =0 0
B =1

A =0 0 0
F2
C =0

B =1 0
C =0
Analysis Procedure
Truth Table Approach

A B C F1 F2
A =0 0 0 0 0 0
0 0
B =1 0 0 1 1 0
F1
C =1
A =0
0 1 0 1 0
1 0
B =1 0 1 1 0 1
C =1
0
A =0 0
B =1

A =0 0 1
F2
C =1

B =1 1
C =1
Analysis Procedure
Truth Table Approach

A B C F1 F2
A =1 0 0 0 0 0
0 1
B =0 0 0 1 1 0
F1
C =0
A =1
0 1 0 1 0
1 1
B =0 0 1 1 0 1
C =0 1 0 0 1 0
1
A =1 0
B =0

A =1 0 0
F2
C =0

B =0 0
C =0
Analysis Procedure
Truth Table Approach

A B C F1 F2
A =1 0 0 0 0 0
0 0
B =0 0 0 1 1 0
F1
C =1
A =1
0 1 0 1 0
1 0
B =0 0 1 1 0 1
C =1
0 1 0 0 1 0
A =1 0 0 1
B =0
1 0 1

A =1 1 1
F2
C =1

B =0 0
C =1
Analysis Procedure
Truth Table Approach

A B C F1 F2
A =1 0 0 0 0 0
0 0
B =1 0 0 1 1 0
F1
C =0
A =1
0 1 0 1 0
1 0
B =1 0 1 1 0 1
C =0
0 1 0 0 1 0
A =1 1
B =1
1 0 1 0 1
1 1 0 0 1
A =1 0 1
F2
C =0

B =1 0
C =0
Analysis Procedure
Truth Table Approach
A B C F1 F2
A =1 0 0 0 0 0
1 1
B =1 0 0 1 1 0
F1
C =1
A =1
0 1 0 1 0
1 0
B =1 0 1 1 0 1
C =1 1 0 0 1 0
0
A =1 1
B =1
1 0 1 0 1
1 1 0 0 1
A =1 1 1
C =1
F2 1 1 1 1 1
B =1 1
C =1
B B
0 1 0 1 0 0 1 0
A 1 0 1 0 A 0 1 1 1
C C
F1=AB'C'+A'BC'+A'B'C+ABC F2=AB+AC+BC
Obtaining Boolean Functions and Truth Table from a
Logic Diagram
Obtain output Boolean functions from a logic diagram:

Obtain the truth table directly from a logic diagram:

Problem 4-2
Design Procedure
Given a problem statement:
Determine the number of inputs and outputs
Derive the truth table
Simplify the Boolean expression for each output
Produce the required circuit
Example:
Design a circuit to convert a “BCD” code to “Excess 3”
code
➢ 4-bits ➢ 4-bits
➢ 0-9 values
? ➢ Value+3

• Find the decimal equivalent of the given binary number.

• Add +3 to each digit of decimal number.
• Convert the newly obtained decimal number back to binary number to get required excess-3 equivalent.
Design Procedure
BCD-to-Excess 3 Converter

A B C D w x y z C C
0 0 0 0 0 0 1 1 1 1 1
0 0 0 1 0 1 0 0 1 1 1 1
0 0 1 0 0 1 0 1 x x x x
B x x x x
B
0 0 1 1 0 1 1 0 A 1 1 x x
A 1 x x
0 1 0 0 0 1 1 1 D D
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1 w = A+BC+BD x = B’C+B’D+BC’D’
0 1 1 1 1 0 1 0
C C
1 0 0 0 1 0 1 1
1 1 1 1
1 0 0 1 1 1 0 0
1 1 1 1
1 0 1 0 x x x x B B
x x x x x x x x
1 0 1 1 x x x x A A
1 x x 1 x x
1 1 0 0 x x x x
D D
1 1 0 1 x x x x
1 1 1 0 x x x x y = C’D’+CD z = D’
1 1 1 1 x x x x
Design Procedure
BCD-to-Excess 3 Converter

A B C D w x y z A
0 0 0 0 0 0 1 1 w
0 0 0 1 0 1 0 0
0 0 1 0 0 1 0 1
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1 x
B
0 1 0 1 1 0 0 0
0 1 1 0 1 0 0 1
0 1 1 1 1 0 1 0
1 0 0 0 1 0 1 1 C y
1 0 0 1 1 1 0 0
1 0 1 0 x x x x
D z
1 0 1 1 x x x x
1 1 0 0 x x x x
1 1 0 1 x x x x w = A + B(C+D) y = (C+D)’ + CD
1 1 1 0 x x x x x = B’(C+D) + B(C+D)’ z = D’
1 1 1 1 x x x x
Problem 4-6 Majority Circuit
A majority circuit is a combinational circuit whose output is equal to 1 if the
input variables have more 1’s than 0’s. The output is 0 otherwise. Design a 3-
input majority circuit.
Binary Adder-Subtractor
Half Adder - Addition of Two Bits
Two inputs: x and y Adds 1-bit plus 1-bit x S
Produces Sum and Carry y HA
Two outputs: C

• Sum S = x’y + xy’ x y C S

0 0 0 0 x
• Carry C = xy
+ y
It can also be implemented with an 0 1 0 1 ───
1 0 0 1 C S
exclusive-OR and an AND gate
1 1 1 0

x S

y C
Full-Adder –Sum of Three Bits
Full Adder
x S
Adds 1-bit plus 1-bit plus 1-bit y
z
FA
C
Produces Sum and Carry
y x
0 1 0 1 + y
x y z C S + z
x 1 0 1 0
0 0 0 0 0 ───
z
0 0 1 0 1 C S
S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
0 1 0 0 1
0 1 1 1 0 y
1 0 0 0 1 0 0 1 0
1 0 1 1 0 x 0 1 1 1
1 1 0 1 0 z
1 1 1 1 1
C = xy + xz + yz
Full-Adder –Sum of Three Bits
S = xy'z'+x'yz'+x'y'z+xyz = x  y  z
x C = xy + xz + yz
y
z
x
y x
x z y
x S z S
y
z
x
x
x y
y y y
z x
x z C
y z
y
z x C
z
z
y
z
Full-Adder – Sum of Three Bits

x S
y HA HA

z C

x
S

y
C

z
Binary Adder
An n-bit adder requires n full x3x2x1x0 y3y2y1y0
adders with each output carry c3 c2 c1 .
+ x3 x2 x1 x0
connected to the input carry Carry + y3 y2 y1 y0
of the next higher-order full Cy Binary Adder C0 Propagate ────────
adder Addition Cy S3 S2 S1 S0
4-bit adder: Interconnection of S3S2S1S0
four full adder (FA) circuits
x3 x2 x1 x0
y3 y2 y1 y0
0

FA FA FA FA

C4 C3 C2 C1
S3 S2 S1 S0
Binary Adder
Carry Propagate Adder

x7 x6 x5 x4 x3 x2 x1 x0
y7 y6 y5 y4 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0 A3 A2 A1 A0 B3 B2 B1 B0

Cy CPA C0 Cy CPA C0 0

S3 S 2 S1 S0 S3 S2 S1 S0

S 7 S6 S5 S4 S3 S2 S1 S0
Binary Adder – Carry Propagation
Total propagation time = propagation delay of a typical gate * number of gate levels in the circuit

The longest propagation delay time in an adder is the time it takes the carry to propagate
through the full adders.
Inputs Ai and Bi are available as soon as input signals are applied to the adder.
The value of Si in any given stage will be in its steady state final value only after the input
carry to that stage has been propagated.
C3 has to wait for C2, C2 has to wait for C1 and so on down to C0.
A limiting factor on the speed with which two numbers are added.
The signal from the input carry Ci to the output carry Ci+1 propagates through an AND gate and an
OR gate, which constitute two gate levels.
For an n-bit adder, there are 2n gate levels for the carry to propagate from input to output.
4-bit adder
Carry propagation: 2 * 4 = 8 gate levels from C0 to C4.
Binary Adder – Reducing Carry Propagation Delay
Binary Subtractor
Use 2’s complement with
binary adder x3 x2 x1 x0 y3 y2 y1 y0
x – y = x + (-y) = x + y’ + 1

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 1
S3 S2 S1 S0

F3 F2 F1 F0
Binary Adder/Subtractor
M: Control Signal (Mode)
M=0 ➔ F = x + y
M=1 ➔ F = x – y

x3 x2 x1 x0 y3 y2 y1 y0 M

V: to detect an overflow
A3 A2 A1 A0 B3 B2 B1 B0 for signed numbers
Cy Binary Adder Ci
S3 S2 S1 S0

F3 F2 F1 F0 Binary numbers in the signed-complement system are added and subtracted

by the same basic addition and subtraction rules as unsigned numbers
Binary Adder/Subtractor – Overflow
When two numbers of n digits each are added and the sum occupies n+1 digits, an overflow
occurs
Addition of two unsigned numbers: detected from the end carry of the most significant
position
Addition of two signed numbers: May occur if the two numbers are both positive or both
negative
Overflow for unsigned numbers
C bit detects a carry after addition or a borrow after subtraction
Overflow for signed numbers
V=0 after an addition or subtraction: indicate no overflow
V=1: the result of the operation contains n+1 bits
An overflow has occurred
The (n+1)th bit is the actual sign and has been shifted out of position
Decimal Adder
• Binary adder: (1000)2 + (1001)2 = (1 0001)2
• BCD adder: (1000)BCD + (1001)BCD = (1 0111)BCD
• Decimal adder: 8 + 9 = 17
BCD/Decimal Adder
4-bits plus 4-bits
Operands and Result: 0 to 9 x3 x2 x1 x0 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0
X +Y x3 x2 x1 x0 y3 y2 y1 y0 Sum Cy S3 S2 S1 S0
Cy Binary Adder Ci 0
0+0 0 0 0 0 0 0 0 0 =0 0 0 0 0 0 + x3 x2 x1 x0
S3 S2 S1 S0
0+1 0 0 0 0 0 0 0 1 =1 0 0 0 0 1 + y3 y2 y1 y0
0+2 0 0 0 0 0 0 1 0 =2 0 0 0 1 0 ────────
Cy S3 S2 S1 S0
0+9 0 0 0 0 1 0 0 1 =9 0 1 0 0 1
1+0 0 0 0 1 0 0 0 0 =1 0 0 0 0 1
1+1 0 0 0 1 0 0 0 1 =2 0 0 0 1 0 0 0

1+8 0 0 0 1 1 0 0 0 =9 0 1 0 0 1 A3 A2 A1 A0 B3 B2 B1 B0
1+9 0 0 0 1 1 0 0 1 =A 0 1 0 1 0 Cy Binary Adder Ci 0
2+0 0 0 1 0 0 0 0 0 =2 0 0 0 1 0 Invalid Code
S3 S2 S1 S0

9+9 1 0 0 1 1 0 0 1 = 12 1 0 0 1 0 Cy S3 S2 S1 S0
Wrong BCD Value
0001 1000
BCD/Decimal Adder
When the binary sum is
equal to or less than 1001,
the corresponding BCD X +Y x3 x2 x1 x0 y3 y2 y1 y0 Sum Cy S3 S2 S1 S0 Required BCD Output Value
number is identical
Therefore, no conversion 9+0 1 0 0 1 0 0 0 0 =9 0 1 0 0 1 0 0 0 0 1 0 0 1 =9
is needed. 9+1 1 0 0 1 0 0 0 1 = 10 0 1 0 1 0 0 0 0 1 0 0 0 0 = 16 
When the binary sum is 9+2 1 0 0 1 0 0 1 0 = 11 0 1 0 1 1 0 0 0 1 0 0 0 1 = 17 
9+3 1 0 0 1 0 0 1 1 = 12 0 1 1 0 0 0 0 0 1 0 0 1 0 = 18 
greater than 1001, 9+4 1 0 0 1 0 1 0 0 = 13 0 1 1 0 1 0 0 0 1 0 0 1 1 = 19 
we obtain an invalid BCD 9+5 1 0 0 1 0 1 0 1 = 14 0 1 1 1 0 0 0 0 1 0 1 0 0 = 20 
representation. 9+6 1 0 0 1 0 1 1 0 = 15 0 1 1 1 1 0 0 0 1 0 1 0 1 = 21 
9+7 1 0 0 1 0 1 1 1 = 16 1 0 0 0 0 0 0 0 1 0 1 1 0 = 22 
The addition of binary 6 9+8 1 0 0 1 1 0 0 0 = 17 1 0 0 0 1 0 0 0 1 0 1 1 1 = 23 
(0110) to the binary sum 9+9 1 0 0 1 1 0 0 1 = 18 1 0 0 1 0 0 0 0 1 1 0 0 0 = 24 
converts it to the correct
BCD representation and
also produces an output
carry as required. +6
BCD/Decimal Adder
x3 x2 x1 x0 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 0
S3 S2 S1 S0

Err

0 0

A3 A2 A1 A0 B3 B2 B1 B0
Cy Binary Adder Ci 0
S3 S2 S1 S0

Cy S3 S2 S1 S0
Binary Multiplier
Multiplication of binary numbers is performed in the same way as in decimal numbers
partial product: the multiplicand is multiplied by each bit of the multiplier starting from the
least significant bit
Four-bit by three-bit binary multiplier
The multiplicand be represented by B3B2B1B0
The multiplier by A2A1A0.
Since K = 4 and J = 3, we need 12 AND gates and
two 4-bit adders to produce a product of seven
bits.
Arithmetic Circuits
f(x)=x2
f(x)=sqrt(x);
round, trunc, floor, are the examples of arithmetic
circuits.

* Homework
Explore the internet and do it by yourself.
Magnitude Comparator
A combinational circuit that compares two
numbers, A and B, and determines their
relative magnitudes: A>B, A=B, or A<B
4-bit comparator:
A=A3A2A1A0,
B=B3B2B1B0

Where xi = 1 only if the pair of bits in position i

are equal (i.e., if both are 1 or both are 0).
Magnitude Comparator

x7 x6 x5 x4 x3 x2 x1 x0
y7 y6 y5 y4 y3 y2 y1 y0

A3 A2 A1 A0 B3 B2 B1 B0 A3 A2 A1 A0 B3 B2 B1 B0
0 I(A>B) I(A>B)
1
Magnitude Magnitude
I(A=B) I(A=B)
I(A<B)
Comparator I(A<B)
Comparator
0
A<B A=B A>B A<B A=B A>B

A<B A=B A>B

Decoders
A combinational circuit that converts binary information from n input lines to a maximum of
2n unique outp
n-to-m-line decoders: generate m (=2n or fewer) minterms of n input variables
Only one lamp
Extract “Information” from the code will turn on
Binary Decoder
Example: 2-bit Binary Number

0 1
x1 0
Binary
x0 0 Decoder 0
0
Decoders
2-to-4 Line Decoder Y3

Y2
y3

Decoder
I1

Binary
y2 Y1
y1
I0 y0 Y0

I 1 I0 Y3 Y2 Y1 Y0 I1
I0
0 0 0 0 0 1
0 1 0 0 1 0 Y3 = I1 I 0 Y2 = I1 I 0
1 0 0 1 0 0
Y1 = I1 I 0 Y0 = I1 I 0
1 1 1 0 0 0
 Y7 = I 2 I1 I 0
Decoders Y7 Y6 = I 2 I1 I 0
Y6
3-to-8 Line Decoder Y5 = I 2 I1 I 0
Y5

Decoder
Binary
I2 Y4 Y4 = I 2 I1 I 0
I1 Y3
I0 Y2 Y3 = I 2 I1 I 0
Y1 Y2 = I 2 I1 I 0
Y0
Y1 = I 2 I1 I 0

Y0 = I 2 I1 I 0

I2
I1
I0
Decoders – with enable input using NAND
•More economical to generate the decoder minterms in their complemented form using NAND gates.
•Support one or more enable inputs to control the circuit operation.
• e.g. disabled when E is equal to 1 (no outputs).
• same as a Demultiplexer: a circuit that receives information from a single line and directs it to one of 2n possible
output lines.
• Selection of a specific output is controlled by bit combination of n selection lines. Y3

Y2
E I 1 I0 Y3 Y2 Y1 Y0
0 x x 0 0 0 0 Y3 Y1

Decoder
I1

Binary
Y2
1 0 0 0 0 0 1 I0 Y1 Y0
1 0 1 0 0 1 0 E Y0
1 1 0 0 1 0 0
1 1 1 1 0 0 0 I1
I0
E
Connecting multiple decoders to form a larger one
• A decoder provides the 2n minterm of n input variable
• Any combinational circuit with n inputs and m outputs can be implemented with an n-to-2n-line
decoder and m OR gates I2 I1 I0

I2 I1 I0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 0 0 0 0 0 0 0 0 0 1 Y3 Y7

Decoder
I0

Binary
0 0 1 0 0 0 0 0 0 1 0 Y2 Y6
0 1 0 0 0 0 0 0 1 0 0 I1 Y1 Y5
0 1 1 0 0 0 0 1 0 0 0 E Y0 Y4
1 0 0 0 0 0 1 0 0 0 0
1 0 1 0 0 1 0 0 0 0 0 Y3 Y3

Decoder
1 1 0 0 1 0 0 0 0 0 0 I0

Binary
Y2 Y2
1 1 1 1 0 0 0 0 0 0 0 I1 Y1 Y1
E Y0 Y0
Combinational Logic Implementation – Full Adder
with a Decoder Binary
Decoder
1. Each output is a minterm
Y7
2. All minterms are produced Y6
3. Sum the required minterms Y5
x I2 Y4
y I1 Y3
Example: Full Adder z I0 Y2
S(x, y, z) = ∑(1, 2, 4, 7) Y1
C(x, y, z) = ∑(3, 5, 6, 7) Y0

S C
Combinational Logic Implementation – Full Adder
with a Decoder Binary
Binary Decoder
Decoder
Y7
Y7 Y6
Y6 Y5
Y5 x I2 Y4
x I2 Y4 y I1 Y3
y I1 Y3 z I0 Y2
z I0 Y2 Y1
Y1 Y0
Y0

S C
S C
Seven-Segment Decoder
w x y z abcdefg a
0 0 0 0 1111110
w a
0 0 0 1 0110000 b
x c f b
0 0 1 0 1101101
d g
0 0 1 1 1111001 y ? e
0 1 0 0 0110011 z f
g e c
0 1 0 1 1011011
0 1 1 0 1011111 BCD code
0 1 1 1 1110000
1 0 0 0 1111111
d
1 0 0 1 1111011 y
1 0 1 0 xxxxxxx 1 1 1
1 0 1 1 xxxxxxx 1 1 1
x x x x
x
1 1 0 0 xxxxxxx w
1 1 0 1 xxxxxxx 1 1 x x
1 1 1 0 xxxxxxx z b=...
1 1 1 1 xxxxxxx c=...
a = w + y + xz + x’z’ d=...
Combinational Logic Implementation – Example
Problem 4-25
Construct a 5-to-32-line decoder with four 3-to-8-line decoders with enable and a 2-to-4-line
decoder. Use block diagrams for the components
Encoders
An encoder has 2n (or fewer) input lines and n output lines, which generate the binary code
corresponding to the input value.
Put “Information” into code
Binary Encoder
Example: 4-to-2 Binary Encoder Only one switch
should be activated
at a time
x1

x3 x2 x1 y1 y0
x2 y1
Binary 0 0 0 0 0
Encoder
y0 0 0 1 0 1
x3
0 1 0 1 0
1 0 0 1 1
Encoders
Octal-to-binary encoder: 8 inputs (one for each of the octal digits) and three outputs
generating the corresponding binary number.
•multiple inputs: undefined => priority encoder
•Input with all 0’s = I0 is equal to 1
• The encoder can be implemented with three OR gates.
Y2 = I 7 + I 6 + I 5 + I 4
I7 I6 I5 I4 I3 I2 I1 I0 Y2 Y1 Y0
0 0 0 0 0 0 0 1 0 0 0 I7 Y1 = I 7 + I 6 + I 3 + I 2
0 0 0 0 0 0 1 0 0 0 1 I6 Y0 = I 7 + I 5 + I 3 + I1
0 0 0 0 0 1 0 0 0 1 0 I5

Encoder
Y2

Binary
I7
0 0 0 0 1 0 0 0 0 1 1 I4 Y1 I6 Y2
I5
0 0 0 1 0 0 0 0 1 0 0 I3 Y0 I4
0 0 1 0 0 0 0 0 1 0 1 I2 I3 Y1
I2
0 1 0 0 0 0 0 0 1 1 0 I1 I1
1 0 0 0 0 0 0 0 1 1 1 I0 I0 Y0
Priority Encoder
A priority encoder is an encoder circuit that includes the priority function. The operation of
the priority encoder is such that if two or more inputs are equal to 1 at the same time, the
input having the highest priority will take precedence.
Input D3 has the highest priority, so, regardless of the values
of the other inputs, when this input is 1, the output for xy is
11 (binary 3).
D2 has the next priority level. The output is 10 if D2 = 1,
provided that D3 = 0, regardless of the values of the other
two lower priority inputs.
The output for D1 is generated only if higher priority inputs
are 0, and so on down the priority levels.
Encoder / Decoder Pairs
Binary Binary
Encoder Decoder

I7 Y7
I6 Y6
I5 Y5
Y2 I2 Y4
I4 Y1 I1 Y3
I3 Y0 I0 Y2
I2
I1 Y1
I0 Y0
Multiplexers
A combinational circuit that selects binary information from one of many input lines and
directs it to a single output line
Normally, there are 2n input lines and n selection lines whose bit combinations determine
which input is selected
also called a data selector
2-to-1-line multiplexer: two data input lines, one output line, and one selection line S

S1 S0 Y
I0
0 0 I0 I1
MUX Y
0 1 I1 I2
1 0 I2 I3
S1 S0
1 1 I3
Multiplexers
S=0: the upper AND is enabled and Y = I0
2-to-1 MUX Y=S’I0+SI1 S=1: the lower AND is enabled and Y = I1
I0
I0
MUX Y Y
I1
S I1

4-to-1 MUX
I0

I1
I0 I2
Y
I1
MUX Y I3
I2
I3
S1 S0

S1 S0
Multiplexers
Quad 2-to-1 MUX

x3 A3
I0 Y3
y3 MUX Y
I1 A2
S Y2
A1
Y1
x2 I0 A0
y2 MUX Y Y0
I1
S B3

B2
x1 I0 A3
y1 MUX Y B1 A2
I1
S A1
Y3
B0 A0
Y
MUX 2
x0 I0
MUX Y B3
Y1
y0 I1 B2
Y0
S S E
B1
B0
S S E
Implementation Using Multiplexers
Boolean Function Implementation

Example
F(x, y) = ∑(0, 1, 3)

x y F I0
1
0 0 1 1 I1
MUX Y F
0 1 1 0 I2
1 0 0 1 I3
S1 S0
1 1 1
x y
Implementation Using Multiplexers
Boolean Function Implementation

Example
F(x, y, z) = ∑(1, 2, 6, 7)

0 I0
x y z F 1 I1
0 0 0 0 1 I2
0 0 1 1 0 I3
Y F
0 1 0 1 0 I4 MUX
0 1 1 0 0 I5
1 I6
1 0 0 0
1 I7
1 0 1 0 S2 S1 S0
1 1 0 1
1 1 1 1 x y z
Implementation Using Multiplexers
Boolean Function Implementation

Example
F(x, y, z) = ∑(1, 2, 6, 7)

x y z F
0 0 0 0 z I0
F=z z I1 F
0 0 1 1
MUX Y
0 1 0 1 0 I2
F=z 1 I3
0 1 1 0 S1 S0
1 0 0 0
F=0 x y
1 0 1 0
1 1 0 1
F=1
1 1 1 1
Implementation Using Multiplexers
Boolean Function Implementation

Example
F(A, B, C, D) = ∑(1, 3, 4, 11, 12, 13, 14, 15)

A B C D F
0 0 0 0 0
F=D
D I0
0 0 0 1 1
0 0 1 0 0
D I1
F=D
0 0 1 1 1 D I2
0 1 0 0 1
0 1 0 1 0
F=D 0 I3
0 MUX Y F
0 1 1 0 0
F=0 I4
0 1 1 1 0 D
1 0 0 0 0
I5
1 0 0 1 0 F=0 1 I6
1 0 1 0 0
1 0 1 1 1
F=D 1 I7
1 1 0 0 1 S2 S1 S0
F=1
1 1 0 1 1
1 1 1 0 1 F=1
1 1 1 1 1 A B C
Multiplexer Expansion
8-to-1 MUX using Dual 4-to-1 MUX

I0 I0
I1 I1
MUX Y
I2 I2
I3 I3
S1 S0 I0
MUX Y Y
I1
I0 S
I4
I5 I1
MUX Y
I6 I2
I7 I3
S1 S0

1 0 0
S2 S1 S0
DeMultiplexers
A demultiplexer (or demux) is a device that
takes a single input line and routes it to one of
several digital output lines. A demultiplexer of
2n outputs has n select lines, which are used
to select which output line to send the input. A
demultiplexer is also called a data distributor.

Y3
S1 S0 Y3 Y2 Y1 Y0
Y2 Y3 0 0 0 0 0 I
I
Y1
Y2 0 1 0 0 I 0
I DeMUX Y
1
Y0 1 0 0 I 0 0
S S Y0
1 0 1 1 I 0 0 0
S1
S0
Multiplexer / DeMultiplexer Pairs
MUX DeMUX

I7 Y7
I6 Y6
I5 Y5
I4 Y4
Y I Y3
I3
I2 Y2
I1 Y1
I0 Y0

S2 S1 S0 S2 S1 S0

Synchronize
x2 x1 x0 y 2 y1 y0
DeMultiplexers / Decoders
A Decoder decodes an
encrypted input signal to Y3 Y3

Decoder
I1

Binary
multiple output signals Y2 Y2
I DeMUX Y I0 Y1
from one format to another 1
E Y0
format. A De-Multiplexer S S Y0
1 0
routes an input signal to
multiple output signals.
E I1 I0 Y3 Y2 Y1 Y0
A Decoder has 'n' input
lines and maximum of S1 S0 Y3 Y2 Y1 Y0 0 x x 0 0 0 0
2n output lines. A De- 0 0 0 0 0 I 1 0 0 0 0 0 1
Multiplexer has single 0 1 0 0 I 0 1 0 1 0 0 1 0
input, 'n' selection lines 1 0 0 I 0 0 1 1 0 0 1 0 0
and maximum of 1 1 I 0 0 0 1 1 1 1 0 0 0
2n outputs.
Three-State Gates
A digital circuit that exhibits three states
Two of the states are signal equivalent to logic 1 and 0
The third state is a high-impedance state, which behaves like a disconnected open circuit
May perform as AND, NAND, buffer, etc. However, the one most commonly used is the
buffer gate.
A multiplexer can be constructed with three-state gates
Chapter
END