CH 01
CH 01
CH 01
and
Computer Architecture
Von-Neumann CPU architecture
Same physical memory address is used for instructions and data. Separate physical memory address is used for instructions and data.
There is common bus for data and instruction transfer. Separate buses are used for transferring data and instruction.
Two clock cycles are required to execute single instruction. An instruction is executed in a single cycle.
CPU can not access instructions and read/write at the same time. CPU can access instructions and read/write at the same time.
It is used in personal computers and small computers. It is used in micro controllers and signal processing.
CISC & RISC CPU architecture
CISC RISC
Complex Instruction Set Reduced Instruction Set
Computer. Computer.
9
Microprocessor Fifth Generation Pentium
Fourth Generation
During 1980s
Low power version of HMOS technology
(HCMOS)
Third Generation 32 bit processors
During 1978 Physical memory space 224 bytes = 16 Mb
HMOS technology Faster speed, Higher Virtual memory space 240 bytes = 1 Tb
packing density Floating point hardware
16 bit processors 40/ 48/ 64 pins Supports increased number of addressing
Easier to program modes
Dynamically relatable programs
Processor has multiply/ divide arithmetic Intel 80386
hardware
More powerful interrupt handling
capabilities Second Generation
Flexible I/O port addressing During 1973
NMOS technology Faster speed, Higher
Intel 8086 (16 bit processor) density, Compatible with TTL
4 / 8/ 16 bit processors 40 pins
First Generation Ability to address large memory spaces
Between 1971 – 1973 and I/O ports
PMOS technology, non compatible with TTL Greater number of levels of subroutine
4 bit processors 16 pins nesting
8 and 16 bit processors 40 pins Better interrupt handling capabilities
Due to limitations of pins, signals are 10
multiplexed Intel 8085 (8 bit processor)
8086 Microprocessor features:
1. It is 16-bit microprocessor
2. It has a 16-bit data bus, so it can read data from or write
data to memory and ports either 16-bit or 8-bit at
a time.
3. It has 20 bit address bus and can access up to 220 memory
locations (1 MB).
4. It can support up to 64K I/O ports
5. It provides 14, 16-bit registers
6. It has multiplexed address and data bus AD0-AD15 & A16-
A19
7. It requires single phase clock with 33% duty cycle to
provide internal timing.
8. Prefetches up to 6 instruction bytes from memory and
queues them in order to speed up the processing.
9. 8086 supports 2 modes of operation
a. Minimum mode
b. Maximum mode
Microprocessor Functional blocks
13
Pins and signals
8086 Microprocessor
Pins and Signals Common signals
AD0-AD15 (Bidirectional)
Address/Data bus
15
8086 Microprocessor
Pins and Signals Common signals
MN/ MX
MINIMUM / MAXIMUM
TEST
READY
RESET (Input)
CLK
19
8086 Microprocessor
Pins and Signals Minimum mode signals
Pins 24 -31
DT/𝐑
ഥ (Data Transmit/ Receive) Output signal from the
processor to control the direction of data flow
through the data transceivers
Pins 24 -31
21
8086 Microprocessor
Pins and Signals Maximum mode signals
22
8086 Microprocessor
Pins and Signals Maximum mode signals
23
8086 Microprocessor
Pins and Signals Maximum mode signals
24
Architecture
ARCHITECTURE
26
8086 Microprocessor
Architecture
Segment
Registers
29
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
30
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
31
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
32
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
33
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
34
8086 Microprocessor
Architecture Bus Interface Unit (BIU)
Instruction queue
A group of First-In-First-
Out (FIFO) in which up to
6 bytes of instruction
code are pre fetched
from the memory ahead
of time.
35
8086 Microprocessor
Architecture Execution Unit (EU)
EU decodes and
executes instructions.
A decoder in the EU
control system
translates instructions.
and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 36
DX can be used as DH and DL
8086 Microprocessor
Architecture Execution Unit (EU)
37
8086 Microprocessor
Architecture Execution Unit (EU)
38
8086 Microprocessor
Architecture Execution Unit (EU)
Example:
39
8086 Microprocessor
Architecture Execution Unit (EU)
40
8086 Microprocessor
Architecture Execution Unit (EU)
41
8086 Microprocessor
Architecture Execution Unit (EU)
42
8086 Microprocessor
Architecture Execution Unit (EU)
43
8086 Microprocessor
Architecture Execution Unit (EU)
Auxiliary Carry Flag
Carry Flag
Flag Register This is set, if there is a carry from the
This flag is set, when there is
lowest nibble, i.e, bit three during
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.
This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF
Tarp Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction
8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
into 4 groups OF DF IF TF SF ZF AF PF CF
Program
A set of instructions written to solve
a problem.
Instruction
Directions which a microprocessor
follows to execute a task or part of a
task.
Computer language
1. Register Addressing
Group I : Addressing modes for
2. Immediate Addressing register and immediate data
3. Direct Addressing
5. Based Addressing
Group II : Addressing modes for
6. Indexed Addressing memory data
7. Based Index Addressing
8. String Addressing
8. String Addressing
52
8086 Microprocessor Group I : Addressing modes for
Addressing Modes register and immediate data
1. Register Addressing
In immediate addressing mode, an 8-bit or 16-bit
2. Immediate Addressing data is specified as part of the instruction
3. Direct Addressing
Example:
4. Register Indirect Addressing
MOV DL, 08H
5. Based Addressing
The 8-bit data (08H) given in the instruction is
6. Indexed Addressing moved to DL
8. String Addressing
MOV AX, 0A9FH
9. Direct I/O port Addressing
The 16-bit data (0A9FH) given in the instruction is
10. Indirect I/O port Addressing
moved to AX register
11. Relative Addressing
(AX) 0A9FH
12. Implied Addressing
53
8086 Microprocessor
Addressing Modes : Memory Access
1. Register Addressing
2. Immediate Addressing
Here, the effective address of the memory
3. Direct Addressing
location at which the data operand is stored is
4. Register Indirect Addressing given in the instruction.
12. Implied Addressing This addressing mode is called direct because the
displacement of the operand from the segment
base is specified directly in the instruction.
57
8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data
(CL) (MA)
(CH) (MA +1)
58
8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data
(AL) (MA)
59
(AH) (MA + 1)
8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data
(CL) (MA)
(CH) (MA + 1)
60
8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data
61
8086 Microprocessor Group II : Addressing modes
Addressing Modes for memory data
1. Register Addressing
2. Immediate Addressing
1. Register Addressing
2. Immediate Addressing
3. Direct Addressing
5. Based Addressing
6. Indexed Addressing
Instructions using this mode have no operands.
The instruction itself will specify the data to be
7. Based Index Addressing
operated by the instruction.
8. String Addressing
Example: CLC
9. Direct I/O port Addressing
This clears the carry flag to zero.
10. Indirect I/O port Addressing
65
INSTRUCTION SET
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
3. Logical Instructions
67
8086 Microprocessor
Instruction Set
Instructions that are used to transfer data/ address in to registers, memory locations and
I/O ports.
Generally involve two operands: Source operand and Destination operand of the same
size.
A 8-bit data can only be moved to 8-bit register/ memory and a 16-bit data can be moved
to 16-bit register/ memory.
68
8086 Microprocessor
Instruction Set
69
8086 Microprocessor
Instruction Set
71
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
ADD A, data
72
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
ADDC A, data
73
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
SUB A, data
74
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
SBB A, data
75
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
76
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
77
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
78
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
79
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
80
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
81
8086 Microprocessor
Instruction Set
2. Arithmetic Instructions
Mnemonics: ADD, ADC, SUB, SBB, INC, DEC, MUL, DIV, CMP…
CMP A, data
82
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
83
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
84
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
85
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
86
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
87
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
88
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
89
8086 Microprocessor
Instruction Set
3. Logical Instructions
Mnemonics: AND, OR, XOR, TEST, SHR, SHL, RCR, RCL …
90
8086 Microprocessor
Instruction Set
91
8086 Microprocessor
Instruction Set
REP
92
8086 Microprocessor
Instruction Set
MOVS
(MAE) (MA)
93
8086 Microprocessor
Instruction Set
CMPS
94
8086 Microprocessor
Instruction Set
LODS
96
8086 Microprocessor
Instruction Set
STOS
97
8086 Microprocessor
Instruction Set
CLC Clear CF 0
NOP No operation
Mnemonics Explanation
CALL reg/ mem/ disp16 Call subroutine
99
8086 Microprocessor
Instruction Set
Checks flags
100
8086 Microprocessor
Instruction Set
Mnemonics Explanation
JC disp8 Jump if CF = 1
JP disp8 Jump if PF = 1
JO disp8 Jump if OF = 1
JS disp8 Jump if SF = 1
102
Assembler directives
8086 Microprocessor
Assemble Directives
Used to :
› specify the start and end of a program
› attach value to variables
› allocate storage locations to input/ output data
› define start and end of segments, procedures, macros etc..
104
8086 Microprocessor
Assemble Directives
DB Define Byte
PROC
Example:
FAR
NEAR LIST DB 7FH, 42H, 35H
ENDP
Three consecutive memory locations are reserved for
SHORT the variable LIST and each data specified in the
instruction are stored as initial value in the reserved
MACRO memory location
ENDM 105
8086 Microprocessor
Assemble Directives
DB Define Word
PROC
Example:
FAR
NEAR ALIST DW 6512H, 0F251H, 0CDE2H
ENDP
Six consecutive memory locations are reserved for
SHORT the variable ALIST and each 16-bit data specified in
the instruction is stored in two consecutive memory
MACRO location.
ENDM 106
8086 Microprocessor
Assemble Directives
ORG
END Segnam SEGMENT
EVEN
…
EQU … Program code
… or
PROC … Data Defining Statements
…
FAR …
NEAR
ENDP Segnam ENDS
SHORT
ORG
User defined name of
END Segment Register
the segment
EVEN
EQU
PROC Example:
FAR
NEAR ASSUME CS: ACODE, DS:ADATA Tells the compiler that the
ENDP instructions of the program are
stored in the segment ACODE and
data are stored in the segment
SHORT ADATA
MACRO
ENDM 108
8086 Microprocessor
Assemble Directives
ORG
Examples:
END
EVEN ORG 1000H Informs the assembler that the statements
EQU following ORG 1000H should be stored in
memory starting with effective address
1000H
PROC
FAR
LOOP EQU 10FEH Value of variable LOOP is 10FEH
NEAR
ENDP
_SDATA SEGMENT In this data segment, effective address of
SHORT ORG 1200H memory location assigned to A will be 1200H
A DB 4CH and that of B will be 1202H and 1203H.
EVEN
MACRO B DW 1052H
ENDM _SDATA ENDS 109
8086 Microprocessor
Assemble Directives
General form
ASSUME
ORG
procname PROC[NEAR/ FAR]
END
EVEN …
… Program statements of the
EQU procedure
…
DB
Examples:
DW
RET
ORG ADD64 ENDP
END
EVEN
EQU CONVERT PROC FAR The subroutine/ procedure named CONVERT
is declared as FAR and so the assembler will
… code the CALL and RET instructions involved
PROC … in this procedure as far call and return
ENDP …
FAR
RET
NEAR CONVERT ENDP
SHORT
MACRO
ENDM 111
8086 Microprocessor
Assemble Directives
PROC
ENDP
FAR
NEAR
SHORT
MACRO
ENDM 112
8086 Microprocessor
Assemble Directives
PROC
ENDP
FAR User defined name of
NEAR the macro
SHORT
MACRO
ENDM 113
114
Interfacing memory and i/o ports
8086 Microprocessor
Memory
Processor Memory
▪ Registers inside a microcomputer
▪ Store data and results temporarily
▪ No speed disparity
▪ Cost
Secondary Memory
▪ Storage media comprising of slow
devices such as magnetic tapes and
disks
▪ Hold large data files and programs:
Operating system, compilers,
databases, permanent programs etc. 116
8086 Microprocessor
Memory organization in 8086
8086 : 16-bit
Bank 0 : A0 = 0 Even
addressed memory bank
117
8086 Microprocessor
Memory organization in 8086
119
8086 Microprocessor
Interfacing SRAM and EPROM
120
8086 Microprocessor
Interfacing SRAM and EPROM
121
8086 Microprocessor
Interfacing SRAM and EPROM
122
8086 Microprocessor
Interfacing SRAM and EPROM
Monitor Programs
Programing 8279 for keyboard scanning and display
refreshing
Initialization of stack
123
8086 Microprocessor
Interfacing I/O and peripheral devices
I/O devices
For communication between microprocessor and
outside world
Interrupt driven I/ O
I/O device interrupts the
processor and initiate data
transfer
Direct memory access
Data transfer is achieved by 124
bypassing the microprocessor
8086 Microprocessor
8086 and 8088 comparison
The I/O ports or peripherals can be Only IN and OUT instructions can be
treated like memory locations and used for data transfer between I/O
so all instructions related to device and processor
memory can be used for data
transmission between I/O device
and processor
Data can be moved from any Data transfer takes place only
register to ports and vice versa between accumulator and ports
When memory mapping is used for Full memory space can be used for
I/O devices, full memory address addressing memory.
space cannot be used for
addressing memory. Suitable for systems which
require large memory capacity
Useful only for small systems
where memory requirement is less
For accessing the memory mapped For accessing the I/O mapped
devices, the processor executes devices, the processor executes I/O
memory read or write cycle. read or write cycle.
8086 8088
16-bit Data bus lines obtained by 8-bit Data bus lines obtained by
demultiplexing AD0 – AD15 demultiplexing AD0 – AD7
In MIN mode, pin 28 is assigned the In MIN mode, pin 28 is assigned the
signal M / 𝐈𝐎 signal IO / 𝐌
ഥ
To access higher byte, 𝐁𝐇𝐄 signal is No such signal required, since the
used data width is only 1-byte
127
8087 Coprocessor
8086 Microprocessor
Co-processor – Intel 8087
129
8086 Microprocessor
Co-processor – Intel 8087
130
8086 Microprocessor
Co-processor – Intel 8087
131
8086 Microprocessor
Co-processor – Intel 8087
BUSY
132
8086 Microprocessor
Co-processor – Intel 8087
𝐑𝐐 / 𝐆𝐓𝟎
𝐑𝐐 / 𝐆𝐓𝟏
133
8086 Microprocessor
Co-processor – Intel 8087
INT
134
8086 Microprocessor
Co-processor – Intel 8087
𝐒ഥ𝟎- 𝐒ത𝟐
𝐒ഥ𝟐 𝐒ഥ𝟏 𝐒ഥ𝟎 Status
1 0 0 Unused
1 0 1 Read memory
1 1 0 Write memory
1 1 1 Passive
QS0 – QS1
135
8086 Microprocessor
Co-processor – Intel 8087
Wake up the
coprocessor
Monitor
ESC 8086/
8088
Deactivate the
Execute the host’s TEST pin
8086 and execute the
instructions specific
operation
Activate
WAIT the TEST
pin
Wake up the
8086/ 8088
137