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    Postlab-2 Eee201

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    Postlab-2 Eee201

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    9 views14 pages

    Postlab-2 Eee201

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    Postlab and Prelab

    Exp-02

    Student Name : Mahfuz-Al-Galib


    Student’s ID : 2023-3-80-031
    Experiment Name: LT Spice simulation of AC Circuits
    Course Title : Electrical Circuits II
    Course Code : EEE201
    Section : 2
    Date of performance:10-07-2024
    Date of Submission :20-08-2024
    Group-02
    SL Group : 02
    Partner’s Name ID
    1 Amio Rahman 2023-3-80-031
    2 Rakibul Hasan 2023-3-80-053

    Submitted To:
    Dr. M. Ryyan Khan, Associate Professor,
    Department of EEE, EWU
    ……………………………….PreLab………………………………………
    ……………………………….Post Lab…………………………………….
    Objective : The objective is to simulate simple AC circuits in LTspice
    to analyze and verify the theoretical calculations of voltages and currents
    across resistive, capacitive, and inductive components at 100Hz
    frequency.

    Circuit drawing
    Figure:-1

    Figure-2: Voltage signal .


    Figure-3: Current signal and Voltage signal.

    Figure-4: Current Signal.

    Figure-5: voltage signal across the resistance .


    Figure-6: voltage signal across the inductance.

    Figure-7: voltage signal across the capacitance.

    Figure-8: RMS value of input voltage signal.


    Figure-9: RMS values of the voltage across the Capacitance.

    Figure-10: RMS values of the voltage across the Resistance.

    Figure-11: RMS values of the voltage across the inductance.


    Figure-12: RMS value of current

    Simulated Values

    Table-01:
    Signal 1 Signal 2 Measure Δt Δθ=360*Δt*f Lead/Lag ?
    V1 I 775.57µs 27.92° V lead
    V(R) I 0 0° No one lead or lag
    V(C) I 2.348ms 84.52° I lead
    V(L) I 2.547us 0.091692° V(L)lead

    Table-02:
    Signal RMS value
    V1 7.07V
    V(R) 6.22V
    V(C) 1.21V
    V(L) 4.22V

    Table-03:
    I max 1.01A
    Questions Answer
    Q-1:
    Total voltage V = 10 ∠0 R= 9 Ω
    L =10mH C = 1mF
    ω=2*π*100 rad/s= 200 π rad/s.
    From theoretical part,
    Z(L)= jωL = j*200π*10*10^-3 =j6.28 Ω.
    Z(C) =-j/ωc= -j/200π*1*10^-3 = -j 1.59 Ω.
    Total impedance,
    Z = R+j(XL-XC) = 9+j (6.28-1.59)Ω =10.15∠27.54°Ω
    From experimental part,
    Total voltage V = 10 ∠0 volt ,
    We can see phase difference of I is 27.92°and I=0.92989A.
    Current (I) phasor form I=0.92989∠-27.92°A.
    Z’=10 ∠0/0.92989∠-27.92°=10.75∠27.92° Ω

    Theoretical part Experimental part Error

    10.15∠27.54°Ω 10.75∠27.92° Ω 5.69%


    Q-2:
    Now theoretically calculate the voltage value given below:
    V = 10 V V(R) = 8.8767 V
    V(L) = 6.19 V V(C) = 1.568 V
    ❖ For the total voltage RMS value
    Vrms=10/1.41=7.09 Vrms
    ❖ For the RMS value voltage across Inductor.
    V(L)rms=6.19/1.41=4.39 Vrms.
    ❖ For the RMS value voltage across Capacitor.
    V(C)rms=1.568/1.41=1.12 Vrms
    ❖ For the RMS value voltage across Resistor.
    V(R)rms=8.8767/1.41=6.29 Vrms
    ❖ For the RMS value of Current
    Irms=0.9865/1.41=0.697Arms
    Compare theoretical value and simulated value :
    Signal Simulated Calculated Error
    RMS value RMS value
    V 7.07V 7.09V 0.28%
    V(R) 6.22V 6.29V 1%
    V(C) 1.21V 1.12V 8%
    V(L) 4.22V 4.39V 4%
    I 0.691A 0.697A 0.08%
    Q-3:
    Calculate the complex power consumed in the circuit from
    S = (1⁄2)Vm Im cos(∆θ) +j(1⁄2)Vm Im sin(∆θ)
    Here given ,
    Vm=10volt,
    Im=0.92989A,
    Complex power ,
    S=.5*10*0.929cos(27.92°)+j*.5*10*0.929sin(27.92°)
    = 4.104+j2.17 VA
    = 4.6∠27.92° VA.

    Q-4:
    Now calculate the the power dissipated by the resistance from
    R=9Ω
    P = Im^2*R/2 = ((0.929*0.929)*9)/2 = 3.88 Watt.
    We can see Ques no -3:
    S= 4.104+j2.17 VA
    P*=4.104W

    The real part of S Power dissipated by Error


    is Power the resistance
    4.104 W 3.88 W 5.77%
    Q-5: Simulate the circuit shown in Fig. 3 of Exp.1

    • Phase difference between source voltage and voltage across the


    resistance
    Here, , Δt=163.5µs

    Δθ=360*163.5*10^-6*1000=58.86°.
    So, Voltage signal from the resistance is leading and Voltage signal
    from the source is lagging.

    …………………………………………………………………………….

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