EECS 151/251A Homework 6

Due Friday, October 21st , 2022 11:59PM

Problem 1: CMOS Gates

(a) What is the boolean expression for the function described by the CMOS gate below?

Solution:
We can look at the PDN to observe the boolean expression, converting parallel branches
to boolean ORs and series to boolean ANDs:

Out = A(B + C) + D (1)

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(b) Draw the static complementary CMOS circuit that implements the following logic function:

ABC + DE

Solution:
The output is 0 when ABC +DE is true, so the PDN can directly map to this expression.
Hence there are 2 parallel branches in the PDN, with A/B/C in series on one branch and
D/E in series on the other branch.
The PUN can be derived by applying the duality of complementary CMOS gates. Series
paths are converted to parallel, and parallel paths are converted to series. This results in
2 groups of transistors in series, with one group being A/B/C in parallel and the other
being D/E in parallel.

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Problem 2: Inverter Delay

We want to design a 5-stage inverter chain that can drive a load capacitance of CL = 250Cin with
the smallest delay possible, where Cin is the input capacitance of a minimum sized inverter. The
first inverter is constrained to be minimum size (W = 1 as in shown in the figure). Assume that
τinv = 10 ps and γ = 1.

(a) How should the inverter chain be sized for minimum delay?

Solution:
Delay is minimized when each stage has the same fanout. The total fanout is
CL 250Cin
F = = = 250
Cin Cin
The fanout per stage should then be
√ √
f= F = 250 ≈ 3.02
N 5

We can then size the inverters from the back:

CL 250Cin
Cd = = ≈ 82.9Cin ⇒ d ≈ 82.9
f 3.02
Cd 82.9Cin
Cc = = ≈ 27.5Cin ⇒ c ≈ 27.5
f 3.02
CL 27.5Cin
Cb = = ≈ 9.1Cin ⇒ b ≈ 9.1
f 3.02
CL 9.1Cin
Ca = = ≈ 3.02Cin ⇒ a ≈ 3.02
f 3.02

(b) What is the total delay through the inverter chain?

Solution:

tp,tot = τinv · N (γ + f ) = 10 · 5(1 + 3.02) ≈ 201ps

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(c) Assume that the number of stages is not restricted to 5. How many stages should you use for
minimum delay? What is the total delay?

Solution:
The total (normalized) delay through the inverter chain as a function of N (the number
of stages), F (the total fanout), and γ is

D = N (γ + F 1/N )

Using F = 250 and γ = 1, we can plot the delay curve:

The graph shows that the optimal number of stages is 4. Thus, the total delay is

tp,tot = τinv · N (γ + F 1/N ) = 10 · 4(1 + 2501/4 ) ≈ 199ps

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Problem 3: Logical Effort

In the lecture, we mentioned that inverters in today’s FinFET technology nodes have equal NMOS
and PMOS widths since the Ron,n = Ron,p . Here, we assume a different technology, where for a
minimum size transistor (W = 1),

• NMOS on resistance Ron,n = R

• PMOS on resistance Ron,p = 3R

• Gate capacitance Cg = C (same for both NMOS and PMOS)

Assume γ = 1.

(a) How should the minimum inverter be sized? Specify the NMOS width Wn and PMOS width
Wp .

Solution:
Wn = 1, Wp = 3.
We want equal pull-down/pull-up strengths. Wn = 1 would result in a pull-down resis-
tance of R, and Wp = 3 would result in a pull-up resistance of 3R/3 = R.

(b) What is Req and Cin of the minimum size inverter?

Solution:
Req = R, Cin = 4C.
As mentioned in the solution to part (a), the minimum size inverter is sized to have a
pull-up and pull-down resistance of R.
The total input capacitance is

Cg,n + Cg,p = Wn Cg + Wp Cg = C + 3C = 4C

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(c) We want to design the following custom CMOS gate:

How should the custom gate be sized to have the same output current as the minimum size
inverter?

Solution:

We want to size each transistor such that in the worst case, the pull-up/pull-down resis-
tance is equivalent to that of the minimum size inverter (i.e., R). For parallel branches,
the worst case considers only one branch being on at a time.
First, consider the pull-down network. The NMOS with input C should be sized 1 to
have a PD resistance of R. As for the NMOS with inputs A and B, both transistors
must be on, resulting in 2x the resistance. Thus, each should be sized 2 such that the
PD resistance in this case is R/2 + R/2 = R.
Next, consider the pull-up network. For the PUN to be turned on, all branches must
require a stack of 2 PMOS devices to be on (either A & C or B & C). Thus, each PMOS
must be sized 2x larger to account for the 2-stacked PMOS. In addition, PMOS must be
3x larger than the NMOS to account for the 3x larger on-resistance. Hence, setting the
PMOS devices to have size 6 results in the PU resistances as
Ron,p Ron,p 3R 3R
A, C : + = + =R
WA WC 6 6
Ron,p Ron,p 3R 3R
B, C : + = + =R
WB WC 6 6

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(d) Compute the logical effort LE and (normalized) parasitic delay P of the custom gate.
Note: The logical effort should be calculated separately for each input.

Solution:
The logical effort is computed as
Req,gate Cin,gate
LE =
Req,inv Cin,inv

Because we sized the custom gate to have the same resistance as the inverter,

Req,gate = Req,inv

and the LE equation simplifies to the ratio of capacitances, or

Cin,gate
LE =
Cin,inv

We can first compute the gate input capacitance for each input:

Cin,A = Cg (Wn,A + Wp,A ) = Cg (2 + 6) = 8C

Cin,B = Cg (Wn,B + Wp,B ) = Cg (2 + 6) = 8C
Cin,C = Cg (Wn,C + Wp,C ) = Cg (1 + 6) = 7C

The logical effort for each input is then

Cin,A 8C
LEA = = =2
Cin,inv 4C
Cin,B 8C
LEB = = =2
Cin,inv 4C
Cin,C 7C
LEC = = = 1.75
Cin,inv 4C

The (normalized) parasitic delay is computed as

Req,gate Cp,gate
P =
Req,inv Cp,inv

As in the case with logical effort,

Req,gate = Req,inv

and the parasitic delay equation simplifies to the ratio of capacitances, or

Cp,gate
P =
Cp,inv

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There are 4 transistors whose drains are directly connected to the output: the NMOS
with input B, NMOS with input C, PMOS with input A, and PMOS with input B. The
parasitic output cap of the gate is thus

γCg (Wn,B + Wn,C + Wp,A + Wp,B ) = 15γC

The parasitic output cap of the inverter is

γCg (Wn + Wp ) = 4γC

Thus, the parasitic delay is

15γC 15
P = = = 3.75
4γC 4

(e) (251A Only) Suppose that we have the following data path:

An inverter drives the custom gate’s input A, and the custom gate drives a load capacitance
CL = 16C. Both the inverter and custom gate are minimum size (as denoted by "1" in the
figure). Assume that the custom gate’s inputs B and C are driven by other circuits not shown
here.
What is the total delay from the input to the output? Express in terms of R and C.

Solution:
The total delay can be expressed in terms of parasitic delays, logical effort, and fanout:

tp,tot = tp,inv + tp,gate

= τinv (γ + finv ) + τinv (Pgate + LEgate,A fgate )

The fanout of the inverter is finv = 1 since the custom gate is sized to be 1 (i.e., its input
cap is the same as the minimum size inverter, or 4C).
The fanout of the custom gate is
CL 16C
fgate = = =4
4C 4C

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Thus, the total delay is

tp,tot = τinv [(γ + finv ) + (γ · Pgate + LEgate,A fgate )]

= τinv [(1 + 1) + (1 · 3.75 + 2 × 4)]
= 13.75τinv
= 13.75(4 ln 2RC) ≈ 38.1RC

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