CY28409

CY28409
Clock Synthesizer with Differential SRC and CPU Outputs
Features • Three differential CPU clock pairs

• One differential SRC clock
• Supports Intel Pentium 4-type CPUs • I2C support with readback capabilities
• Selectable CPU frequencies • Ideal Lexmark Spread Spectrum profile for maximum
• 3.3V power supply EMI reduction
• Ten copies of PCI clocks • 56-pin SSOP and TSSOP packages
• Five copies of 3V66 with one optional VCH
CPU SRC 3V66 PCI REF 48M
• Two copies 48-MHz USB clocks
x3 x1 x5 x 10 x2 x2
[1]
Block Diagram Pin Configuration
VDD_REF REF_0 1 56 FS_B

XIN XTAL REF0:1
XOUT OSC PLL Ref Freq
REF_1 2 55 VDD_A
VDD_CPU
VDD_REF 3 54 VSS_A
CPU_STP# Divider CPUT[0:2], CPUC[0:2] XIN 4 53 VSS_IREF
PLL1 XOUT 5 52 IREF
PCI_STP# Network
VDD_SRC
VSS_REF 6 51 FS_A
SRCT, SRCC
FS_[A:B] PCIF0 7 50 CPU_STP#
~
VTT_PWRGD# PCIF1 8 49 PCI_STP#

IREF PCIF2 9 48 VDD_CPU
VDD_PCI 10 47 CPUT2
VDD_3V66 VSS_PCI 11 46 CPUC2
3V66_[0:3]
PCI0 12 45 VSS_CPU
CY28409
VDD_PCI
PCI1 13 44 CPUT1
PLL2 PCIF[0:2] PCI2 14 43 CPUC1
2
PCI3 15 42 VDD_CPU
PCI[0:6]
VDD_PCI 16 41 CPUT0
VSS_PCI 17 40 CPUC0
PCI4 18 39 VSS_SRC
3V66_4/VCH PCI5 19 38 SRCT
PCI6 20 37 SRCC
PD# VDD_48MHz PD# 21 36 VDD_SRC
DOT_48 3V66_0 22 35 VTT_PWRGD#
USB_48 3V66_1 23 34 VDD_48
VDD_3V66 24 33 VSS_48
VSS_3V66 25 32 DOT_48
3V66_2 26 31 USB_48
SDATA I2C 3V66_3 27 30 SDATA
SCLK Logic SCLK 28 29 3V66_4/VCH
56 SSOP/TSSOP
Note:
1. Signals marked with [*] and [**] have internal pull-up and pull-down resistors, respectively.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07445 Rev. *B Revised August 26, 2003
CY28409
Pin Description
Pin No. Name Type Description
1, 2 REF(0:1) O, SE Reference Clock. 3.3V 14.318-Mz clock output.
4 XIN I Crystal Connection or External Reference Frequency Input. This pin has dual
functions. It can be used as an external 14.318-MHz crystal connection or as an external
reference frequency input.
5 XOUT O, SE Crystal Connection. Connection for an external 14.318-MHz crystal output.
41,44,47 CPUT(0:2) O, DIF CPU Clock Output. Differential CPU clock outputs. See Table 1 for frequency config-
uration
40,43,46 CPUC(0:2) O, DIF CPU Clock Output. Differential CPU clock outputs. See Table 1 for frequency config-
uration
38, 37 SRCT, SRCC O, DIF Differential serial reference clock.
22,23,26,27 3V66(0:3) O, SE 66-MHz Clock Output. 3.3V 66-MHz clock from internal VCO.
29 3V66_4VCH O, SE 48-/66-MHz Clock Output. 3.3V selectable through SMBus to be 66 or 48 MHz.
7,8,9 PCIF(0:2) O, SE Free-running PCI Output. 33-MHz clocks divided down from 3V66.
12,13,14, PCI(0:6) O, SE PCI Clock Output. 33-MHz clocks divided down from 3V66.
15,18,19,20
31, USB_48 O, SE Fixed 48-MHz clock output.
32 DOT_48 O, SE Fixed 48-MHz clock output.
51,56 FS_A, FS_B I 3.3V LVTTL input for CPU frequency selection.
52 IREF I Current Reference. A precision resistor is attached to this pin which is connected to
the internal current reference.
21 PD# I, PU 3.3V LVTTL input for PowerDown# active low.
50 CPU_STP# I, PU 3.3V LVTTL input for CPU_STP# active low.
49 PCI_STP# I, PU 3.3V LVTTL input for PCI_STP# active low.
35 VTT_PWRGD# I 3.3V LVTTL input is a level sensitive strobe used to latch the FS_A and FS_B
inputs (active low).
30 SDATA I/O SMBus-compatible SDATA.
28 SCLK I SMBus-compatible SCLOCK.
53 VSS_IREF GND Ground for current reference.
55 VDD_A PWR 3.3V power supply for PLL.
54 VSS_A GND Ground for PLL.
42,48 VDD_CPU PWR 3.3V power supply for outputs.
45 VSS_CPU GND Ground for outputs.
36 VDD_SRC PWR 3.3V power supply for outputs.
39 VSS_SRC GND Ground for outputs.
34 VDD_48 PWR 3.3V power supply for outputs.
33 VSS_48 GND Ground for outputs.
10,16 VDD_PCI PWR 3.3V power supply for outputs.
11,17 VSS_PCI GND Ground for outputs.
24 VDD_3V66 PWR 3.3V power supply for outputs.
25 VSS_3V66 GND Ground for outputs.
3 VDD_REF PWR 3.3V power supply for outputs.
6 VSS_REF GND Ground for outputs.
Document #: 38-07445 Rev. *B Page 2 of 18

CY28409
Frequency Select Pins (FS_A, FS_B) VTT_PWRGD# has been sampled low, all further
VTT_PWRGD#, FS_A and FS_B transitions will be ignored. In
Host clock frequency selection is achieved by applying the the case where FS_B is at mid level when VTT_PWRGD# is
appropriate logic levels to FS_A and FS_B inputs prior to sampled low, the clock chip will assume “Test Clock Mode”.
VTT_PWRGD# assertion (as seen by the clock synthesizer). Once “Test Clock Mode” has been invoked, all further FS_B
Upon VTT_PWRGD# being sampled low by the clock chip transitions will be ignored and FS_A will asynchronously
(indicating processor VTT voltage is stable), the clock chip select between the Hi-Z and REF/N mode. Exiting test mode
samples the FS_A and FS_B input values. For all logic levels is accomplished by cycling power with FS_B in a high or low
of FS_A and FS_B except MID, VTT_PWRGD# employs a state.
one-shot functionality in that once a valid low on
Table 1. Frequency Select Table (FS_A FS_B)
FS_A FS_B CPU SRC 3V66 PCIF/PCI REF0 REF1 USB/DOT
0 0 100 MHz 100/200 MHz 66 MHz 33 MHz 14.3 MHz 14.31 MHz 48 MHz
0 MID REF/N REF/N REF/N REF/N REF/N REF/N REF/N
1 MID Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
Table 2. Frequency Select Table (FS_A FS_B) SMBus Bit 5 of Byte 6 = 1

FS_A FS_B CPU SRC 3V66 PCIF/PCI REF0 REF1 USB/DOT
Serial Data Interface Data Protocol

To enhance the flexibility and function of the clock synthesizer, The clock driver serial protocol accepts byte write, byte read,
a two-signal serial interface is provided. Through the Serial block write, and block read operations from the controller. For
Data Interface, various device functions, such as individual block write/read operation, the bytes must be accessed in
clock output buffers, can be individually enabled or disabled. sequential order from lowest to highest byte (most significant
The registers associated with the Serial Data Interface bit first) with the ability to stop after any complete byte has
initializes to their default setting upon power-up, and therefore been transferred. For byte write and byte read operations, the
use of this interface is optional. Clock device register changes system controller can access individually indexed bytes. The
are normally made upon system initialization, if any are offset of the indexed byte is encoded in the command code,
required. The interface cannot be used during system as described in Table 3.
operation for power management functions. The block write and block read protocol is outlined in Table 4
while Table 5 outlines the corresponding byte write and byte
read protocol. The slave receiver address is 11010010 (D2h).
Table 3. Command Code Definition
Bit Description
7 0 = Block read or block write operation, 1 = Byte read or byte write operation
(6:0) Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be
'0000000'
Table 4. Block Read and Block Write Protocol

Block Write Protocol Block Read Protocol
Bit Description Bit Description
1 Start 1 Start
2:8 Slave address – 7 bits 2:8 Slave address – 7 bits
9 Write = 0 9 Write = 0
10 Acknowledge from slave 10 Acknowledge from slave
11:18 Command Code – 8 Bit 11:18 Command Code – 8 Bit
'00000000' stands for block operation '00000000' stands for block operation

CY28409
Table 4. Block Read and Block Write Protocol(continued)
Block Write Protocol Block Read Protocol
20:27 Byte Count – 8 bits 20 Repeat start
28 Acknowledge from slave 21:27 Slave address – 7 bits
29:36 Data byte 1 – 8 bits 28 Read = 1
38:45 Data byte 2 – 8 bits 30:37 Byte count from slave – 8 bits
46 Acknowledge from slave 38 Acknowledge from master
.... ...................... 39:46 Data byte from slave – 8 bits
.... Data Byte (N–1) –8 bits 47 Acknowledge from master
.... Acknowledge from slave 48:55 Data byte from slave – 8 bits
.... Data Byte N –8 bits 56 Acknowledge from master
.... Acknowledge from slave .... Data byte N from slave – 8 bits
.... Stop .... Acknowledge from master
.... Stop
Table 5. Byte Read and Byte Write protocol

Byte Write Protocol Byte Read Protocol
1 Start 1 Start
2:8 Slave address – 7 bits 2:8 Slave address – 7 bits
9 Write = 0 9 Write = 0
11:18 Command Code – 8 bits 11:18 Command Code – 8 bits
'100xxxxx' stands for byte operation, bits[4:0] of the '100xxxxx' stands for byte operation, bits[4:0] of
command code represents the offset of the byte to the command code represents the offset of the
be accessed byte to be accessed
20:27 Data byte from master – 8 bits 20 Repeat start
28 Acknowledge from slave 21:27 Slave address – 7 bits
29 Stop 28 Read = 1
29 Acknowledge from slave
30:37 Data byte from slave – 8 bits
38 Acknowledge from master
39 Stop
Control Registers
Byte 0:Control Register 0
Bit @Pup Name Description
7 0 Reserved Reserved, Set = 0
6 1 PCIF PCI Drive Strength Override
PCI 0 = Force All PCI and PCIF Outputs to Low Drive Strength
1 = Force All PCI and PCIF Outputs to High Drive Strength

CY28409
Byte 0:Control Register 0 (continued)
3 Externally PCI_STP# PCI_STP# reflects the current value of the external PCI_STP# pin.
Selected 0 =PCI_STP# pin is low.
2 Externally CPU_STP# CPU_STP# reflects the current value of the external CPU_STP# pin.
Selected 0 = CPU_STP# pin is low.
1 Externally FS_B FS_B reflects the value of the FS_B pin sampled on power-up.
Selected
0 Externally FS_A FS_A reflects the value of the FS_A pin sampled on power-up.
Selected
Byte 1: Control Register 1

7 0 SRCT, SRCC Allows control of SRCT/C with assertion of PCI_STP# or SW PCI_STP
0 = Free Running, 1 = Stopped with PCI_STP#
6 1 SRCT, SRCC SRCT/C Output Enable; 0 = Disabled (Hi-z), 1 = Enabled
2 1 CPUT2, CPUC2 CPUT/C2 Output Enable; 0 = Disabled (Hi-z), 1 = Enabled

7 0 SRCT, SRCC SRCT/C Pwrdwn Drive Mode
0 = Driven during power-down, 1 = Three-state during power-down
6 0 SRCT, SRCC SRCT/C Stop Drive Mode
0 = Driven during PCI_STP, 1 = Three-state during PCI_STP
5 0 CPUT2, CPUC2 CPUT/C2 Pwrdwn Drive Mode
0 = Driven during power ‘down, 1 = Three-state during power-down
2 0 CPUT2, CPUC2 CPUT/C2 stop Drive Mode
0 = Driven when stopped, 1 = Three-state when stopped

7 1 SW PCI STOP SW PCI_STP Function
0= PCI_STP assert, 1= PCI_STP deassert
When this bit is set to 0, all STOPPABLE PCI, PCIF and SRC outputs will
be stopped in a synchronous manner with no short pulses.
When this bit is set to 1, all STOPPED PCI,PCIF and SRC outputs will
resume in a synchronous manner with no short pulses.
6 1 PCI6 PCI6 Output Enable
0 = Disabled, 1 = Enabled

CY28409

7 0 USB_48 USB_48 Drive Strength
0 = High drive strength, 1 = Low drive strength
6 1 USB_48 USB_48 Output Enable
5 0 PCIF2 Allow control of PCIF2 with assertion of PCI_STP# or SW PCI_STP
2 1 PCIF2 PCIF2 Output Enable

7 1 DOT_48 DOT_48 Output Enable
5 0 3V66_4/VCH VCH Select 66 MHz/48 MHz
0 = 3V66 mode, 1 = VCH (48 MHz) mode
4 1 3V66_4/VCH 3V66_4/VCH Output Enable
3 1 3V66_3 3V66_3 Output Enable

CY28409
5 0 CPUC0, CPUT0 FS_A & FS_B Operation
CPUC1, CPUT1 0 = Normal, 1 = Test mode
CPUC2, CPUT2
4 0 SRCT, SRCC SRC Frequency Select
0 = 100Mhz, 1 = 200MHz
3 0 PCIF Spread Spectrum Mode
PCI 0 = down (default), 1 = center
3V66
SRCT,SRCC
CPUT_ITP,CPUC_ITP
2 0 PCIF Spread Spectrum Enable
PCI 0 = Spread Off, 1 = Spread On
3V66
SRCT,SRCC
CPUT_ITP,CPUC_ITP
1 1 REF_1 REF_1 Output Enable
0 1 REF_0 REF_0 Output Enable
Byte 7: Vendor ID
7 0 Revision ID Bit 3 Revision ID Bit 3
3 1 Vendor ID Bit 3 Vendor ID Bit 3
Crystal Recommendations
The CY28409 requires a Parallel Resonance Crystal.
Substituting a series resonance crystal will cause the
CY28409 to operate at the wrong frequency and violate the
ppm specification. For most applications there is a 300-ppm
frequency shift between series and parallel crystals due to
incorrect loading.
Table 6. Crystal Recommendations
Frequency Drive Shunt Cap Motional Tolerance Stability Aging
(Fund) Cut Loading Load Cap (max.) (max.) (max.) (max.) (max.) (max.)
14.31818 MHz AT Parallel 20 pF 0.1 mW 5 pF 0.016 pF 50 ppm 50 ppm 5 ppm
Crystal Loading
Crystal loading plays a critical role in achieving low ppm perfor-
mance. To realize low ppm performance, the total capacitance
the crystal will see must be considered to calculate the appro-
priate capacitive loading (CL).

CY28409
The following diagram shows a typical crystal configuration
using the two trim capacitors. An important clarification for the Load Capacitance (each side)
following discussion is that the trim capacitors are in series Ce = 2 * CL – (Cs + Ci)
with the crystal not parallel. It’s a common misconception that Total Capacitance (as seen by the crystal)
load capacitors are in parallel with the crystal and should be CLe = 1
1
( Ce1 + Cs1 1 )
+ Ci1 + Ce2 + Cs2 + Ci2
approximately equal to the load capacitance of the crystal.
This is not true.
CL ....................................................Crystal load capacitance
CLe ......................................... Actual loading seen by crystal
using standard value trim capacitors
Ce ..................................................... External trim capacitors
Cs ..............................................Stray capacitance (terraced)
Ci .......................................................... Internal capacitance
(lead frame, bond wires etc.)
PD# (Power-down) Clarification

Figure 1. Crystal Capacitive Clarification The PD# (Power-down) pin is used to shut off ALL clocks prior
to shutting off power to the device. PD# is an asynchronous
Calculating Load Capacitors active LOW input. This signal is synchronized internally to the
device powering down the clock synthesizer. PD# is an
In addition to the standard external trim capacitors, trace asynchronous function for powering up the system. When PD#
capacitance and pin capacitance must also be considered to is low, all clocks are driven to a LOW value and held there and
correctly calculate crystal loading. As mentioned previously, the VCO and PLLs are also powered down. All clocks are shut
the capacitance on each side of the crystal is in series with the down in a synchronous manner so as not to cause glitches
crystal. This means the total capacitance on each side of the while changing to the low ‘stopped’ state.
crystal must be twice the specified crystal load capacitance
(CL). While the capacitance on each side of the crystal is in PD# Assertion
series with the crystal, trim capacitors (Ce1,Ce2) should be When PD# is sampled low by two consecutive rising edges of
calculated to provide equal capacitive loading on both sides. the CPUC clock then all clock outputs (except CPU) clocks
C lo c k C h ip must be held low on their next high to low transition. CPU
(C Y 2 8 4 0 9 ) clocks must be held with CPU clock pin driven high with a
C i2
value of 2 x Iref and CPUC undriven. Due to the state of
C i1
internal logic, stopping and holding the REF clock outputs in
P in
3 to 6 p the LOW state may require more than one clock cycle to
complete
X1 X2
C s1 C s2
T ra c e
2 .8 p F
XTAL
Ce1 Ce2 T r im
33pF
Figure 2. Crystal Loading Example
Use the following formulas to calculate the trim capacitor
values fro Ce1 and Ce2.

CY28409
PD#
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF
Figure 3. Power-down Assertion Timing Waveform
PD# Deassertion
The power-up latency between PD# rising to a valid logic ‘1’
level and the starting of all clocks is less than 1.8 ms.
Tstable
<1.8nS
PD#
CPUT, 133MHz
CPUC, 133MHz
SRCT 100MHz
SRCC 100MHz
3V66, 66MHz
USB, 48MHz
PCI, 33MHz
REF
Tdrive_PWRDN#
<300µS, >200mV
Figure 4. Power-down Deassertion Timing Waveform

CY28409
CPU_STP# Assertion
The CPU_STP# signal is an active low input used for
synchronous stopping and starting the CPU output clocks
while the rest of the clock generator continues to function.
When the CPU_STP# pin is asserted, all CPU outputs that are
set with the SMBus configuration to be stoppable via assertion
of CPU_STP# will be stopped after being sampled by two
rising edges of the internal CPUT clock. The final states of the
stopped CPU signals are CPUT = HIGH and CPUC = LOW.
There is no change to the output drive current values during
the stopped state. The CPUT is driven HIGH with a current
value equal to (Mult 0 ‘select’) x (Iref), and the CPUC signal
will not be driven. Due to the external pull-down circuitry,
CPUC will be LOW during this stopped state.
CPU_STP#
CPUT
CPUC
Figure 5. CPU_STP# Assertion Waveform
CPU_STP# Deassertion
The de-assertion of the CPU_STP# signal will cause all CPU
outputs that were stopped to resume normal operation in a
synchronous manner. Synchronous manner meaning that no
short or stretched clock pulses will be produce when the clock
resumes. The maximum latency from the deassertion to active
outputs is no more than two CPU clock cycles
CPU_STP#
CPUT
CPUC
CPU Internal
Tdrive_CPU_STP#,10nS>200mV
Figure 6. CPU_STP# Deassertion Waveform

CY28409
PCI_STP# Assertion[2]
The PCI_STP# signal is an active LOW input used for
synchronous stopping and starting the PCI outputs while the
rest of the clock generator continues to function. The set-up
time for capturing PCI_STP# going LOW is 10 ns (tSU). (See
Figure 7.) The PCIF clocks will not be affected by this pin if
their corresponding control bit in the SMBus register is set to
allow them to be free-running.
Tsu
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 7. PCI_STP# Assertion Waveform

PCI_STP# Deassertion
The deassertion of the PCI_STP# signal will cause all PCI and
stoppable PCIF clocks to resume running in a synchronous
manner within two PCI clock periods after PCI_STP# transi-
tions to a high level.
Tsu Tdrive_SRC
PCI_STP#
PCI_F
PCI
SRC 100MHz
Figure 8. PCI_STP# Deassertion Waveform

Note:
2. The PCI STOP function is controlled by two inputs. One is the device PCI_STP# pin number 34 and the other is SMBus byte 0 bit 3. These two inputs are logically
ANDed. If either the external pin or the internal SMBus register bit is set low then the stoppable PCI clocks will be stopped in a logic low state. Reading SMBus
Byte 0 Bit 3 will return a 0 value if either of these control bits are set LOW thereby indicating the device’s stoppable PCI clocks are not running.

CY28409
FS_A, FS_B
VTT_PWRGD#
PWRGD_VRM
0.2-0.3mS Wait for Sample Sels Device is not affected,

VDD Clock Gen
Delay VTT_PWRGD# VTT_PWRGD# is ignored
Clock State State 0 State 1 State 2 State 3
Off On
Clock Outputs
Off On
Clock VCO
Figure 9. VTT_PWRGD# Timing Diagram
S1 S2
Delay VTT_PWRGD# = Low Sample

>0.25mS Inputs straps
VDDA = 2.0V
Wait for <1.8ms
S0 S3
VDDA = off Normal Enable Outputs
Power Off Operation
VTT_PWRGD# = toggle
Figure 10. Clock Generator Power-up/Run State Diagram

CY28409
Absolute Maximum Conditions
Parameter Description Condition Min. Max. Unit
VDD Core Supply Voltage –0.5 4.6 V
VDD_A Analog Supply Voltage –0.5 4.6 V
VIN Input Voltage Relative to VSS –0.5 VDD + 0.5 VDC
TS Temperature, Storage Non-functional –65 150 °C
TA Temperature, Operating Ambient Functional 0 70 °C
TJ Temperature, Junction Functional – 150 °C
ØJC Dissipation, Junction to Case Mil-Spec 883E Method 1012.1 – 15 °C/W
ØJA Dissipation, Junction to Ambient JEDEC (JESD 51) – 45 °C/W
ESDHBM ESD Protection (Human Body Model) MIL-STD-883, Method 3015 2000 – V
UL–94 Flammability Rating @ 1/8 in. V–0
MSL Moisture Sensitivity Level 1
Multiple Supplies: The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing
is NOT required.
DC Electrical Specifications
VDD_A, 3.3V Operating Voltage 3.3 ± 5% 3.135 3.465 V
VDD_REF,
VDD_PCI,
VDD_3V66,
VDD_48,
VDD_CPU
VILI2C Input Low Voltage SDATA, SCLK – 1.0 V
VIHI2C Input High Voltage SDATA, SCLK 2.2 – V
VIL Input Low Voltage VSS – 0.5 0.8 V
VIH Input High Voltage 2.0 VDD + 0.5 V
IIL Input Low Leakage Current except internal pull-ups resistors, 0 < VIN < VDD –5 µA
IIH Input High Leakage Current except internal pull-down resistors, 0 < VIN < VDD 5 µA
VOL Output Low Voltage IOL = 1 mA – 0.4 V
VOH Output High Voltage IOH = –1 mA 2.4 – V
IOZ High-impedance Output Current –10 10 µA
IDD Dynamic Supply Current All outputs loaded per Table 9 and Figure 11 – 350 mA
CIN Input Pin Capacitance 2 5 pF
COUT Output Pin Capacitance 3 6 pF
LIN Pin Inductance – 7 nH
VXIH Xin High Voltage 0.7VDD VDD V
VXIL Xin Low Voltage 0 0.3VDD V
IPD3.3V Power-down Supply Current PD# Asserted – 1 mA

CY28409
AC Electrical Specifications
Crystal
TDC XIN Duty Cycle The device will operate reliably with input duty
cycles up to 30/70 but the REF clock duty cycle 47.5 52.5 %
will not be within specification
TPERIOD XIN Period When XIN is driven from an external clock
69.841 71.0 ns
source
TR / TF XIN Rise and Fall Times Measured between 0.3VDD and 0.7VDD – 10.0 ns
TCCJ XIN Cycle to Cycle Jitter As an average over 1-µs duration – 500 ps
LACC Long-term Accuracy Over 150 ms 300 ppm
CPU at 0.7V
TDC CPUT and CPUC Duty Cycle Measured at crossing point VOX 45 55 %
TPERIOD 100-MHz CPUT and CPUC Period Measured at crossing point VOX 9.9970 10.003 ns
TSKEW Any CPUT/C to CPUT/C Clock Skew Measured at crossing point VOX – 100 ps
TCCJ CPUT/C Cycle to Cycle Jitter Measured at crossing point VOX – 125 ps
TR / TF CPUT and CPUC Rise and Fall Times Measured from VOL = 0.175 to VOH = 0.525V 175 700 ps
TRFM Rise/Fall Matching Determined as a fraction of 2*(TR – TF)/(TR + TF) – 20 %
∆TR Rise Time Variation – 125 ps
∆TF Fall Time Variation – 125 ps
VHIGH Voltage High Math averages Figure 11 660 850 mv
VLOW Voltage Low Math averages Figure 11 –150 – mv
VOX Crossing Point Voltage at 0.7V Swing 250 550 mv
VOVS Maximum Overshoot Voltage – VHIGH + 0.3 V
VUDS Minimum Undershoot Voltage –0.3 – V
VRB Ring Back Voltage See Figure 11. Measure SE – 0.2 V
SRC
TDC SRCT and SRCC Duty Cycle Measured at crossing point VOX 45 55 %
TPERIOD 100 MHz SRCT and SRCC Period Measured at crossing point VOX 9.9970 10.003 ns
TPERIOD 200 MHz SRCT and SRCC Period Measured at crossing point VOX 4.9985 5.0015 ns
TCCJ SRCT/C Cycle to Cycle Jitter Measured at crossing point VOX – 125 ps
LACC SRCT/C Long Term Accuracy Measured at crossing point VOX – 300 ppm
TR / TF SRCT and SRCC Rise and Fall Times Measured from VOL = 0.175 to VOH = 0.525V 175 700 ps
TRFM Rise/Fall Matching Determined as a fraction of 2*(TR – TF)/(TR + TF) – 20 %
∆TR Rise Time Variation – 125 ps
∆TF Fall Time Variation – 125 ps
VHIGH Voltage High Math averages Figure 11 660 850 mv
VLOW Voltage Low Math averages Figure 11 –150 – mv
VOX Crossing Point Voltage at 0.7V Swing 250 550 mV
VOVS Maximum Overshoot Voltage – VHIGH + 0.3 V
VUDS Minimum Undershoot Voltage –0.3 – V
VRB Ring Back Voltage See Figure 11. Measure SE – 0.2 V
3V66
TDC 3V66 Duty Cycle Measurement at 1.5V 45 55 %
TPERIOD Spread Disabled 3V66 Period Measurement at 1.5V 14.9955 15.0045 ns
TPERIOD Spread Enabled 3V66 Period Measurement at 1.5V 14.9955 15.0799 ns
THIGH 3V66 High Time Measurement at 2.0V 4.9500 – ns
TLOW 3V66 Low Time Measurement at 0.8V 4.5500 – ns

CY28409
AC Electrical Specifications (continued)
TR / TF 3V66 Rise and Fall Times Measured between 0.8V and 2.0V 0.5 2.0 ns
TSKEW Any 3V66 to Any 3V66 Clock Skew Measurement at 1.5V – 250 ps
TCCJ 3V66 Cycle to Cycle Jitter Measurement at 1.5V – 250 ps
PCI/PCIF
TDC PCI Duty Cycle Measurement at 1.5V 45 55 %
TPERIOD Spread Disabled PCIF/PCI Period Measurement at 1.5V 29.9910 30.0009 ns
TPERIOD Spread Enabled PCIF/PCI Period Measurement at 1.5V 29.9910 30.1598 ns
THIGH PCIF and PCI high time Measurement at 2.0V 12.0 – ns
TLOW PCIF and PCI low time Measurement at 0.8V 12.0 – ns
TR / TF PCIF and PCI rise and fall times Measured between 0.8V and 2.0V 0.5 2.0 ns
TSKEW Any PCI clock to Any PCI clock Skew Measurement at 1.5V – 500 ps
TCCJ PCIF and PCI Cycle to Cycle Jitter Measurement at 1.5V – 250 ps
DOT
TDC Duty Cycle Measurement at 1.5V 45 55 %
TPERIOD Period Measurement at 1.5V 20.8271 20.8396 ns
TSKEW Any 48-MHz to 48-MHz Clock Skew Measured at crossing point VOX – 500 ps
THIGH USB high time Measurement at 2.0V 8.994 10.486 ns
TLOW USB low time Measurement at 0.8V 8.794 10.386 ns
TR / TF Rise and Fall Times Measured between 0.8V and 2.0V 0.5 1.0 ns
TCCJ Cycle to Cycle Jitter Measurement at 1.5V – 350 ps
USB
TDC Duty Cycle Measurement at 1.5V 45 55 %
TPERIOD Period Measurement at 1.5V 20.8271 20.8396 ns
TSKEW Any 48-MHz to 48-MHz Clock Skew Measured at crossing point VOX – 500 ps
THIGH USB high time Measurement at 2.0V 8.094 10.036 ns
TLOW USB low time Measurement at 0.8V 7.694 9.836 ns
TR / TF Rise and Fall Times Measured between 0.8V and 2.0V 1.0 2.0 ns
TCCJ Cycle to Cycle Jitter Measurement at 1.5V – 350 ps
REF
TDC REF Duty Cycle Measurement at 1.5V 45 55 %
TPERIOD REF Period Measurement at 1.5V 69.827 69.855 ns
TSKEW Any REF to REF Clock Skew Measured at crossing point VOX – 500 ps
TR / TF REF Rise and Fall Times Measured between 0.8V and 2.0V 0.5 2.0 ns
TCCJ REF Cycle to Cycle Jitter Measurement at 1.5V – 1000 ps
ENABLE/DISABLE and SET-UP
TSTABLE Clock Stabilization from Power-up – 1.8 ms
TSS Stopclock Set-up Time 10.0 – ns
TSH Stopclock Hold Time 0 – ns
Table 7. Group Timing Relationship and Tolerances Table 8. USB to DOT Phase Offset
Offset Parameter Typical Value Tolerance
Group Conditions Min. Max.
DOT Skew 0° 0.0 ns 1000 ps
3V66 to PCI 3V66 Leads PCI 1.5 ns 3.5 ns
USB Skew 180° 0.0 ns 1000 ps
VCH SKew 0° 0.0 ns 1000 ps

CY28409
Table 9. Maximum Lumped Capacitive Output Loads
Clock Max Load Unit
PCI Clocks 30 pF
3V66 Clocks 30 pF
USB Clock 20 pF
DOT Clock 10 pF
REF Clock 30 pF
Test and Measurement Set-up

For Differential CPU and SRC Output Signals
The following diagram shows lumped test load configurations
for the differential Host Clock Outputs.
33Ω T PCB M e a s u re m e n t
CPUT P o in t
4 9 .9 Ω 2pF
33Ω T PCB M e a s u re m e n t
CPUC P o in t
4 9 .9 Ω 2pF
IR E F
475Ω
Figure 11. 0.7V Load Configuration
O u tp u t u n d e r T e s t
P ro b e
Load C ap
3 . 3 V s ig n a l s
tD C
- -
3 .3 V
2 .0 V
1 .5 V
0 .8 V
0V
Tr Tf
Figure 12. Lumped Load For Single-ended Output Signals (for AC Parameters Measurement)
Table 10. CPU Clock Current Select Function

Board Target Trace/Term Z Reference R, IREF – VDD (3*RREF) Output Current Voh @ Z
50 Ohms RREF = 475 1%, IREF = 2.32 mA IOH = 6*IREF 0.7V @ 50
Ordering Information
Part Number Package Type Product Flow
CY28409OC 56-pin SSOP Commercial, 0° to 70°C
CY28409OCT 56-pin SSOP – Tape and Reel Commercial, 0° to 70°C
CY28409ZC 56-pin TSSOP Commercial, 0° to 70°C
CY28409ZCT 56-pin TSSOP – Tape and Reel Commercial, 0° to 70°C

CY28409
Package Drawings and Dimensions

56-lead Shrunk Small Outline Package O56
51-85062-*C
56-lead Thin Shrunk Small Outline Package, Type II (6 mm x 14 mm) Z56
51-85060-*B
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips
I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification
as defined by Philips. Intel and Pentium are registered trademarks of Intel Corporation. All product and company names mentioned
in this document are the trademarks of their respective holders.

© Cypress Semiconductor Corporation, 2003. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY28409
Document History Page
Document Title: CY28409 Clock Synthesizer with Differential SRC and CPU Outputs
Document Number: 38-07445
Orig. of
REV. ECN NO. Issue Date Change Description of Change
** 121414 12/04/02 RGL New Data Sheet
*A 124795 07/07/03 RGL Changed revision code to 4
Corrected rise/fall time value on DOT from 1.0/2.0 to 0.5/1.0 ns, respectively
Changed USB and DOT from long-term jitter to cycle-to-cycle jitter
Changed USB and DOT period value from 28.8257/28.8340 to
20.8271/20.8396 ns, respectively
*B 128864 08/29/03 RGL Fixed the I2C registers to match the actual device
Removed all items referencing to 166 MHz

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CY28409

Clock Synthesizer with Differential SRC and CPU Outputs

Features • Three differential CPU clock pairs

VDD_REF REF_0 1 56 FS_B

VTT_PWRGD# PCIF1 8 49 PCI_STP#

Document #: 38-07445 Rev. *B Page 2 of 18

Table 2. Frequency Select Table (FS_A FS_B) SMBus Bit 5 of Byte 6 = 1

Serial Data Interface Data Protocol

Table 4. Block Read and Block Write Protocol

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Table 5. Byte Read and Byte Write protocol

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Byte 1: Control Register 1

Byte 2: Control Register 2

Byte 3: Control Register 3

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Byte 4: Control Register 4

Byte 5: Control Register 5

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PD# (Power-down) Clarification

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Figure 3. Power-down Assertion Timing Waveform

Figure 4. Power-down Deassertion Timing Waveform

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Figure 5. CPU_STP# Assertion Waveform

Figure 6. CPU_STP# Deassertion Waveform

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Figure 7. PCI_STP# Assertion Waveform

Figure 8. PCI_STP# Deassertion Waveform

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0.2-0.3mS Wait for Sample Sels Device is not affected,

Clock State State 0 State 1 State 2 State 3

Figure 9. VTT_PWRGD# Timing Diagram

Delay VTT_PWRGD# = Low Sample

Wait for <1.8ms

Figure 10. Clock Generator Power-up/Run State Diagram

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Test and Measurement Set-up

Figure 11. 0.7V Load Configuration

Table 10. CPU Clock Current Select Function

Document #: 38-07445 Rev. *B Page 16 of 18

Package Drawings and Dimensions

56-lead Thin Shrunk Small Outline Package, Type II (6 mm x 14 mm) Z56

Document #: 38-07445 Rev. *B Page 17 of 18

Document #: 38-07445 Rev. *B Page 18 of 18

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