QDD 400G VSR4 C - Datasheets - EN
QDD 400G VSR4 C - Datasheets - EN
QDD 400G VSR4 C - Datasheets - EN
Arista Networks® QDD-400G-VSR4 Compatible TAA 400GBase-SR4 PAM4 112G QSFP-DD Transceiver (MMF,
850nm, 50m, MPO-12, DOM, CMIS 4.0)
Features:
• 53.125 GBd PAM4 4 channel 400G-SR4 Optical interface
• 26.5625 GBd PAM4 8 channel 400G AUI-8 C2M Electrical
interface
• Compliant with IEEE 802.3ck and IEEE 802.3db
• QSFP-DD MSA package with MPO-12 APC
• Multi-mode Fiber
• Commercial Temperature 0 to 70 Celsius
• Hot Pluggable
• Metal with Lower EMI
• Excellent ESD Protection
• CMIS Rev4.0
• RoHS Compliant and Lead Free
Applications:
• 400GBase Ethernet
• Datacenter switch
Product Description
This Arista Networks® QDD-400G-VSR4 compatible QSFP-DD transceiver provides 400GBase-SR4 throughput up
to 50m over multi-mode fiber (MMF) using a wavelength of 850nm via an MPO-12 connector. It is guaranteed
to be 100% compatible with the equivalent Arista Networks® transceiver. This easy to install, hot swappable
transceiver has been programmed, uniquely serialized and data-traffic and application tested to ensure that it
will initialize and perform identically. Digital optical monitoring (DOM) support is also present to allow access
to real-time operating parameters. This transceiver is Trade Agreements Act (TAA) compliant. We stand behind
the quality of our products and proudly offer a limited lifetime warranty.
TAA refers to the Trade Agreements Act (19 U.S.C. & 2501-2581), which is intended to
foster fair and open international trade. TAA requires that the U.S. Government may
acquire only “U.S. – made or designated country end products.”
Rev. 100724
Absolute Maximum Ratings
Parameter Symbol Min. Typ. Max. Unit Notes
Notes:
1. Non-condensing.
Electrical Characteristics
Parameter Symbol Min. Typ. Max. Unit Notes
Notes:
1.
Optical Characteristics
Parameter Symbol Min. Typ. Max. Unit Notes
Transmitter
Notes:
1. RMS spectral width is the standard deviation of the spectrum.
2. Even if the TDECQ<1.8dB, the OMA (min) must exceed this value.
3. If measured into type A1a.2, type A1a.3 or type A1a.4, 50 μm fiber, in accordance with IEC 61280-1-4.
4. Average receive power, each lane (min) is informative and not the principal indicator of signal strength.
A received power below this value cannot be compliant; however, a value above this does not ensure
compliance.
Receiver sensitivity is informative and is defined for a transmitter with a value of SECQ up to 4.6dB.
Pin Descriptions
Pin Logic Symbol Name/Descriptions Notes
1 GND Ground
2 CML-I Tx2n Transmitter Inverted Data Input
3 CML-I Tx2p Transmitter Non-Inverted Data Input
4 GND Ground 1
5 CML-I Tx4n Transmitter Inverted Data Input
6 CML-I Tx4p Transmitter Non-Inverted Data Input
7 GND Ground 1
8 LVTTL-I ModSelL Module Select
9 LVTTL-I ResetL Module Reset
10 VccRx 3.3V Power Supply Receiver 2
11 LVCMOS–I/O SCL 2 Wire Serial Interface Clock
12 LVCMOS–I/O SDA 2 Wire Serial Interface Data
13 GND Ground 1
14 CML-O Rx3n Transmitter Inverted Data Output
15 CML-O Rx3p Transmitter Non-Inverted Data Output
16 GND Ground 1
17 CML-O Rx1n Transmitter Inverted Data Output
18 CML-O Rx1p Transmitter Non-Inverted Data Output
19 GND Ground 1
20 GND Ground 1
21 CML-O Rx2n Transmitter Inverted Data Output
22 CML-O Rx2p Transmitter Non-Inverted Data Output
23 GND Ground 1
24 CML-O Rx4n Transmitter Inverted Data Output
25 CML-O Rx4p Transmitter Non-Inverted Data Output
26 GND Ground 1
27 LVTTL-O ModPrsL Module Present
28 LVTTL-O IntL Interrupt
29 VccRx 3.3V Power Supply Transmitter 2
30 Vcc l 3.3V Power Supply 2
31 LVTTL-I InitMode Initialization mode. In legacy QSFP applications, the InitMode pad is
called LPMODE.
32 GND Ground 1
33 CML-I Tx1n Transmitter Inverted Data Input
34 CML-I Tx1p Transmitter Non-Inverted Data Input
35 GND Ground 1
36 CML-I Tx1n Transmitter Inverted Data Input
37 CML-I Tx1p Transmitter Non-Inverted Data Input
38 GND Ground 1
39 GND Ground 1
40 CML-I Tx6n Transmitter Inverted Data Input
41 CML-I Tx6p Transmitter Non-Inverted Data Input
42 GND Ground 1
43 CML-I Tx8n Transmitter Inverted Data Input
44 CML-I Tx8p Transmitter Non-Inverted Data Input
45 GND Ground 1
46 Reserved NC 3
47 VS1 NC 3
48 VccRx1 3.3V Power Supply 2
49 VS2 NC 3
50 VS3 NC 3
51 GND Ground 1
52 CML-O Rx7n Transmitter Inverted Data Output
53 CML-O Rx7p Transmitter Non-Inverted Data Output
54 GND Ground 1
55 CML-O Rx5n Transmitter Inverted Data Output
56 CML-O Rx5p Transmitter Non-Inverted Data Output
57 GND Ground 1
58 GND Ground 1
59 CML-O Rx6n Transmitter Inverted Data Output
60 CML-O Rx6p Transmitter Non-Inverted Data Output
61 GND Ground 1
62 CML-O Rx8n Transmitter Inverted Data Output
63 CML-O Rx8p Transmitter Non-Inverted Data
Output
64 GND Ground 1
65 NC NC 3
66 Reserved NC 3
67 VccTx1 3.3V Power Supply 2
68 Vcc2 3.3V Power Supply 2
69 Reserved NC 3
70 GND Ground 1
71 CML-I Tx7n Transmitter Inverted Data Input
72 CML-I Tx7p Transmitter Non-Inverted Data Input
73 GND Ground 1
74 CML-I Tx5n Transmitter Inverted Data Input
75 CML-I Tx5p Transmitter Non-Inverted Data Input
76 GND Ground 1
Notes:
1. QSFP-DD uses common ground (GND) for all signals and supply (power). All are common within the
QSFP-DD module and all module voltages are referenced to this potential unless otherwise noted.
Connect these directly to the host board signal-common ground plane.
2. VccRx, VccRx1, Vcc1, Vcc2, VccTx and VccTx1 shall be applied concurrently. Requirements defined for
the host side of the Host Card Edge Connector are listed in Table 6. VccRx, VccRx1, Vcc1, Vcc2, VccTx and
VccTx1 may be internally connected within the module in any combination. The connector Vcc pins are
each rated for a maximum current of 1000mA.
3. All Vendor Specific, Reserved and No Connect pins may be terminated with 50 ohms to ground on the
host. Pad 65 (No Connect) shall be left unconnected within the module. Vendor specific and reserved
pads shall have an impedance to GND that is greater than 10kΩ and less than 100pF.
4. Plug Sequence specifies the mating sequence of the host connector and module. The sequence is 1A,
2A, 3A, 1B, 2B, 3B. (see Figure 2 for pad locations) Contact sequence A will make, then break contact
with additional QSFP-DD pads. Sequence 1A, 1B will then occur simultaneously, followed by 2A, 2B,
followed by 3A, 3B.
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