Lpc11u2x 1893403

LPC11U2x
32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash; up

to 10 kB SRAM and 4 kB EEPROM; USB device; USART
Rev. 2.3 — 27 March 2014 Product data sheet
1. General description
The LPC11U2x are an ARM Cortex-M0 based, low-cost 32-bit MCU family, designed for
8/16-bit microcontroller applications, offering performance, low power, simple instruction set
and memory addressing together with reduced code size compared to existing 8/16-bit
architectures.
The LPC11U2x operate at CPU frequencies of up to 50 MHz.
Equipped with a highly flexible and configurable Full-Speed USB 2.0 device controller, the
LPC11U2x brings unparalleled design flexibility and seamless integration to today’s
demanding connectivity solutions.
The peripheral complement of the LPC11U2x includes up to 32 kB of flash memory, up to 10

2
kB of SRAM data memory and 4 kB EEPROM, one Fast-mode Plus I C-bus interface, one
RS-485/EIA-485 USART with support for synchronous mode and smart card
interface, two SSP interfaces, four general-purpose counter/timers, a 10-bit ADC
(Analog-to-Digital Converter), and up to 54 general-purpose I/O pins.
For additional documentation related to the LPC11U2x parts, see Section 15

“References”.
2. Features and benefits
■ System:
◆ ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.
◆ ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).
◆ Non-Maskable Interrupt (NMI) input selectable from several input sources.
◆ System tick timer.
■ Memory:
◆ Up to 32 kB on-chip flash program memory.
◆ Up to 4 kB on-chip EEPROM data memory; byte erasable and byte programmable. ◆

Up to 10 kB SRAM data memory.
◆ 16 kB boot ROM.
◆ In-System Programming (ISP) and In-Application Programming (IAP) for flash and
EEPROM via on-chip bootloader software.
◆ ROM-based USB drivers. Flash updates via USB supported.
◆ ROM-based 32-bit integer division routines.
■ Debug options:
NXP Semiconductors LPC11U2x 32-bit ARM Cortex-M0 microcontroller

◆ Standard JTAG (Joint Test Action Group) test interface for BSDL (Boundary Scan
Description Language).
◆ Serial Wire Debug.
■ Digital peripherals:
◆ Up to 54 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down

resistors, repeater mode, and open-drain mode.
◆ Up to 8 GPIO pins can be selected as edge and level sensitive interrupt sources.
◆ Two GPIO grouped interrupt modules enable an interrupt based on a

programmable pattern of input states of a group of GPIO pins.
◆ High-current source output driver (20 mA) on one pin.
◆ High-current sink driver (20 mA) on true open-drain pins.
◆ Four general-purpose counter/timers with a total of up to 5 capture inputs and 13

match outputs.
◆ Programmable Windowed WatchDog Timer (WWDT) with a dedicated, internal
low-power WatchDog Oscillator (WDO).
■ Analog peripherals:
◆ 10-bit ADC with input multiplexing among eight pins.
■ Serial interfaces:
◆ USB 2.0 full-speed device controller.
◆ USART (Universal Synchronous Asynchronous Receiver/Transmitter) with

fractional baud rate generation, internal FIFO, a full modem control handshake
interface, and support for RS-485/9-bit mode and synchronous mode. USART
supports an asynchronous smart card interface (ISO 7816-3).
◆ Two SSP (Synchronous Serial Port) controllers with FIFO and multi-protocol
capabilities.
2 2
◆ I C-bus interface supporting the full I C-bus specification and Fast-mode Plus with a
data rate of up to 1 Mbit/s with multiple address recognition and monitor mode.
■ Clock generation:
◆ Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator).
◆ 12 MHz high-frequency Internal RC oscillator (IRC) that can optionally be used as a

system clock.
◆ Internal low-power, low-frequency WatchDog Oscillator (WDO) with programmable
frequency output.
◆ PLL allows CPU operation up to the maximum CPU rate with the system oscillator or
the IRC as clock sources.
◆ A second, dedicated PLL is provided for USB.
◆ Clock output function with divider that can reflect the crystal oscillator, the main
clock, the IRC, or the watchdog oscillator.
■ Power control:
◆ Integrated PMU (Power Management Unit) to minimize power consumption during

Sleep, Deep-sleep, Power-down, and Deep power-down modes.
◆ Power profiles residing in boot ROM provide optimized performance and minimized
power consumption for any given application through one simple function call.
◆ Four reduced power modes: Sleep, Deep-sleep, Power-down, and Deep
power-down.
◆ Processor wake-up from Deep-sleep and Power-down modes via reset, selectable
GPIO pins, watchdog interrupt, or USB port activity.
LPC11U2X All information provided in this document is subject to legal disclaimers. © NXP B.V. 2014. All rights reserved. Product data sheet Rev. 2.3 — 27 March 2014 2 of 74
◆ Processor wake-up from Deep power-down mode using one special function pin.
◆ Power-On Reset (POR).
◆ Brownout detect with four separate thresholds for interrupt and forced reset.
■ Unique device serial number for identification.
■ Single 3.3 V power supply (1.8 V to 3.6 V).
■ Temperature range −40 °C to +85 °C.
■ Available as LQFP64, LQFP48, TFBGA48, and HVQFN33 packages.
3. Applications
■ Consumer peripherals ■ Handheld scanners
■ Medical ■ USB audio devices
■ Industrial control
4. Ordering information
Table 1. Ordering information

Type number Package
Name Description Version
plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm

LPC11U22FBD48/30 LQFP48 SOT313-
1 2

1 2
LPC11U24FHI33/30 plastic thermal enhanced very thin quad flat package; no leads; n/a
1 HVQFN3
33 terminals; body 5 × 5 × 0.85 mm
3

1 2
plastic thin fine-pitch ball grid array package; 48 balls; body 4.5 ×
LPC11U24FET48/30 SOT1155-
1 TFBGA4 2
8 4.5 × 0.7 mm
LPC11U24FHN33/40 plastic thermal enhanced very thin quad flat package; no leads; n/a
1 HVQFN3
33 terminals; body 7 × 7 × 0.85 mm
3

1 2
plastic low profile quad flat package; 64 leads; body 10 × 10 × 1.4

1 2
mm
4.1 Ordering options

Table 2. Part ordering options
Part Number Fla EEPR Main USB US I2C- SS ADC GPI Package
sh OM SR SR B bus P channel O
(kB (kB) AM AM FM+ s
) (kB) (kB)
LPC11U22FBD48/30 16 1 6 2 1 1 2 8 40 LQFP48
1
LPC11U23FBD48/30 24 1 6 2 1 1 2 8 40 LQFP48
1
HVQFN33 (5 ×
LPC11U24FHI33/30 32 2 6 2 1 1 2 8 26
1
5)
LPC11U24FBD48/30 32 2 6 2 1 1 2 8 40 LQFP48
1
LPC11U24FET48/30 32 2 6 2 1 1 2 8 40 TFBGA48
1
HVQFN33 (7 ×
LPC11U24FHN33/4 32 4 8 2 1 1 2 8 26
01
7)
LPC11U24FBD48/40 32 4 8 2 1 1 2 8 40 LQFP48
1
LPC11U24FBD64/40 32 4 8 2 1 1 2 8 54 LQFP64
1
5. Block diagram
RESET SWD, JTAG
XTALIN XTALOUT
LPC11U2x
SYSTEM OSCILLATOR
TEST/DEBUG
CLOCK
INTERFACE
GENERATION,
IRC, WDO
POWER CONTROL,
CLKOUT
SYSTEM
BOD
ARM
FUNCTIONS
CORTEX-M0
POR
PLL0 USB PLL

EEPROM
1/2/4 kB
FLASH
ROM
SRAM
system bus
16/24/32 kB
16 kB
8/10 kB
master
slave slave
slave
USB_DP
slave
USB_DM
USB DEVICE
HIGH-SPEED
GPIO ports 0/1 AHB-LITE BUS
slave
USB_VBUS
CONTROLLER
GPIO
USB_FTOGGLE,
USB_CONNECT
slave
AHB TO APB
BRIDGE
RXD
TXD
10-bit ADC USART/
(1) (1)
DCD, DSR , RI
SMARTCARD INTERFACE AD[7:0]
CTS, RTS, DTR
SCLK
SCL, SDA
2
I C-BUS
16-bit COUNTER/TIMER 0 CT16B0_MAT[2:0]
(2)
CT16B0_CAP[1:0]
SSP0 SCK0, SSEL0,
CT16B1_MAT[1:0]
MISO0, MOSI0
16-bit COUNTER/TIMER 1
(2)
CT16B1_CAP[1:0]
SSP1 SCK1, SSEL1,
MISO1, MOSI1
(2)
CT32B0_CAP[1:0]
IOCON
(2)
CT32B1_CAP[1:0]
SYSTEM CONTROL
WINDOWED WATCHDOG
PMU
TIMER
GPIO pins
GPIO INTERRUPTS
GPIO pins
GPIO GROUP0 INTERRUPTS
GPIO pins GPIO GROUP1 INTERRUPTS
002aag333
(1) Not available on HVQFN33 packages.

(2) CT32B1_CAP1 available on TFBGA48/LQFP64 packages only. CT16B0_CAP1 and CT16B1_CAP1 available on LQFP64
packages only. CT32B0_CAP1 available on LQFP48/TFBGA48/LQFP64 packages only.
Fig 1. Block diagram
6. Pinning information
6.1 Pinning
PIO0_16/AD5/CT32B1_MAT3/WAKEUP
SWDIO/PIO0_15/AD4/CT32B1_MAT2
PIO1_15/DCD/CT16B0_MAT2/SCK1
1 0
PIO0_19/TXD/CT32B0_MAT PIO0_18/RXD/CT32B0_MAT
PIO0_17/RTS/CT32B0_CAP0/SCLK
PIO0_23/AD7
D
V D
terminal 1
index area
32
31
30
29
28
27
26
25
1 24
PIO1_19/DTR/SSEL1 TRST/PIO0_14/AD3/CT32B1_MAT1
2 23
RESET/PIO0_0 TDO/PIO0_13/AD2/CT32B1_MAT0
3 22
PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE TMS/PIO0_12/AD1/CT32B1_CAP0 4 21
XTALIN TDI/PIO0_11/AD0/CT32B0_MAT3
LPC11U24
5 20
XTALOUT PIO0_22/AD6/CT16B1_MAT1/MISO1
6 19
VDD SWCLK/PIO0_10/SCK0/CT16B0_MAT2
7 18
PIO0_20/CT16B1_CAP0
PIO0_9/MOSI0/CT16B0_MAT1
33 VSS
8 17
PIO0_8/MISO0/CT16B0_MAT0
PIO0_2/SSEL0/CT16B0_CAP0
10
11
12
13
14
15
16
9
S L
PIO0_3/USB_VBU PIO0_4/SC PIO0_5/SDA
M P 1 0
PIO0_21/CT16B1_MAT0/MOSI USB_D USB_D PIO0_6/USB_CONNECT/SCK PIO0_7/CTS
002aag621
Transparent top view
Fig 2. Pin configuration (HVQFN33)

ball A1
LPC11U24FET48/301
index area
1357 2468
A
B
C
D
E
F
G
H
002aag623
Transparent top view
Fig 3. Pin configuration (TFBGA48)

PIO0_16/AD5/CT32B1_MAT3/WAKEUP
SWDIO/PIO0_15/AD4/CT32B1_MAT2
PIO1_15/DCD/CT16B0_MAT2/SCK1
PIO0_17/RTS/CT32B0_CAP0/SCLK
PIO1_14/DSR/CT16B0_MAT1/RXD
PIO0_18/RXD/CT32B0_MAT0
PIO0_19/TXD/CT32B0_MAT1
PIO1_16/RI/CT16B0_CAP0
PIO1_22/RI/MOSI1
PIO0_23/AD7
D
V D
S
V S
48
47
46
45
44
43
42
41
40
39
38
37
1
36
PIO1_25/CT32B0_MAT1 PIO1_13/DTR/CT16B0_MAT0/TXD 2
35
PIO1_19/DTR/SSEL1 TRST/PIO0_14/AD3/CT32B1_MAT1 3
34
RESET/PIO0_0 TDO/PIO0_13/AD2/CT32B1_MAT0
4
33
PIO0_1/CLKOUT/CT32B0_MAT2/USB_FTOGGLE TMS/PIO0_12/AD1/CT32B1_CAP0 5
32
VSS TDI/PIO0_11/AD0/CT32B0_MAT3
LPC11U22FBD48/301
LPC11U23FBD48/301
6
31
XTALIN PIO1_29/SCK0/CT32B0_CAP1
LPC11U24FBD48/301
7
30
XTALOUT PIO0_22/AD6/CT16B1_MAT1/MISO1
LPC11U24FBD48/401
8
29
VDD SWCLK/PIO0_10/SCK0/CT16B0_MAT2
9
28
PIO0_20/CT16B1_CAP0 PIO0_9/MOSI0/CT16B0_MAT1
10
27
PIO0_2/SSEL0/CT16B0_CAP0 PIO0_8/MISO0/CT16B0_MAT0 11
26
PIO1_26/CT32B0_MAT2/RXD PIO1_21/DCD/MISO1
12
25
PIO1_27/CT32B0_MAT3/TXD PIO1_31
13
14
15
16
17
18
19
20
21
22
23
24
002aag622
PIO1_20/DSR/SCK1
PIO0_4/SCL
PIO0_21/CT16B1_MAT0/MOSI1
PIO1_23/CT16B1_MAT1/SSEL1
PIO1_24/CT32B0_MAT0
PIO0_6/USB_CONNECT/SCK0
PIO1_28/CT32B0_CAP0/SCLK
PIO0_7/CTS
USB_DP
PIO0_3/USB_VBUS
PIO0_5/SDA
USB_DM
Fig 4. Pin configuration (LQFP48)

SWDIO/PIO0_15
PIO1_15
PIO0_23
PIO0_16
PIO1_22
PIO1_14
PIO1_16
PIO0_19
PIO0_18
PIO0_17
PIO1_12
PIO1_9
PIO1_3
PIO1_6
D
V D
S
V S
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1
48
PIO1_0 VDD
2
47
PIO1_25 PIO1_13
3
46
PIO1_19 TRST/PIO0_14
4
45
RESET/PIO0_0 TDO/PIO0_13
5
44
PIO0_1 TMS/PIO0_12
6
43
PIO1_7 PIO1_11
7
42
VSS TDI/PIO0_11
8
41
XTALIN PIO1_29
LPC11U24FBD64/401
9
40
XTALOUT PIO0_22
10
39
VDD PIO1_8
11
38
PIO0_20 SWCLK/PIO0_10
12
37
PIO1_10 PIO0_9
13
36
PIO0_2 PIO0_8
14
35
PIO1_26 PIO1_21
15
34
PIO1_27 PIO1_2
16
33
PIO1_4 VDD
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
002aag624
PIO0_6
PIO0_7
PIO1_5
PIO1_23
PIO1_24
PIO1_18
PIO1_28
PIO1_1
PIO0_3
PIO0_4
PIO0_5
PIO1_20
PIO0_21
PIO1_17
USB_DP
USB_DM
See Table 3 for the full pin name.
Fig 5. Pin configuration (LQFP64)
6.2 Pin description

Table 3 shows all pins and their assigned digital or analog functions in order of the GPIO
port number. The default function after reset is listed first. All port pins have internal
pull-up resistors enabled after reset except for the true open-drain pins PIO0_4 and
PIO0_5.
Every port pin has a corresponding IOCON register for programming the digital or analog
function, the pull-up/pull-down configuration, the repeater, and the open-drain modes.
The USART, counter/timer, and SSP functions are available on more than one port pin.
Table 3. Pin description

Symbol Re Typ Description
P P P Pin set e
i in i LQFP stat
e
n T n 64 [1]
H F L
V B Q
Q G F
F A P
N 4 4
8 8
3
3
RESET/PIO0_0 2 3 4 [2] I; PU I RESET — External reset input with 20 ns glitch

C filter. A LOW-going pulse as short as 50 ns on this
1 pin resets the device, causing I/O ports and
peripherals to take on their default states, and
processor execution to begin at address 0. This
pin also serves as the debug select input. LOW
level selects the JTAG boundary scan. HIGH level
selects the ARM SWD debug mode.
In deep power-down mode, this pin must be pulled
HIGH externally. The RESET pin can be left
unconnected or be used as a GPIO pin if an
external RESET function is not needed and Deep
power-down mode is not used.
- I/O PIO0_0 — General purpose digital input/output pin.
PIO0_1/CLKOUT/ 3 4 5 [3] I; PU I/O PIO0_1 — General purpose digital input/output

CT32B0_MAT2/ C pin. A LOW level on this pin during reset starts the
USB_FTOGGLE 2 ISP command handler or the USB device
enumeration.
- O CLKOUT — Clockout pin.
- O CT32B0_MAT2 — Match output 2 for 32-bit timer

0.
- O USB_FTOGGLE — USB 1 ms Start-of-Frame

signal.
PIO0_2/SSEL0/ 8 13 [3] I; PU I/O PIO0_2 — General purpose digital input/output pin.

CT16B0_CAP0 F 1
1 0 - I/O SSEL0 — Slave select for SSP0.
- I CT16B0_CAP0 — Capture input 0 for 16-bit timer

0.
PIO0_3/USB_VBUS 9 19 [3] I; PU I/O PIO0_3 — General purpose digital input/output

H 1 pin. A LOW level on this pin during reset starts the
2 4 ISP command handler. A HIGH level during reset
starts the USB device enumeration.
- I USB_VBUS — Monitors the presence of USB

bus power.
PIO0_4/SCL 1 20 [4] I; IA I/O PIO0_4 — General purpose digital input/output
0 G 1 pin (open-drain).
3 5
- I/O SCL — I2C-bus clock input/output (open-
drain). High-current sink only if I2C Fast-
mode Plus is selected in the I/O
configuration register.

P P P Pin set e
i in i LQFP stat
e
n T n 64 [1]
H F L
V B Q
Q G F
F A P
N 4 4
8 8
3
3
PIO0_5/SDA 1 21 [4] I; IA I/O PIO0_5 — General purpose digital input/output

1 H 1 pin (open-drain).
3 6
- I/O SDA — I2C-bus data input/output (open-
drain). High-current sink only if I2C Fast-
mode Plus is selected in the I/O
configuration register.
PIO0_6/ 1 29 [3] I; PU I/O PIO0_6 — General purpose digital input/output pin.

USB_CONNECT/ 5 H 2
SCK0 6 2 - O USB_CONNECT — Signal used to switch an
external 1.5 kΩ resistor under software control.
Used with the SoftConnect USB feature.
- I/O SCK0 — Serial clock for SSP0.
PIO0_7/CTS 1 30 [5] I; PU I/O PIO0_7 — General purpose digital input/output

6 G 2 pin (high-current output driver).
7 3
- I CTS — Clear To Send input for USART.
PIO0_8/MISO0/ 1 36 [3] I; PU I/O PIO0_8 — General purpose digital input/output pin.

CT16B0_MAT0 7 F 2
8 7 - I/O MISO0 — Master In Slave Out for SSP0.

0.
PIO0_9/MOSI0/ 1 37 [3] I; PU I/O PIO0_9 — General purpose digital input/output pin.

CT16B0_MAT1 8 F 2
7 8 - I/O MOSI0 — Master Out Slave In for SSP0.

0.
SWCLK/PIO0_10/ 1 38 [3] I; PU I SWCLK — Serial wire clock and test clock TCK
SCK0/ 9 E 2 for JTAG interface.
CT16B0_MAT2 7 9
- I/O PIO0_10 — General purpose digital input/output
pin.
- O SCK0 — Serial clock for SSP0.

0.
TDI/PIO0_11/AD0/ 2 42 [6] I; PU I TDI — Test Data In for JTAG interface.

CT32B0_MAT3 1 D 3
8 2 - I/O PIO0_11 — General purpose digital input/output
pin.
- I AD0 — A/D converter, input 0.

0.
TMS/PIO0_12/AD1/ 2 44 [6] I; PU I TMS — Test Mode Select for JTAG interface.

CT32B1_CAP0 2 C 3
7 3 - I/O PIO_12 — General purpose digital input/output pin.

1.
TDO/PIO0_13/AD2/ 2 45 [6] I; PU O TDO — Test Data Out for JTAG interface.

CT32B1_MAT0 3 C 3
- I/O PIO0_13 — General purpose digital input/output
pin.

1.

P P P Pin set e
i in i LQFP stat
e
n T n 64 [1]
H F L
V B Q
Q G F
F A P
N 4 4
8 8
3
3
TRST/PIO0_14/AD3/ 2 46 [6] I; PU I TRST — Test Reset for JTAG interface.

CT32B1_MAT1 4 B 3
7 5 - I/O PIO0_14 — General purpose digital input/output
pin.

1.
SWDIO/PIO0_15/ 2 52 [6] I; PU I/O SWDIO — Serial wire debug input/output.

AD4/ 5 B 3
CT32B1_MAT2 6 9 - I/O PIO0_15 — General purpose digital input/output
pin.

1.
PIO0_16/AD5/ 2 53 [6] I; PU I/O PIO0_16 — General purpose digital input/output

CT32B1_MAT3/ 6 A 4 pin. In Deep power-down mode, this pin functions
WAKEUP 6 0 as the WAKEUP pin with 20 ns glitch filter. Pull
this pin HIGH externally to enter Deep power-
down mode. Pull this
pin LOW to exit Deep power-down mode. A
LOW-going pulse as short as 50 ns wakes up
the part.

1.
PIO0_17/RTS/ 3 60 [3] I; PU I/O PIO0_17 — General purpose digital input/output

CT32B0_CAP0/SCLK 0 A 4 pin.
3 5
- O RTS — Request To Send output for USART.

0.
- I/O SCLK — Serial clock input/output for USART

in synchronous mode.
PIO0_18/RXD/ 3 61 [3] I; PU I/O PIO0_18 — General purpose digital input/output

CT32B0_MAT0 1 B 4 pin.
3 6
- I RXD — Receiver input for USART. Used in UART
ISP mode.

0.
PIO0_19/TXD/ 3 62 [3] I; PU I/O PIO0_19 — General purpose digital input/output

CT32B0_MAT1 2 B 4 pin.
2 7
- O TXD — Transmitter output for USART. Used in
UART ISP mode.

0.
PIO0_20/CT16B1_CAP0 7 9 11 [3] I; PU I/O PIO0_20 — General purpose digital input/output

F pin.
2
1.
PIO0_21/ 1 22 [3] I; PU I/O PIO0_21 — General purpose digital input/output

2 G 1 pin.
CT16B1_MAT0/ 4 7 - O CT16B1_MAT0 — Match output 0 for 16-bit timer
MOSI1 1.
- I/O MOSI1 — Master Out Slave In for SSP1.
PIO0_22/AD6/ 2 40 [6] I; PU I/O PIO0_22 — General purpose digital input/output

CT16B1_MAT1/MISO1 0 E 3 pin.
8 0

1.
- I/O MISO1 — Master In Slave Out for SSP1.

P P P Pin set e
i in i LQFP stat
e
n T n 64 [1]
H F L
V B Q
Q G F
F A P
N 4 4
8 8
3
3
PIO0_23/AD7 2 56 [6] I; PU I/O PIO0_23 — General purpose digital input/output

7 A 4 pin.
5 2
PIO1_0/CT32B1_MAT0 - - - 1 [3] I; PU I/O PIO1_0 — General purpose digital input/output pin.

1.

1.

1.

1.
PIO1_4/CT32B1_CAP0 - - - 16 [3] I; PU I/O PIO1_4 — General purpose digital input/output pin.

1.
PIO1_5/CT32B1_CAP1 - - 32 [3] I; PU I/O PIO1_5 — General purpose digital input/output pin.

H
8 - I CT32B1_CAP1 — Capture input 1 for 32-bit timer
1.
PIO1_6 - - - 64 [3] I; PU I/O PIO1_6 — General purpose digital input/output pin.
PIO1_10 - - - 12 [3] I; PU I/O PIO1_10 — General purpose digital input/output

pin.

pin.

pin.
PIO1_13/DTR/ - 47 [3] I; PU I/O PIO1_13 — General purpose digital input/output

CT16B0_MAT0/TXD B 3 pin.
8 6
- O DTR — Data Terminal Ready output for USART.

0.
- O TXD — Transmitter output for USART.
PIO1_14/DSR/ - 49 [3] I; PU I/O PIO1_14 — General purpose digital input/output

CT16B0_MAT1/RXD A 3 pin.
8 7
- I DSR — Data Set Ready input for USART.

0.
- I RXD — Receiver input for USART.
PIO1_15/DCD/ 2 57 [3] I; PU I/O PIO1_15 — General purpose digital input/output

CT16B0_MAT2/SCK1 8 A 4 pin.
4 3
I DCD — Data Carrier Detect input for USART.

0.
PIO1_16/RI/ - 63 [3] I; PU I/O PIO1_16 — General purpose digital input/output

CT16B0_CAP0 A 4 pin.
2 8
- I RI — Ring Indicator input for USART.

0.

P P P Pin set e
i in i LQFP stat
e
n T n 64 [1]
H F L
V B Q
Q G F
F A P
N 4 4
8 8
3
3
PIO1_17/ - - - 23 [3] I; PU I/O PIO1_17 — General purpose digital input/output

CT16B0_CAP1/ RXD pin.

0.
PIO1_18/ - - - 28 [3] I; PU I/O PIO1_18 — General purpose digital input/output

CT16B1_CAP1/ TXD pin.

1.
PIO1_19/DTR/SSEL1 1 2 3 [3] I; PU I/O PIO1_19 — General purpose digital input/output

B pin.
1
- O DTR — Data Terminal Ready output for USART.
- I/O SSEL1 — Slave select for SSP1.
PIO1_20/DSR/SCK1 - 18 [3] I; PU I/O PIO1_20 — General purpose digital input/output

H 1 pin.
1 3
- I DSR — Data Set Ready input for USART.
PIO1_21/DCD/MISO1 - 35 [3] I; PU I/O PIO1_21 — General purpose digital input/output

G 2 pin.
8 6
- I DCD — Data Carrier Detect input for USART.
- I/O MISO1 — Master In Slave Out for SSP1.
PIO1_22/RI/MOSI1 - 51 [3] I; PU I/O PIO1_22 — General purpose digital input/output

A 3 pin.
7 8
- I RI — Ring Indicator input for USART.
- I/O MOSI1 — Master Out Slave In for SSP1.
PIO1_23/ - 24 [3] I; PU I/O PIO1_23 — General purpose digital input/output

CT16B1_MAT1/ H 1 pin.
SSEL1 4 8
1.
- I/O SSEL1 — Slave select for SSP1.

PIO1_24/CT32B0_MAT0 - 27 [3] I; PU I/O PIO1_24 — General purpose digital input/output
G 2 pin.
6 1
0.
PIO1_25/CT32B0_MAT1 - 1 2 [3] I; PU I/O PIO1_25 — General purpose digital input/output

A pin.
1
0.

CT32B0_MAT2/ RXD G 1 pin.
2 1
0.

CT32B0_MAT3/ TXD G 1 pin.
1 2
0.

CT32B0_CAP0/ SCLK H 2 pin.
7 4
0.
- I/O SCLK — Serial clock input/output for USART

in synchronous mode.
PIO1_29/SCK0/ - 41 [3] I; PU I/O PIO1_29 — General purpose digital input/output

CT32B0_CAP1 D 3 pin.
7 1

0.

P P P Pin set e
i in i LQFP stat
e
n T n 64 [1]
H F L
V B Q
Q G F
F A P
N 4 4
8 8
3
3
PIO1_31 - - - [3] I; PU I/O PIO1_31 — General purpose digital input/output

2 pin.
5
USB_DM 25 [7] F -
USB_DM — USB bidirectional D− line.
1 G 1
3 5 9
USB_DP 26 [7] F - USB_DP — USB bidirectional D+ line.

1 H 2
4 5 0
XTALIN 6 8 [8] - - Input to the oscillator circuit and internal clock

4 D generator circuits. Input voltage must not
1 exceed 1.8 V.
XTALOUT 7 9 [8] - - Output from the oscillator amplifier.

5 E
1
VDD 6 B4 8; 10; - - Supply voltage to the internal regulator, the

; ; 4 33; external rail, and the ADC. Also used as the
2 E 4 48; ADC reference voltage.
9 2 58
VSS 3 5; 7; - - Ground.
3 B 4 54
5 1
;
D
2
[1] Pin state at reset for default function: I = Input; O = Output; PU = internal pull-up enabled; IA = inactive, no pull-up/down enabled; F =
floating; If the pins are not used, tie floating pins to ground or power to minimize power consumption.
[2] 5 V tolerant pad. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to reset the chip and wake up from Deep
power-down mode. An external pull-up resistor is required on this pin for the Deep power-down mode. See Figure 32 for the reset pad
configuration.
[3] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 31).
2 2 2 2 2
[4] I C-bus pin compliant with the I C-bus specification for I C standard mode, I C Fast-mode, and I C Fast-mode Plus. The pin requires an external
pull-up to provide output functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain
configuration applies to all functions on this pin.
[5] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis (see Figure 31); includes
high-current output driver.
[6] 5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors, configurable hysteresis, and analog input. When
configured as a ADC input, digital section of the pad is disabled and the pin is not 5 V tolerant (see Figure 31); includes digital input glitch
filter.
[7] Pad provides USB functions. It is designed in accordance with the USB specification, revision 2.0 (Full-speed and Low-speed mode only).
This pad is not 5 V tolerant.
[8] When the system oscillator is not used, connect XTALIN and XTALOUT as follows: XTALIN can be left floating or can be grounded
(grounding is preferred to reduce susceptibility to noise). Leave XTALOUT floating.
7. Functional description
7.1 On-chip flash programming memory

The LPC11U2x contain 24 kB or 32 kB on-chip flash program memory. The flash can be
programmed using In-System Programming (ISP) or In-Application Programming (IAP) via
the on-chip boot loader software.
7.2 EEPROM
The LPC11U2x contain 1 kB, 2 kB, or 4 kB of on-chip byte-erasable and
byte-programmable EEPROM data memory. The EEPROM can be programmed using In-
Application Programming (IAP) via the on-chip boot loader software.
7.3 SRAM
The LPC11U2x contain a total of 8 kB or 10 kB on-chip static RAM memory.
7.4 On-chip ROM

The on-chip ROM contains the boot loader and the following Application Programming
Interfaces (APIs):
• In-System Programming (ISP) and In-Application Programming (IAP) support for flash •
IAP support for EEPROM
• USB API
• Power profiles for configuring power consumption and PLL settings
• 32-bit integer division routines
7.5 Memory map

The LPC11U2x incorporates several distinct memory regions, shown in the following
figures. Figure 6 shows the overall map of the entire address space from the user
program viewpoint following reset. The interrupt vector area supports address remapping.
The AHB (Advanced High-performance Bus) peripheral area is 2 MB in size and is divided to
allow for up to 128 peripherals. The APB (Advanced Peripheral Bus) peripheral area is 512
kB in size and is divided to allow for up to 32 peripherals. Each peripheral of either type is
allocated 16 kB of space. This addressing scheme allows simplifying the address decoding
for each peripheral.

LPC11U2x
4 GB
0xFFFF FFFF
reserved
0xE010 0000
private peripheral bus
0xE000 0000
reserved
APB peripherals
0x4008 0000
0x5000 4000
GPIO
25 - 31 reserved
0x4006 4000
0x5000 0000
24 GPIO GROUP1 INT
0x4006 0000
reserved
23 GPIO GROUP0 INT
0x4005 C000
0x4008 4000
SSP1
22
USB
0x4005 8000
0x4008 0000
20 - 21 reserved
0x4004 C000
APB peripherals
0x4000 0000
1 GB
19 GPIO interrupts
0x4004 C000
reserved
system control
18
0x4004 8000
IOCON
17
0x4004 4000
0x2000 4800
SSP0
16
2 kB USB RAM
0x4004 0000
0x2000 4000
15
flash/EEPROM controller
reserved
0x4003 C000
0x2000 0000
0.5 GB
14
PMU
0x4003 8000
reserved
10 - 13 reserved
0x1FFF 4000
0x4002 8000
16 kB boot ROM
0x1FFF 0000
reserved
9
0x4002 4000
reserved
8
0x4002 0000
reserved
ADC
7
0x4001 C000
0x1000 2000
32-bit counter/timer 1
6
0x4001 8000
8 kB SRAM (LPC11U2x/401)
0x1000 1800
5
0x4001 4000
6 kB SRAM (LPC11U2x/301)
4
0x4001 0000
0x1000 0000
3
0x4000 C000
reserved
USART/SMART CARD
2
0x4000 8000
0x0000 8000
WWDT
1
0x4000 4000
32 kB on-chip flash (LPC11U24)
0x0000 6000
2
I C-bus
0
0x4000 0000
0x0000 4000 24 kB on-chip flash (LPC11U23)
0x0000 00C0
16 kB on-chip flash (LPC11U22)
active interrupt vectors
0x0000 0000
0 GB 0x0000 0000
002aag594
Fig 6. LPC11U2x memory map
7.6 Nested Vectored Interrupt Controller (NVIC)

The Nested Vectored Interrupt Controller (NVIC) is part of the Cortex-M0. The tight
coupling to the CPU allows for low interrupt latency and efficient processing of late arriving
interrupts.
7.6.1 Features
• Controls system exceptions and peripheral interrupts.

• In the LPC11U2x, the NVIC supports 24 vectored interrupts.

• Four programmable interrupt priority levels, with hardware priority level masking.
• Software interrupt generation.
7.6.2 Interrupt sources
Each peripheral device has one interrupt line connected to the NVIC but can have several
interrupt flags. Individual interrupt flags can also represent more than one interrupt
source.
7.7 IOCON block

The IOCON block allows selected pins of the microcontroller to have more than one function.
Configuration registers control the multiplexers to allow connection between the pin and the
on-chip peripherals.
Connect peripherals to the appropriate pins before activating the peripheral and before
enabling any related interrupt. Activity of any enabled peripheral function that is not
mapped to a related pin is treated as undefined.
7.7.1 Features
• Programmable pull-up, pull-down, or repeater mode.

• All GPIO pins (except PIO0_4 and PIO0_5) are pulled up to 3.3 V (VDD = 3.3 V) if their
pull-up resistor is enabled.
• Programmable pseudo open-drain mode.
• Programmable 10 ns glitch filter on pins PIO0_22, PIO0_23, and PIO0_11 to
PIO0_16. The glitch filter is turned on by default.
• Programmable hysteresis.
• Programmable input inverter.
7.8 General-Purpose Input/Output GPIO

The GPIO registers control device pin functions that are not connected to a specific
peripheral function. Pins can be dynamically configured as inputs or outputs. Multiple
outputs can be set or cleared in one write operation.
LPC11U2x use accelerated GPIO functions:
• GPIO registers are a dedicated AHB peripheral so that the fastest possible I/O timing can
be achieved.
• Entire port value can be written in one instruction.
Any GPIO pin providing a digital function can be programmed to generate an interrupt on a
level, a rising or falling edge, or both.
The GPIO block consists of three parts:
1. The GPIO ports.

2. The GPIO pin interrupt block to control eight GPIO pins selected as pin interrupts.
3. Two GPIO group interrupt blocks to control two combined interrupts from all GPIO
pins.

7.8.1 Features
• GPIO pins can be configured as input or output by software.
• All GPIO pins default to inputs with interrupt disabled at reset.
• Pin registers allow pins to be sensed and set individually.
• Up to eight GPIO pins can be selected from all GPIO pins to create an edge- or
level-sensitive GPIO interrupt request.
• Any pin or pins in each port can trigger a port interrupt.
7.9 USB interface

The Universal Serial Bus (USB) is a 4-wire bus that supports communication between a
host and one or more (up to 127) peripherals. The host controller allocates the USB
bandwidth to attached devices through a token-based protocol. The bus supports
hot-plugging and dynamic configuration of the devices. The host controller initiates all
transactions.
The LPC11U2x USB interface consists of a full-speed device controller with on-chip PHY
(PHYsical layer) for device functions.
Remark: Configure the LPC11U2x in default power mode with the power profiles before
using the USB (see Section 7.17.5.1). Do not use the USB with the part in performance,
efficiency, or low-power mode.
7.9.1 Full-speed USB device controller

The device controller enables 12 Mbit/s data exchange with a USB Host controller. It consists
of a register interface, serial interface engine, and endpoint buffer memory. The serial
interface engine decodes the USB data stream and writes data to the appropriate endpoint
buffer. The status of a completed USB transfer or error condition is indicated via status
registers. If enabled, an interrupt is generated.
7.9.1.1 Features
• Dedicated USB PLL available.

• Fully compliant with USB 2.0 specification (full speed).
• Supports 10 physical (5 logical) endpoints including one control endpoint.
• Single and double buffering supported.
• Each non-control endpoint supports bulk, interrupt, or isochronous endpoint types. •
Supports wake-up from Deep-sleep mode and Power-down mode on USB activity and
remote wake-up.
• Supports SoftConnect.
7.10 USART
The LPC11U2x contains one USART.
The USART includes full modem control, support for synchronous mode, and a smart
card interface. The RS-485/9-bit mode allows both software address detection and
automatic address detection using 9-bit mode.

The USART uses a fractional baud rate generator. Standard baud rates such as
115200 Bd can be achieved with any crystal frequency above 2 MHz.
7.10.1 Features
• Maximum USART data bit rate of 3.125 Mbit/s.
• 16 byte receive and transmit FIFOs.
• Register locations conform to 16C550 industry standard.
• Receiver FIFO trigger points at 1 B, 4 B, 8 B, and 14 B.
• Built-in fractional baud rate generator covering wide range of baud rates without a
need for external crystals of particular values.
• Fractional divider for baud rate control, auto baud capabilities and FIFO control
mechanism that enables software flow control implementation.
• Support for RS-485/9-bit mode.
• Support for modem control.
• Support for synchronous mode.
• Includes smart card interface.
7.11 SSP serial I/O controller

The SSP controllers operate on a SSP, 4-wire SSI, or Microwire bus. It can interact with
multiple masters and slaves on the bus. Only a single master and a single slave can
communicate on the bus during a given data transfer. The SSP supports full duplex
transfers, with frames of 4 bit to 16 bit of data flowing from the master to the slave and
from the slave to the master. In practice, often only one of these data flows carries
meaningful data.
7.11.1 Features
• Maximum SSP speed of 25 Mbit/s (master) or 4.17 Mbit/s (slave) (in SSP mode)
• Compatible with Motorola SPI (Serial Peripheral Interface), 4-wire Texas Instruments SSI
(Serial Synchronous Interface), and National Semiconductor Microwire buses
• Synchronous serial communication
• Master or slave operation
• 8-frame FIFOs for both transmit and receive
• 4-bit to 16-bit frame
7.12 I2C-bus serial I/O controller

2
The LPC11U2x contain one I C-bus controller.
2
The I C-bus is bidirectional for inter-IC control using only two wires: a Serial CLock line (SCL)
and a Serial DAta line (SDA). Each device is recognized by a unique address and can
operate as either a receiver-only device (e.g., an LCD driver) or a transmitter with the
capability to both receive and send information (such as memory). Transmitters and/or
receivers can operate in either master or slave mode, depending on whether the chip has to
2
initiate a data transfer or is only addressed. The I C-bus is a multi-master bus, and more than
one bus master connected to the interface can be controlled the bus.

7.12.1 Features
• The I2C-interface is an I2C-bus compliant interface with open-drain pins. The I2C-bus
interface supports Fast-mode Plus with bit rates up to 1 Mbit/s.
• Easy to configure as master, slave, or master/slave.
• Programmable clocks allow versatile rate control.
• Bidirectional data transfer between masters and slaves.
• Multi-master bus (no central master).
• Arbitration between simultaneously transmitting masters without corruption of serial data
on the bus.
• Serial clock synchronization allows devices with different bit rates to communicate via one
serial bus.
• Serial clock synchronization can be used as a handshake mechanism to suspend and
resume serial transfer.
• The I2C-bus can be used for test and diagnostic purposes.
• The I2C-bus controller supports multiple address recognition and a bus monitor mode.
7.13 10-bit ADC

The LPC11U2x contains one ADC. It is a single 10-bit successive approximation ADC with
eight channels.
7.13.1 Features
• 10-bit successive approximation ADC.
• Input multiplexing among 8 pins.
• Power-down mode.
• Measurement range 0 V to VDD.
• 10-bit conversion time ≥ 2.44 μs (up to 400 kSamples/s).
• Burst conversion mode for single or multiple inputs.
• Optional conversion on transition of input pin or timer match signal.
• Individual result registers for each ADC channel to reduce interrupt overhead.
7.14 General purpose external event counter/timers

The LPC11U2x includes two 32-bit counter/timers and two 16-bit counter/timers. The
counter/timer is designed to count cycles of the system derived clock. It can optionally
generate interrupts or perform other actions at specified timer values, based on four match
registers. Each counter/timer also includes one capture input to trap the timer value when an
input signal transitions, optionally generating an interrupt.
7.14.1 Features
• A 32-bit/16-bit timer/counter with a programmable 32-bit/16-bit prescaler.
• Counter or timer operation.
• One capture channel per timer, that can take a snapshot of the timer value when an
input signal transitions. A capture event can also generate an interrupt.

• Four match registers per timer that allow:
– Continuous operation with optional interrupt generation on match.
– Stop timer on match with optional interrupt generation.
– Reset timer on match with optional interrupt generation.
• Up to four external outputs corresponding to match registers, with the following
capabilities:
– Set LOW on match.
– Set HIGH on match.
– Toggle on match.
– Do nothing on match.
• The timer and prescaler can be configured to be cleared on a designated capture event.
This feature permits easy pulse-width measurement by clearing the timer on
the leading edge of an input pulse and capturing the timer value on the trailing edge.
7.15 System tick timer

The ARM Cortex-M0 includes a system tick timer (SYSTICK) that is intended to generate a
dedicated SYSTICK exception at a fixed time interval (typically 10 ms).
7.16 Windowed WatchDog Timer (WWDT)

The purpose of the WWDT is to prevent an unresponsive system state. If software fails to
update the watchdog within a programmable time window, the watchdog resets the
microcontroller
7.16.1 Features
• Internally resets chip if not periodically reloaded during the programmable time-out
period.
• Optional windowed operation requires reload to occur between a minimum and
maximum time period, both programmable.
• Optional warning interrupt can be generated at a programmable time before watchdog
time-out.
• Software enables the WWDT, but a hardware reset or a watchdog reset/interrupt is
required to disable the WWDT.
• Incorrect feed sequence causes reset or interrupt, if enabled.
• Flag to indicate watchdog reset.
• Programmable 24-bit timer with internal prescaler.
• Selectable time period from (Tcy(WDCLK) × 256 × 4) to (Tcy(WDCLK) × 224 × 4) in
multiples of Tcy(WDCLK) × 4.
• The Watchdog Clock (WDCLK) source can be selected from the IRC or the dedicated
watchdog oscillator (WDO). The clock source selection provides a wide range of
potential timing choices of watchdog operation under different power conditions.
7.17 Clocking and power control

7.17.1 Integrated oscillators
The LPC11U2x include three independent oscillators: the system oscillator, the Internal RC
oscillator (IRC), and the watchdog oscillator. Each oscillator can be used for more than one
purpose as required in a particular application.
Following reset, the LPC11U2x operates from the internal RC oscillator until software
switches to a different clock source. The IRC allows the system to operate without any
external crystal and the bootloader code to operate at a known frequency.
See Figure 7 for an overview of the LPC11U2x clock generation.


CPU, system control,
PMU
system clock
SYSTEM CLOCK
n
memories,
DIVIDER
peripheral clocks
SYSAHBCLKCTRLn
(AHB clock enable)
main clock IRC oscillator

SSP0 PERIPHERAL
CLOCK DIVIDER SSP0
watchdog oscillator
USART PERIPHERAL
CLOCK DIVIDER UART
MAINCLKSEL
(main clock select)
SSP1 PERIPHERAL
CLOCK DIVIDER SSP1
IRC oscillator
SYSTEM PLL
system oscillator
SYSPLLCLKSEL
(system PLL clock select)
USB PLL
system oscillator
USB 48 MHz CLOCK
DIVIDER USB
USBPLLCLKSEL
(USB clock select)
USBUEN
(USB clock update enable)
IRC oscillator
system oscillator CLKOUT PIN CLOCK
DIVIDER CLKOUT pin
watchdog oscillator
CLKOUTUEN
(CLKOUT update enable)
IRC oscillator
WDT
watchdog oscillator
WDCLKSEL
(WDT clock select)
002aaf892
Fig 7. LPC11U2x clocking generation block diagram
7.17.1.1 Internal RC oscillator

The IRC can be used as the clock source for the WDT, and/or as the clock that drives the
system PLL and then the CPU. The nominal IRC frequency is 12 MHz.
Upon power-up, any chip reset, or wake-up from Deep power-down mode, the LPC11U2x
use the IRC as the clock source. Software can later switch to one of the other available clock
sources.
7.17.1.2 System oscillator
The system oscillator can be used as the clock source for the CPU, with or without using the
PLL. On the LPC11U2x, use the system oscillator to provide the clock source to USB.
The system oscillator operates at frequencies of 1 MHz to 25 MHz. This frequency can be
boosted to a higher frequency, up to the maximum CPU operating frequency, by the system
PLL.
7.17.1.3 Watchdog oscillator

The watchdog oscillator can be used as a clock source that directly drives the CPU, the
watchdog timer, or the CLKOUT pin. The watchdog oscillator nominal frequency is
programmable between 7.8 kHz and 1.7 MHz. The frequency spread over processing and
temperature is ±40 % (see also Table 13).
7.17.2 System PLL and USB PLL

The LPC11U2x contain a system PLL and a dedicated PLL for generating the 48 MHz
USB clock. The system and USB PLLs are identical.
The PLL accepts an input clock frequency in the range of 10 MHz to 25 MHz. The input
frequency is multiplied up to a high frequency with a Current Controlled Oscillator (CCO). The
multiplier can be an integer value from 1 to 32. The CCO operates in the range of 156 MHz to
320 MHz. To support this frequency range, an additional divider keeps the CCO within its
frequency range while the PLL is providing the desired output frequency. The output divider
can be set to divide by 2, 4, 8, or 16 to produce the output clock. The PLL output frequency
must be lower than 100 MHz. Since the minimum output divider value is 2, it is insured that
the PLL output has a 50 % duty cycle. The PLL is turned off and bypassed following a chip
reset. Software can enable the PLL later. The program must configure and activate the PLL,
wait for the PLL to lock, and then connect to the PLL as a clock source. The PLL settling time
is 100 μs.
7.17.3 Clock output

The LPC11U2x feature a clock output function that routes the IRC oscillator, the system
oscillator, the watchdog oscillator, or the main clock to an output pin.
7.17.4 Wake-up process

The LPC11U2x begin operation by using the 12 MHz IRC oscillator as the clock source at
power-up and when awakened from Deep power-down mode. This mechanism allows chip
operation to resume quickly. If the application uses the main oscillator or the PLL, software
must enable these components and wait for them to stabilize. Only then can the system use
the PLL and main oscillator as a clock source.
7.17.5 Power control

The LPC11U2x support various power control features. There are four special modes of
processor power reduction: Sleep mode, Deep-sleep mode, Power-down mode, and Deep
power-down mode. The CPU clock rate can also be controlled as needed by
changing clock sources, reconfiguring PLL values, and/or altering the CPU clock divider
value. This power control mechanism allows a trade-off of power versus processing speed
based on application requirements. In addition, a register is provided for shutting down the
clocks to individual on-chip peripherals. This register allows fine-tuning of power

consumption by eliminating all dynamic power use in any peripherals that are not required for
the application. Selected peripherals have their own clock divider which provides even better
power control.
7.17.5.1 Power profiles

The power consumption in Active and Sleep modes can be optimized for the application
through simple calls to the power profile. The power configuration routine configures the
LPC11U2x for one of the following power modes:
• Default mode corresponding to power configuration after reset.

• CPU performance mode corresponding to optimized processing capability.
• Efficiency mode corresponding to optimized balance of current consumption and CPU
performance.
• Low-current mode corresponding to lowest power consumption.
In addition, the power profile includes routines to select the optimal PLL settings for a
given system clock and PLL input clock.
Remark: When using the USB, configure the LPC11U2x in Default mode.
7.17.5.2 Sleep mode

When Sleep mode is entered, the clock to the core is stopped. Resumption from the Sleep
mode does not need any special sequence but re-enabling the clock to the ARM core.
In Sleep mode, execution of instructions is suspended until either a reset or interrupt

occurs. Peripheral functions continue operation during Sleep mode and can generate
interrupts to cause the processor to resume execution. Sleep mode eliminates dynamic
power used by the processor itself, by memory systems and related controllers, and by
internal buses.
7.17.5.3 Deep-sleep mode

In Deep-sleep mode, the LPC11U2x is in Sleep-mode and all peripheral clocks and all clock
sources are off except for the IRC. The IRC output is disabled unless the IRC is selected as
input to the watchdog timer. In addition all analog blocks are shut down and the flash is in
stand-by mode. In Deep-sleep mode, the application can keep the watchdog oscillator and
the BOD circuit running for self-timed wake-up and BOD protection.
The LPC11U2x can wake up from Deep-sleep mode via reset, selected GPIO pins, a
watchdog timer interrupt, or an interrupt generating USB port activity.
Deep-sleep mode saves power and allows for short wake-up times.
7.17.5.4 Power-down mode

In Power-down mode, the LPC11U2x is in Sleep-mode and all peripheral clocks and all
clock sources are off except for watchdog oscillator if selected. In addition all analog blocks
and the flash are shut down. In Power-down mode, the application can keep the BOD
circuit running for BOD protection.
The LPC11U2x can wake up from Power-down mode via reset, selected GPIO pins, a
watchdog timer interrupt, or an interrupt generating USB port activity.

Power-down mode reduces power consumption compared to Deep-sleep mode at the
expense of longer wake-up times.
7.17.5.5 Deep power-down mode

In Deep power-down mode, power is shut off to the entire chip except for the WAKEUP pin.
The LPC11U2x can wake up from Deep power-down mode via the WAKEUP pin.
The LPC11U2x can be prevented from entering Deep power-down mode by setting a lock bit
in the PMU block. Locking out Deep power-down mode enables the application to keep the
watchdog timer or the BOD running at all times.
When entering Deep power-down mode, an external pull-up resistor is required on the
WAKEUP pin to hold it HIGH. Pull the RESET pin HIGH to prevent it from floating while in
Deep power-down mode.
7.17.6 System control
7.17.6.1 Reset
Reset has four sources on the LPC11U2x: the RESET pin, the Watchdog reset, power-on
reset (POR), and the BrownOut Detection (BOD) circuit. The RESET pin is a Schmitt trigger
input pin. Assertion of chip reset by any source, once the operating voltage attains a usable
level, starts the IRC and initializes the flash controller.
A LOW-going pulse as short as 50 ns resets the part.
When the internal Reset is removed, the processor begins executing at address 0, which is
initially the Reset vector mapped from the boot block. At that point, all of the processor and
peripheral registers have been initialized to predetermined values.
In Deep power-down mode, an external pull-up resistor is required on the RESET pin.
7.17.6.2 Brownout detection
The LPC11U2x includes four levels for monitoring the voltage on the VDD pin. If this
voltage falls below one of the four selected levels, the BOD asserts an interrupt signal to the
NVIC. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC to
cause a CPU interrupt. Alternatively, software can monitor the signal by reading a dedicated
status register. Four additional threshold levels can be selected to cause a forced reset of the
chip.
7.17.6.3 Code security (Code Read Protection - CRP)

CRP provides different levels of security in the system so that access to the on-chip flash and
use of the Serial Wire Debugger (SWD) and In-System Programming (ISP) can be restricted.
Programming a specific pattern into a dedicated flash location invokes CRP. IAP commands
are not affected by the CRP.
In addition, ISP entry via the PIO0_1 pin can be disabled without enabling CRP. For
details, see the LPC11Uxx user manual.
There are three levels of Code Read Protection:

1. CRP1 disables access to the chip via the SWD and allows partial flash update
(excluding flash sector 0) using a limited set of the ISP commands. This mode is
useful when CRP is required and flash field updates are needed but all sectors cannot be
erased.
2. CRP2 disables access to the chip via the SWD and only allows full flash erase and
update using a reduced set of the ISP commands.
3. Running an application with level CRP3 selected, fully disables any access to the chip via
the SWD pins and the ISP. This mode effectively disables ISP override using
PIO0_1 pin as well. If necessary, the application must provide a flash update
mechanism using IAP calls or using a call to the reinvoke ISP command to enable
flash update via the USART.
CAUTION
If level three Code Read Protection (CRP3) is selected, no future factory testing can be
performed on the device.
In addition to the three CRP levels, sampling of pin PIO0_1 for valid user code can be
disabled. For details, see the LPC11Uxx user manual.
7.17.6.4 APB interface

The APB peripherals are located on one APB bus.
7.17.6.5 AHBLite
The AHBLite connects the CPU bus of the ARM Cortex-M0 to the flash memory, the main
static RAM, and the ROM.
7.17.6.6 External interrupt inputs

All GPIO pins can be level or edge sensitive interrupt inputs.
7.18 Emulation and debugging

Debug functions are integrated into the ARM Cortex-M0. Serial wire debug functions are
supported in addition to a standard JTAG boundary scan. The ARM Cortex-M0 is
configured to support up to four breakpoints and two watch points.
The RESET pin selects between the JTAG boundary scan (RESET = LOW) and the ARM
SWD debug (RESET = HIGH). The ARM SWD debug port is disabled while the
LPC11U2x is in reset.
To perform boundary scan testing, follow these steps:
1. Erase any user code residing in flash.

2. Power up the part with the RESET pin pulled HIGH externally.
3. Wait for at least 250 μs.

4. Pull the RESET pin LOW externally.
5. Perform boundary scan operations.
6. Once the boundary scan operations are completed, assert the TRST pin to enable the
SWD debug mode, and release the RESET pin (pull HIGH).
Remark: The JTAG interface cannot be used for debug purposes.
8. Limiting values
Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). [1]
Symbol Parameter Conditions Min Max Unit
−0.5
supply voltage (core [2] +4.6 V
VDD
and external rail)
−0.5
input voltage [5][2] +5.5 V
VI
5 V tolerant digital I/O pins;
VDD ≥ 1.8 V
−0.5
VDD = 0 V +3.6 V
−0.5
[2][4] +5.5
5 V tolerant open-drain pins
PIO0_4 and PIO0_5
VIA analog input voltage pin configured as analog input [2][3] −0.5
4.6 V
IDD supply current per supply pin - 100 mA
ISS ground current per ground pin - 100 mA
−(0.5VDD) < VI < (1.5VDD);

Ilatch I/O latch-up current - 100 mA
Tj < 125 °C
non-operating [6] −65 °C

Tstg storage temperature +150
°C
Tj(max) maximum junction - 150
temperature
Ptot(pack) total power dissipation based on package heat - 1.5 W

(per package) transfer, not device power
consumption
VESD electrostatic human body model; all pins [7] - +6500 V

discharge voltage
[1] The following applies to the limiting values:

a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static
charge. Nonetheless, it is suggested that conventional precautions be taken to avoid applying greater than the rated maximum.
b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V SS unless
otherwise noted.
c) The limiting values are stress ratings only. Operating the part at these values is not recommended, and proper operation is not
guaranteed. The conditions for functional operation are specified in Table 5.
[2] Maximum/minimum voltage above the maximum operating voltage (see Table 5) and below ground that can be applied for a short time (< 10 ms)
to a device without leading to irrecoverable failure. Failure includes the loss of reliability and shorter lifetime of the device.
[3] See Table 6 for maximum operating voltage.
2
[4] VDD present or not present. Compliant with the I C-bus standard. 5.5 V can be applied to this pin when V DD is powered down. [5]
Including voltage on outputs in 3-state mode.
[6] The maximum non-operating storage temperature is different than the temperature for required shelf life which should be determined based on
required shelf lifetime. Please refer to the JEDEC spec (J-STD-033B.1) for further details.
[7] Human body model: equivalent to discharging a 100 pF capacitor through a 1.5 k Ω series resistor.
9. Static characteristics
Table 5. Static characteristics

Tamb = −40 °C to +85 °C, unless otherwise specified.
Symb Parameter Conditions Min Typ[1] Max Uni

ol t
supply voltage [2] 1.8 3.3 3.6 V

VDD
(core and
external rail)
IDD supply current Active mode; VDD = 3.3 V;
Tamb = 25 °C; code
while(1){}
executed from flash;
system clock = 12 MHz [3][4][5][6][7][8] - 2 - mA
system clock = 50 MHz [4][5][6][7][8][9] - 7 - mA
[3][4][5] - 1 - mA
Sleep mode;
[6][7][8]
VDD = 3.3 V; Tamb = 25 °C;

system clock = 12 MHz
[4][7] - 360 -
Deep-sleep mode; VDD = 3.3 V; μA
Tamb = 25 °C
Power-down mode; VDD = 3.3 V; - 2 -

μA
Tamb = 25 °C
[10] - 220 - nA
Deep power-down mode;
VDD = 3.3 V; Tamb = 25 °C
Standard port pins, RESET
IIL LOW-level input current I = 0 V; on-chip pull-up resistor - 0.5 10 nA

V disabled
IIH HIGH-level input VI = VDD; on-chip pull-down - 0.5 10 nA

current resistor disabled
IOZ OFF-state output VO = 0 V; VO = VDD; on-chip - 0.5 10 nA

current pull-up/down resistors disabled
input voltage [11][12] 0 - 5.0 V

VI
pin configured to provide a digital
[13]
function
VO output voltage output active 0 - VDD V
VIH HIGH-level input 0.7VDD - - V

voltage
VIL LOW-level input - - 0.3VDD V

voltage
Vhys hysteresis voltage - 0.4 - V
2.0 V ≤ VDD ≤ 3.6 V; IOH = −4 mA VDD −

VOH HIGH-level output - - V
voltage
0.4
1.8 V ≤ VDD < 2.0 V; IOH = −3 mA VDD −

- - V
0.4
VOL LOW-level output - - 0.4 V

2.0 V ≤ VDD ≤ 3.6 V; IOL = 4 mA
voltage
- - 0.4 V
1.8 V ≤ VDD < 2.0 V; IOL = 3 mA
VOH = VDD − 0.4 V; −4
IOH HIGH-level output - - mA
current
2.0 V ≤ VDD ≤ 3.6 V
−3
- - mA
1.8 V ≤ VDD < 2.0 V

Table 5. Static characteristics …continued

ol t
IOL LOW-level output VOL = 0.4 V 4 - - mA

current
2.0 V ≤ VDD ≤ 3.6 V
3 - - mA
1.8 V ≤ VDD < 2.0 V
VOH =0V [14] −45

IOHS HIGH-level short- - - mA
circuit output current
IOLS LOW-level short- VOL = VDD [14] - - 50 mA

circuit output
current
Ipd pull-down current VI =5V 10 50 150

μA
−15 −50 −85

Ipu pull-up current VI = 0 V; μA
2.0 V ≤ VDD ≤ 3.6 V
1.8 V ≤ VDD < 2.0 V −10 −50 −85 μA
VDD < VI <5V 0 0 0

μA
High-drive output pin (PIO0_7)
IIL LOW-level input current I = 0 V; on-chip pull-up resistor - 0.5 10 nA

V disabled
IIH HIGH-level input VI = VDD; on-chip pull-down - 0.5 10 nA

current resistor disabled
IOZ OFF-state output VO = 0 V; VO = VDD; on-chip - 0.5 10 nA

current pull-up/down resistors disabled
input voltage [11][12] 0 - 5.0 V

VI
pin configured to provide a digital
[13]
function
VO output voltage output active 0 - VDD V

voltage
voltage
Vhys hysteresis voltage 0.4 - - V
2.5 V ≤ VDD ≤ 3.6 V; IOH = −20 mA VDD −

VOH HIGH-level output - - V
voltage
0.4
1.8 V ≤ VDD < 2.5 V; IOH = −12 mA VDD −

- - V
0.4
VOL LOW-level output - - 0.4 V

2.0 V ≤ VDD ≤ 3.6 V; IOL = 4 mA
voltage
- - 0.4 V
1.8 V ≤ VDD < 2.0 V; IOL = 3 mA
VOH = VDD − 0.4 V;

IOH HIGH-level output 20 - - mA
current
2.5 V ≤ VDD ≤ 3.6 V
12 - - mA
1.8 V ≤ VDD < 2.5 V
IOL LOW-level output VOL = 0.4 V 4 - - mA

current
2.0 V ≤ VDD ≤ 3.6 V
3 - - mA
1.8 V ≤ VDD < 2.0 V
IOLS LOW-level short- VOL = VDD [14] - - 50 mA

circuit output
current
Ipd pull-down current VI =5V 10 50 150

μA
−15 −50 −85

Ipu pull-up current VI = 0 V μA
2.0 V ≤ VDD ≤ 3.6 V
1.8 V ≤ VDD < 2.0 V −10 −50 −85 μA
VDD < VI <5V 0 0 0

μA


ol t
I2C-bus pins (PIO0_4 and PIO0_5)

voltage

voltage
Vhys hysteresis voltage - - V

0.05VDD
IOL LOW-level output VOL = 0.4 V; I2C-bus pins 3.5 - - mA

current configured as standard mode
pins
2.0 V ≤ VDD ≤ 3.6 V
3 - -
1.8 V ≤ VDD < 2.0 V
IOL LOW-level output VOL = 0.4 V; I2C-bus pins 20 - - mA

current configured as Fast-mode Plus
pins
2.0 V ≤ VDD ≤ 3.6 V
16 - -
1.8 V ≤ VDD < 2.0 V
ILI input leakage current VI = VDD [15] - 2 4

μA
VI =5V - 10 22
μA
Oscillator pins
−0.5
Vi(xtal) crystal input voltage 1.8 1.95 V
−0.5
Vo(xtal) crystal output voltage 1.8 1.95 V
USB pins
IOZ OFF-state output 0V<VI < 3.3 V [2] - -

±10 μA
current
bus supply voltage [2] - - 5.25 V

VBUS
|(D+) − (D−)| [2]

VDI differential input 0.2 - - V
sensitivity voltage
VCM differential includes VDI range [2] 0.8 - 2.5 V

common mode
voltage range
single-ended [2] 0.8 - 2.0 V

Vth(rs)se
receiver switching
threshold voltage
LOW-level output [2] - - 0.18 V

VOL
voltage for low-/full-speed;
RL of 1.5 kΩ to 3.6 V
HIGH-level output [2] 2.8 - 3.5 V

VOH
voltage driven; for low-/full-speed;
RL of 15 kΩ to GND
Ctrans transceiver pin to GND [2] - - 20 pF

capacitance
driver output [16][2] 36 - 44.1

ZDRV Ω
impedance for driver with 33 Ω series resistor; steady
which is not high-
state drive
speed capable


ol t
Pin capacitance
Cio input/output pins configured for analog function - - 7.1 pF

capacitance
I2C-bus pins (PIO0_4 and PIO0_5) - - 2.5 pF
pins configured as GPIO - - 2.8 pF
[1] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply voltages. [2] For
USB operation 3.0 V ≤ VDD ≤ 3.6 V. Guaranteed by design.
[3] IRC enabled; system oscillator disabled; system PLL disabled.

[4] IDD measurements were performed with all pins configured as GPIO outputs driven LOW and pull-up resistors disabled. [5] BOD
disabled.
[6] All peripherals disabled in the AHBCLKCTRL register. Peripheral clocks to USART, SSP0/1 disabled in the SYSCON block. [7]
USB_DP and USB_DM pulled LOW externally.
[8] Low-current mode PWR_LOW_CURRENT selected when running the set_power routine in the power profiles. [9] IRC
disabled; system oscillator enabled; system PLL enabled.
[10] WAKEUP pin pulled HIGH externally. An external pull-up resistor is required on the RESET pin for the Deep power-down mode. [11]
Including voltage on outputs in 3-state mode.
[12] VDD supply voltage must be present.
[13] 3-state outputs go into 3-state mode in Deep power-down mode.
[14] Allowed as long as the current limit does not exceed the maximum current allowed by the device.
[15] To VSS.
[16] Includes external resistors of 33 Ω ± 1 % on USB_DP and USB_DM.

Table 6. ADC static characteristics

Tamb = −40 °C to +85 °C unless otherwise specified; ADC frequency 4.5 MHz, VDD = 2.5 V to 3.6 V.
Symbol Parameter Conditions Min Typ Max Unit
VIA analog input voltage 0 - VDD V
Cia analog input capacitance - - 1 pF
differential linearity error [1][2] - - LSB

ED ±1
integral non-linearity [3] - - LSB

EL(adj) ±1.5
offset error [4] - - LSB

EO ±3.5
gain error [5] - - 0.6 %

EG
absolute error [6] - - LSB

ET ±4
Rvsi voltage source - - 40

kΩ
interface resistance
input resistance [7][8] - - 2.5

Ri MΩ
[1] The ADC is monotonic, there are no missing codes.

[2] The differential linearity error (ED) is the difference between the actual step width and the ideal step width. See Figure 8. [3] The integral non-
linearity (EL(adj)) is the peak difference between the center of the steps of the actual and the ideal transfer curve after appropriate adjustment of
gain and offset errors. See Figure 8.
[4] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the straight line which fits the ideal
curve. See Figure 8.
[5] The gain error (EG) is the relative difference in percent between the straight line fitting the actual transfer curve after removing offset error, and
the straight line which fits the ideal transfer curve. See Figure 8.
[6] The absolute error (ET) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated ADC and
the ideal transfer curve. See Figure 8.
[7] Tamb = 25 °C; maximum sampling frequency fs = 400 kSamples/s and analog input capacitance Cia = 1 pF. [8]
Input resistance Ri depends on the sampling frequency fs: Ri = 1 / (fs × Cia).


offset
gain
error
error
EO
EG
1023
1022
1021
1020
1019
1018
(2)
7
code
(1)
out
6
5
(5)
4
(4)
3
(3)
2
1 LSB
1
(ideal)
0
123456 7 1018 1019 1020 1021 1022 1023 1024
VIA (LSBideal)
offset error
EO
VDD − VSS
1 LSB =
1024
002aaf426
(1) Example of an actual transfer curve.

(2) The ideal transfer curve.
(3) Differential linearity error (ED).
(4) Integral non-linearity (EL(adj)).
(5) Center of a step of the actual transfer curve.
Fig 8. ADC characteristics
9.1 BOD static characteristics

Table 7. BOD static characteristics[1]
Tamb = 25 °C.
Symbo Parameter Conditions Min Typ Max Unit

l
Vth threshold voltage interrupt level 1
assertion - 2.22 - V
de-assertion - 2.35 - V
interrupt level 2
interrupt level 3
reset level 0
reset level 1
reset level 2
reset level 3
[1] Interrupt levels are selected by writing the level value to the BOD control register BODCTRL, see the
LPC11Uxx user manual.
9.2 Power consumption

Power measurements in Active, Sleep, and Deep-sleep modes were performed under the
following conditions (see the LPC11Uxx user manual):
• Configure all pins as GPIO with pull-up resistor disabled in the IOCON block.
• Configure GPIO pins as outputs using the GPIOnDIR registers.
• Write 0 to all GPIOnDATA registers to drive the outputs LOW.

002aag749
9
(2)
48 MHz
IDD
(mA)
6
(2)
36 MHz
(2)
24 MHz
3
(1)
12 MHz
0
1.8 2.4 3.0 3.6 VDD (V)
Conditions: Tamb = 25 °C; Active mode entered executing code while(1){} from flash;
internal pull-up resistors disabled; BOD disabled; all peripherals disabled in the
SYSAHBCLKCTRL register; all peripheral clocks disabled; low-current mode; USB_DP and
USB_DM pulled LOW externally.
(1) System oscillator and system PLL disabled; IRC enabled.
(2) System oscillator and system PLL enabled; IRC disabled.
Fig 9. Typical supply current versus regulator supply voltage V DD in active mode
002aag750
9
(2)
48 MHz
IDD
(mA)
6
(2)
36 MHz
(2)
24 MHz
3
(1)
12 MHz
0
-40 -15 10 60 35 85 temperature (°C)
Conditions: VDD = 3.3 V; Active mode entered executing code while(1){} from flash; internal
pull-up resistors disabled; BOD disabled; all peripherals disabled in the SYSAHBCLKCTRL
register; all peripheral clocks disabled; low-current mode; USB_DP and USB_DM pulled LOW
externally.
Fig 10. Typical supply current versus temperature in Active mode

002aag751
4
IDD
(mA)
3
(2)
48 MHz
(2)
36 MHz
2
(2)
24 MHz
(1)
12 MHz
1
0
-40 -15 10 60 35 85 temperature (°C)
Conditions: VDD = 3.3 V; Sleep mode entered from flash; internal pull-up resistors disabled; BOD
disabled; all peripherals disabled in the SYSAHBCLKCTRL register; all peripheral clocks disabled;
low-current mode; USB_DP and USB_DM pulled LOW externally.
Fig 11. Typical supply current versus temperature in Sleep mode
002aag745
385
IDD
(μA)
375
VDD = 3.6 V
VDD = 3.3 V
365
VDD = 2.0 V
355
VDD = 1.8 V
345
-40 -15 10 60 35 85 temperature (°C)
Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG
register; USB_DP and USB_DM pulled LOW externally.
Fig 12. Typical supply current versus temperature in Deep-sleep mode

002aag746
20
IDD
VDD = 3.6 V, 3.3 V
(μA)
VDD = 2.0 V
VDD = 1.8 V
15
10
0
-40 -15 10 60 35 85 temperature (°C)
Conditions: BOD disabled; all oscillators and analog blocks turned off in the PDSLEEPCFG
register; USB_DP and USB_DM pulled LOW externally.
Fig 13. Typical supply current versus temperature in Power-down mode
002aag747
0.8
VDD = 3.6 V
IDD
(μA)
VDD = 3.3 V
VDD = 2.0 V
0.6
VDD = 1.8 V
0.4
0.2
0
-40 -15 10 60 35 85 temperature (°C)
Fig 14. Typical supply current versus temperature in Deep power-down mode
9.3 Peripheral power consumption

The supply current per peripheral is measured as the difference in supply current between
the peripheral block enabled and the peripheral block disabled in the SYSAHBCLKCFG and
PDRUNCFG (for analog blocks) registers. All other blocks are disabled in both
registers and no code is executed. Measured on a typical sample at Tamb = 25 °C. Unless
noted otherwise, the system oscillator and PLL are running in both measurements.
The supply currents are shown for system clock frequencies of 12 MHz and 48 MHz.

Table 8. Power consumption for individual analog and digital blocks
Peripheral Typical supply current Notes
in mA
n/a 12 48
MHz MHz
IRC 0.27 - - System oscillator running; PLL off;

independent of main clock frequency.
System 0.22 - - IRC running; PLL off; independent of main

oscillator at clock frequency.
12 MHz
Watchdog 0.004 - - System oscillator running; PLL off;

oscillator at independent of main clock frequency.
500 kHz/2
BOD 0.051 - - Independent of main clock frequency.
Main PLL - 0.21 - -
ADC - 0.08 0.29 -
CLKOUT - 0.12 0.47 Main clock divided by 4 in the

CLKOUTDIV register.
CT16B0 - 0.02 0.06 -
CT16B1 - 0.02 0.06 -
CT32B0 - 0.02 0.07 -
CT32B1 - 0.02 0.06 -
GPIO - 0.23 0.88 GPIO pins configured as outputs and set to

LOW. Direction and pin state are
maintained if the GPIO is disabled in the
SYSAHBCLKCFG register.
IOCONFIG - 0.03 0.10 -
I2C - 0.04 0.13 -
ROM - 0.04 0.15 -
SPI0 - 0.12 0.45 -
SPI1 - 0.12 0.45 -
UART - 0.22 0.82 -
WWDT - 0.02 0.06 Main clock selected as clock source for

the WDT.
USB - - 1.2 -
9.4 Electrical pin characteristics

002aae990
3.6
VOH
T = 85 °C
(V)
25 °C
−40 °C
3.2
2.8
2.4
2
0 10 50 20 30 40 60
IOH (mA)
Conditions: VDD = 3.3 V; on pin PIO0_7.

Fig 15. High-drive output: Typical HIGH-level output voltage V OH versus HIGH-
level output current IOH.
002aaf019
60
T = 85 °C
IOL
(mA)
25 °C
−40 °C
40
20
0
0 0.2 0.4 0.6
VOL (V)
Conditions: VDD = 3.3 V; on pins PIO0_4 and PIO0_5.

2
Fig 16. I C-bus pins (high current sink): Typical LOW-level output current I OL
versus LOW-level output voltage VOL

002aae991
15
IOL
T = 85 °C
(mA)
25 °C
−40 °C
10
0
0 0.2 0.4 0.6
VOL (V)
Conditions: VDD = 3.3 V; standard port pins and PIO0_7.
Fig 17. Typical LOW-level output current I OL versus LOW-level output voltage VOL
002aae992
3.6
VOH
(V)
T = 85 °C
3.2
25 °C
−40 °C
2.8
2.4
2
0 8 16 24
IOH (mA)
Conditions: VDD = 3.3 V; standard port pins.

Fig 18. Typical HIGH-level output voltage V OH versus HIGH-level output source
current IOH

002aae988
10
Ipu
(μA)
−10
−30
T = 85 °C
25 °C
−40 °C
−50
−70
012345
VI (V)
Fig 19. Typical pull-up current Ipu versus input voltage VI
002aae989
80
T = 85 °C
Ipd
25 °C
(μA)
−40 °C
60
40
20
0
012345
VI (V)
Fig 20. Typical pull-down current Ipd versus input voltage VI
10. Dynamic characteristics
10.1 Flash memory

Table 9. Flash characteristics
endurance [1] 1000 - cycl

Nendu
0 100000 es
tret retention time powered 10 - -

year
s
unpowered 20 - -
year
s
ter erase time sector or multiple 95 100 105 ms

consecutive sectors
programming [2] 0.95 1 1.05 ms

tprog
time
[1] Number of program/erase cycles.

[2] Programming times are given for writing 256 bytes from RAM to the flash. Data must be written to the flash in
blocks of 256 bytes.
Table 10. EEPROM characteristics

Tamb = −40 °C to +85 °C; VDD = 2.7 V to 3.6 V. Based on JEDEC NVM qualification. Failure rate <
10 ppm for parts as specified below.
Nendu endurance 100000 1000000 -

cycles
tret retention time powered 100 200 - years
unpowered 150 300 - years
tprog programming 64 bytes - 2.9 - ms

time
10.2 External clock

Table 11. Dynamic characteristic: external clock
Tamb = −40 °C to +85 °C; VDD over specified ranges.[1]
Symb Parameter Conditions Min Typ[2] Max Unit

ol
fosc oscillator frequency 1 - 25

MHz
Tcy(clk) clock cycle time 40 - 1000 ns
Tcy(clk) × 0.4
tCHCX clock HIGH time - - ns
Tcy(clk) × 0.4
tCLCX clock LOW time - - ns
tCLCH clock rise time - - 5 ns
tCHCL clock fall time - - 5 ns

[1] Parameters are valid over operating temperature range unless otherwise specified.
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply
voltages.

tCHCX
tCHCL tCLCX
tCLCH
Tcy(clk)
002aaa907
Fig 21. External clock timing (with an amplitude of at least V i(RMS) = 200 mV)
10.3 Internal oscillators

Table 12. Dynamic characteristics: IRC
Tamb = −40 °C to +85 °C; 2.7 V ≤ VDD ≤ 3.6 V[1].
Symbol Parameter Conditions Min Typ[2] Max Unit
fosc(RC) internal RC oscillator - 11.88 12 12.12

frequency MHz
[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 °C), nominal supply
voltages.
002aaf403
12.15
f
(MHz)
VDD = 3.6 V
3.3 V
3.0 V
12.05
2.7 V
2.4 V
2.0 V
11.95
11.85
−40 −15 10 60 35 85 temperature (°C)
Conditions: Frequency values are typical values. 12 MHz ± 1 % accuracy is guaranteed for 2.7 V ≤
VDD ≤ 3.6 V and Tamb = −40 °C to +85 °C. Variations between parts may cause the IRC to fall
outside the 12 MHz ± 1 % accuracy specification for voltages below 2.7 V.
Fig 22. Internal RC oscillator frequency versus temperature
Table 13. Dynamic characteristics: Watchdog oscillator

Symbol Parameter Conditions Mi Typ[ Ma Un
n 1] x it
internal [2][3] - 7.8 -

fosc(int)
oscillator DIVSEL = 0x1F, FREQSEL = kH
frequency 0x1 in the WDTOSCCTRL z
register;
[2][3] - -
DIVSEL = 0x00, FREQSEL = 170 kH
0xF in the WDTOSCCTRL 0 z
register
[1] Typical ratings are not guaranteed. The values listed are at nominal supply voltages.
[2] The typical frequency spread over processing and temperature (T amb = −40 °C to +85 °C) is ±40 %.
[3] See the LPC11Uxx user manual.
10.4 I/O pins

Table 14. Dynamic characteristics: I/O pins[1]
Tamb = −40 °C to +85 °C; 3.0 V ≤ VDD ≤ 3.6 V.
Symbol Paramete Conditions Min Typ Max Unit

r
tr rise time pin configured as output 3.0 - 5.0 ns
tf fall time pin configured as output 2.5 - 5.0 ns
[1] Applies to standard port pins and RESET pin.
10.5 I2C-bus
Table 15. Dynamic characteristic: I2C-bus pins[1]
Tamb = −40 °C to +85 °C.[2]
Symbol Parameter Conditions Min Max Unit
fSCL SCL clock Standard-mode 0 100 kHz

frequency
Fast-mode 0 400 kHz
Fast-mode Plus 0 1 MHz
tf fall time [3][4][5][6] of both SDA and - 300 ns

SCL signals
Standard-mode
20 + 0.1 × Cb
Fast-mode 300 ns
Fast-mode Plus - 120 ns
tLOW LOW period of the Standard-mode 4.7 -

μs
SCL clock
Fast-mode 1.3 -
μs
Fast-mode Plus 0.5 -

μs
tHIGH HIGH period of the Standard-mode 4.0 -

μs
SCL clock
Fast-mode 0.6 -
μs
Fast-mode Plus 0.26 -

μs
tHD;DAT data hold time [3][7][8] Standard-mode 0 -

μs
Fast-mode 0 -
μs
Fast-mode Plus 0 -
μs
tSU;DAT data set-up time [9][10] Standard-mode 250 - ns
Fast-mode 100 - ns
Fast-mode Plus 50 - ns
2
[1] See the I C-bus specification UM10204 for details.
[3] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V IH(min) of the SCL signal) to bridge the
undefined region of the falling edge of SCL.
[4] Cb = total capacitance of one bus line in pF.

[5] The maximum tf for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t f is specified at 250 ns.
This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA/SCL bus lines without exceeding
the maximum specified tf.
[6] In Fast-mode Plus, fall time is specified the same for both output stage and bus timing. If series resistors are used, designers should allow for
this when considering bus timing.
[7] The maximum tHD;DAT could be 3.45 μs and 0.9 μs for Standard-mode and Fast-mode but must be less than the maximum of t VD;DAT or tVD;ACK
by a transition time (see UM10204). This maximum must only be met if the device does not stretch the LOW period (t LOW) of the SCL signal. If
the clock stretches the SCL, the data must be valid by the set-up time before it releases the clock.
[8] tHD;DAT is the data hold time that is measured from the falling edge of SCL; applies to data in transmission and the acknowledge.
[9] tSU;DAT is the data set-up time that is measured with respect to the rising edge of SCL; applies to data in transmission and the
acknowledge.
2 2
[10] A Fast-mode I C-bus device can be used in a Standard-mode I C-bus system but the requirement tSU;DAT = 250 ns must then be met. This will
automatically be the case if the device does not stretch the LOW period of the SCL signal. If such a device does stretch the LOW period of the SCL
2
signal, it must output the next data bit to the SDA line t r(max) + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-mode I C-bus
specification) before the SCL line is released. Also the acknowledge timing must meet this set-up time.
tf
tSU;DAT
70 %
70 %
30 % SDA
30 %
tHD;DAT
tVD;DAT
tf
tHIGH
70 %
70 %
70 %
70 %
SCL
30 %
30 %
30 %
30 %
tLOW
S
1 / fSCL
002aaf425
Fig 23. I2C-bus pins clock timing
10.6 SSP interface

Table 16. Dynamic characteristics of SPI pins in SPI mode
Symbol Parameter Conditions Min Typ Max Un
it
SPI master (in SPI mode)
Tcy(clk) clock cycle time full-duplex mode [1] 50 - - ns
when only transmitting [1] 40 ns
data set-up time [2] 15 - - ns

tDS
in SPI mode
2.4 V ≤ VDD ≤ 3.6 V
20 ns
2.0 V ≤ VDD < 2.4 V [2]
24 - - ns
1.8 V ≤ VDD < 2.0 V [2]
tDH data hold time in SPI mode [2] 0 - - ns
tv(Q) data output valid in SPI mode [2] - - 10 ns

time
th(Q) data output hold in SPI mode [2] 0 - - ns

time
SPI slave (in SPI mode)

Tcy(PCLK) PCLK cycle time 20 - - ns
tDS data set-up time in SPI mode [3][4] 0 - - ns
in SPI mode [3][4] 3 × Tcy(PCLK) + 4

tDH data hold time - - ns

tv(Q) data output valid - - ns
time

th(Q) data output hold - - ns
time
[1] Tcy(clk) = (SSPCLKDIV × (1 + SCR) × CPSDVSR) / fmain. The clock cycle time derived from the SPI bit rate T cy(clk) is a function of the main clock
frequency fmain, the SPI peripheral clock divider (SSPCLKDIV), the SPI SCR parameter (specified in the SSP0CR0 register), and the SPI
CPSDVSR parameter (specified in the SPI clock prescale register).
[2] Tamb = −40 °C to 85 °C.
[3] Tcy(clk) = 12 × Tcy(PCLK).
[4] Tamb = 25 °C; for normal voltage supply range: VDD = 3.3 V.

Tcy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)
tv(Q)
th(Q)
DATA VALID DATA VALID
MOSI
CPHA = 1
tDS tDH

MISO
tv(Q)
th(Q)
MOSI
CPHA = 0
tDS tDH

MISO
002aae829
Fig 24. SSP master timing in SPI mode

Tcy(clk)
SCK (CPOL = 0)
SCK (CPOL = 1)
tDS tDH
MOSI
tv(Q)
th(Q)
CPHA = 1
MISO
tDS tDH
MOSI
CPHA = 0
tv(Q)
th(Q)
MISO
002aae830
Fig 25. SSP slave timing in SPI mode
10.7 USB interface

Table 17. Dynamic characteristics: USB pins (full-speed)
CL = 50 pF; Rpu = 1.5 kΩ on D+ to VDD; 3.0 V ≤ VDD ≤ 3.6 V.
tr rise time 10 % to 90 % 8.5 - 13.8 ns
tf fall time 10 % to 90 % 7.7 - 13.7 ns
tFRFM differential rise and fall time tr / t f - - 109 %

matching
VCRS output signal crossover voltage 1.3 - 2.0 V
tFEOPT source SE0 interval of EOP see Figure 26 160 - 175 ns
−2
tFDEOP source jitter for differential see Figure 26 - +5 ns
transition to SE0 transition
−18.5
tJR1 receiver jitter to next transition - +18.5 ns
−9
tJR2 receiver jitter for paired transitions 10 % to 90 % - +9 ns
EOP width at receiver [1] 82 - - ns

tEOPR
must accept as
EOP; see
Figure 26
[1] Characterized but not implemented as production test. Guaranteed by design.
TPERIOD
crossover point
extended
crossover point
differential
data lines
source EOP width: tFEOPT

differential data to
SE0/EOP skew
n TPERIOD + tFDEOP
receiver EOP width: tEOPR
aaa-009330
Fig 26. Differential data-to-EOP transition skew and EOP width
11. Application information
11.1 Suggested USB interface solutions

The USB device can be connected to the USB as self-powered device (see Figure 27) or
bus-powered device (see Figure 28).
On the LPC11U2x, the PIO0_3/USB_VBUS pin is 5 V tolerant only when V DD is applied and
at operating voltage level. Therefore, if the USB_VBUS function is connected to the USB
connector and the device is self-powered, the USB_VBUS pin must be protected for
situations when VDD = 0 V.
If VDD is always at operating level while VBUS = 5 V, the USB_VBUS pin can be
connected directly to the VBUS pin on the USB connector.
For systems where VDD can be 0 V and VBUS is directly applied to the VBUS pin,
precautions must be taken to reduce the voltage to below 3.6 V, which is the maximum
allowable voltage on the USB_VBUS pin in this case.
One method is to use a voltage divider to connect the USB_VBUS pin to the VBUS on the
USB connector. The voltage divider ratio should be such that the USB_VBUS pin will be
greater than 0.7VDD to indicate a logic HIGH while below the 3.6 V allowable maximum
voltage.
For the following operating conditions
VBUSmax = 5.25 V
VDD = 3.6 V,
the voltage divider should provide a reduction of 3.6 V/5.25 V or ~0.686 V.

VDD
USB_CONNECT
soft-connect switch
R1
1.5 kΩ
LPC1xxx
R2
R3
USB_VBUS
R
S = 33 Ω
USB-B
USB_DP
connector
R
S = 33 Ω
USB_DM
VSS
aaa-010178
Fig 27. USB interface on a self-powered device where USB_VBUS = 5 V

For a bus-powered device, the VBUS signal does not need to be connected to the
USB_VBUS pin (see Figure 28). The USB_CONNECT function can additionally be
connected as shown in Figure 27 to prevent the USB from timing out when there is a
significant delay between power-up and handling USB traffic.
VDD
REGULATOR
LPC1xxx
R1
1.5 kΩ
VBUS
USB-B
R
S = 33 Ω
connector USB_DP
R
S = 33 Ω
USB_DM
VSS
aaa-010179
Fig 28. USB interface on a bus-powered device
Remark: When a bus-powered circuit as shown in Figure 28 is used, configure the

PIO0_3/USB_VBUS pin for GPIO (PIO0_3) in the IOCON block to ensure that the
USB_CONNECT signal can still be controlled by software. For details on the soft-connect
feature, see the LPC11U2x user manual (Ref. 1).
Remark: When a self-powered circuit is used without connecting VBUS, configure the
PIO0_3/USB_VBUS pin for GPIO (PIO0_3) and provide software that can detect the host
presence through some other mechanism before enabling USB_CONNECT and the soft-
connect feature. Enabling the soft-connect without host presence will lead to USB
compliance failure.
11.2 XTAL input

The input voltage to the on-chip oscillators is limited to 1.8 V. If the oscillator is driven by a
clock in slave mode, it is recommended that the input be coupled through a capacitor with C i
= 100 pF. To limit the input voltage to the specified range, choose an additional
capacitor to ground Cg which attenuates the input voltage by a factor Ci/(Ci + Cg). In slave
mode, a minimum of 200 mV (RMS) is needed.

LPC1xxx
XTALIN
C
i
C
g
100 pF
002aae788
Fig 29. Slave mode operation of the on-chip oscillator
In slave mode, couple the input clock signal with a capacitor of 100 pF (Figure 29), with an
amplitude between 200 mV (RMS) and 1000 mV (RMS). This signal corresponds to a square
wave signal with a signal swing of between 280 mV and 1.4 V. The XTALOUT pin in this
configuration can be left unconnected.
External components and models used in oscillation mode are shown in Figure 30 and in
Table 18 and Table 19. Since the feedback resistance is integrated on chip, only a crystal
and the capacitances CX1 and CX2 need to be connected externally in case of
fundamental mode oscillation (L, CL and RS represent the fundamental frequency).
Capacitance CP in Figure 30 represents the parallel package capacitance and must not be
larger than 7 pF. Parameters FOSC, CL, RS and CP are supplied by the crystal
manufacturer.
LPC1xxx
L
XTALIN XTALOUT
C C
= L P
XTAL
R
S
C C
X1 X2
002aaf424
Fig 30. Oscillator modes and models: oscillation mode of operation and external
crystal model used for CX1/CX2 evaluation
Table 18. Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters) low frequency mode
Fundamental Crystal load Maximum crystal External load
oscillation frequency capacitance CL series resistance RS capacitors CX1, CX2
FOSC
1 MHz to 5 MHz 10 pF 18 pF, 18 pF

< 300 Ω
20 pF 39 pF, 39 pF
< 300 Ω
30 pF 57 pF, 57 pF
< 300 Ω

< 300 Ω
20 pF 39 pF, 39 pF
< 200 Ω
30 pF 57 pF, 57 pF
< 100 Ω

< 160 Ω
20 pF 39 pF, 39 pF
< 60 Ω

< 80 Ω
Table 19. Recommended values for CX1/CX2 in oscillation mode (crystal and external
components parameters) high frequency mode
Fundamental Crystal load Maximum crystal External load
oscillation frequency capacitance CL series resistance RS capacitors CX1, CX2
FOSC

< 180 Ω
20 pF 39 pF, 39 pF
< 100 Ω

< 160 Ω
20 pF 39 pF, 39 pF
< 80 Ω
11.3 XTAL Printed-Circuit Board (PCB) layout guidelines

Follow these guidelines for PCB layout:
• Connect the crystal on the PCB as close as possible to the oscillator input and output pins
of the chip.
• Take care that the load capacitors Cx1, Cx2, and Cx3 in case of third overtone crystal use
have a common ground plane.
• Connect the external components to the ground plain.
• To keep parasitics and the noise coupled in via the PCB as small as possible, keep
loops as small as possible.
• Choose smaller values of Cx1 and Cx2 if parasitics of the PCB layout increase.
11.4 Standard I/O pad configuration

Figure 31 shows the possible pin modes for standard I/O pins with analog input function:
• Digital output driver

• Digital input: Pull-up enabled/disabled
• Digital input: Pull-down enabled/disabled
• Digital input: Repeater mode enabled/disabled
• Analog input
VDD
ESD
output enable
pin configured
as digital output
output
PIN
driver
ESD
VDD
VSS
weak
pull-up
pull-up enable
weak
repeater mode
pull-down
pin configured
enable
as digital input
pull-down enable
data input
select analog input

pin configured
analog input
002aaf304
as analog input
Fig 31. Standard I/O pad configuration
11.5 Reset pad configuration

VDD
VDD
VDD
Rpu
ESD
20 ns RC
reset
GLITCH FILTER PIN
ESD
VSS
002aaf274
Fig 32. Reset pad configuration
11.6 ADC effective input impedance

A simplified diagram of the ADC input channels can be used to determine the effective
input impedance seen from an external voltage source. See Figure 33.
ADC Block
Source
R R
mux sw
R
s
ADC
COMPARATOR
<2 kΩ <1.3 kΩ
R
in
C
ia
V
EXT
C
io
VSS
002aah615
Fig 33. ADC input channel
The effective input impedance, Rin, seen by the external voltage source, VEXT, is the
parallel impedance of ((1/fs x Cia) + Rmux + Rsw) and (1/fs x Cio), and can be calculated
using Equation 1 with
fs = sampling frequency
Cia = ADC analog input capacitance
Rmux = analog mux resistance
Rsw = switch resistance
Cio = pin capacitance
++
fs Cia × ----------------- Rmux Rsw ⎝⎠⎛⎞1
Rin1
(1)
----------------- ⎛⎞
fs Cio × ⎝⎠ = ||
Under nominal operating condition VDD = 3.3 V and with the maximum sampling
frequency fs = 400 kHz, the parameters assume the following values:
Cia = 1 pF (max)
Rmux = 2 kΩ (max)
Rsw = 1.3 kΩ (max)
Cio = 7.1 pF (max)
The effective input impedance with these parameters is Rin = 308 kΩ.
11.7 ADC usage notes

The following guidelines show how to increase the performance of the ADC in a noisy
environment beyond the ADC specifications listed in Table 6:
• The ADC input trace must be short and as close as possible to the LPC11U2x chip. •
Shield The ADC input traces from fast switching digital signals and noisy power
supply lines.
• The ADC and the digital core share the same power supply. Therefore, filter the power
supply line adequately.
• To improve the ADC performance in a noisy environment, put the device in Sleep
mode during the ADC conversion.

12. Package outline
HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
33 terminals; body 7 x 7 x 0.85 mm
DBA
terminal 1
index area
e1 v AC B detail X C
A
e A1 y1 C y
b
E
c
L 33 e2
1
wC
24
17
Eh e
9 16 8
terminal 1 32 25 X
index area Dimensions
Dh
0 2.5 5 mm scale
Unit (1) (1) (1) Lv w y

A A1 b cD Dh E Eh e e 1 e2 y1
mm
Note
max nom min
1.00 0.85 0.80
0.05 0.02 0.00
0.35 0.28 0.23
0.2
7.1 7.0 6.9
4.85 4.70 4.55
7.1 7.0 6.9
4.85 4.70 4.55
0.65 4.55
4.55
0.75 0.60 0.45
0.1
0.05
0.08
0.1
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. hvqfn33_po
Outline version
References
---
European
IEC JEDEC
projection Issue date
09-03-17
09-03-23
Fig 34. Package outline HVQFN33 (7 x 7 x 0.85 mm)
HVQFN33: plastic thermal enhanced very thin quad flat package; no leads;
32 terminals; body 5 x 5 x 0.85 mm
terminal 1 index area e AA c C

D 1 1
BAE
detail X
y C
y 1 e
1/2 e
b
v AC B
L E
h 8 17 e
9 16 e
wC 2
terminal 1 index area X 24

1 1/2 e
32 25
D 0 2.5 5 mm scale
h
(1)
Unit
(1) (1) (1)
A D Dh E Eh e e1 e2 L
Dimensions (mm are the original dimensions)
max A1 0.05 5.1 3.75 3.75 0.5 y 0.05 y1
b c 0.30 5.1 v w 0.05
mm Note 0.85 0.00 0.18 0.2 4.9 3.45 4.9 3.45 0.5 3.5 3.5 0.3 0.1 0.1 hvqfn33f_po
nom min
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
Outline version
References
IEC JEDEC
MO-220
European
11-10-11
11-10-17
Fig 35. Package outline HVQFN33 (5 x 5 x 0.85 mm)
LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm SOT313-2
c
y
X
37 A Z
E
36 25 24
48 pin 1 index wM 12 bp vMB

θ
bp
E
1 D Z Lp
D
B EH L
DH 13
e
e detail X
(A ) 3 A2 A1 A
vMA
wM
0 2.5 5 mm scale
DIMENSIONS (mm are the original dimensions) UNITA
(1) (1) (1)(1)

max. A1 A2 A3 bp c E e HE L Lp ywv Z θ D
1.45 0.18 7.1 D o

mm 1.6 0.20
1.35 0.25 0.27 HD ZE 0.95
7.1 0.75 0.95 7
6.9 0.5 9.15 9.15
1 0.2 0.12 0.1 o
Note 0.05 0.17 0.12 6.9 8.85 8.85 0.45 0.55 0.55 0
EUROPEAN
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE
REFERENCES
VERSION
PROJECTION ISSUE DATE
IEC JEDEC
SOT313-2 MS-026 136E05 00-01-19 03-02-25
Fig 36. Package outline LQFP48 (SOT313-2)
LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2
c
y
X
48 33
49 e wM 16 B vMA Lp
bp L
D Z
D
32 detail X
Z
E
E
EH A2
A
e (A ) 3
64
pin 1 index
1 θ
wM
17 A1
bp
DH DIMENSIONS (mm are the original dimensions) UNIT A

vMB
0 2.5 5 mm scale
(1) (1) (1)(1)

max. A1 A2 A3 bp c E e HE L Lp ywv Z θ D
0.18 10.1 D
mm 1.6 0.20 1.35 0.25 0.27 1.45 o
HD ZE
10.1 0.75 1.45 1.45 7
9.9 0.5 12.15 12.15
0.05 0.17 0.12 11.85
1 0.2 0.12 0.1 o
Note 9.9 11.85 0.45 1.05 1.05 0
EUROPEAN
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE
REFERENCES
VERSION
PROJECTION ISSUE DATE
IEC JEDEC
SOT314-2 MS-026 136E10 00-01-19 03-02-25
Fig 37. Package outline LQFP64 (SOT314-2)
TFBGA48: plastic thin fine-pitch ball grid array package; 48 balls; body 4.5 x 4.5 x 0.7 mm SOT1155-2
DBA
ball A1
index area
E
AA2
A1
detail X
e1 C
e 1/2 e H e
b G
F
E
Ø v AC B Ø w C e2
y1 C y
D ball A1 solder mask open area X

1357 2468
C
B 1/2 e
A
index area Dimensions
not for solder ball
0 5 mm scale
Unit A A1 A2 b DE ee1 e2 v w y y1
mm max nom 1.10 0.95 0.30 0.25 0.80 0.70 0.35 0.30 4.6 4.5 4.6 4.5 0.5 3.5 0.15 0.08
min 0.85 0.20 0.65 0.25 4.4 4.4 3.5 0.05 0.1 sot1155-2_po
Outline version
IEC JEDEC
References European
SOT1155-2 - - - Fig 38. Package outline TFBGA48 (SOT1155-2) 13-06-17 13-06-19
13. Soldering
Footprint information for reflow soldering of HVQFN33 package
Hx
Gx
see detail X
P
nSPx
Ay
Hy Gy By
SLy
nSPy
D
SLx
Bx
Ax
0.60
solder land
0.30
solder paste
detail X
occupied area
Dimensions in mm
Ax Ay Bx C D
By
Gx
Gy
Hx
Hy
SLx SLy nSPx nSPy
P
5.95 5.95 4.25 0.85
4.25 0.27
5.25
5.25
6.2
6.2
3.75 3.75 3 3
0.5
11-11-15
Issue date 002aag766 11-11-20
Fig 39. Reflow soldering for the HVQFN33 (5x5) package

Footprint information for reflow soldering of HVQFN33 package
OID = 8.20 OA
PID = 7.25 PA+OA
OwDtot = 5.10 OA
evia = 4.25
0.20 SR
W = 0.30 CU
chamfer (4×)
e = 0.65
GapE = 0.70 SP
evia = 1.05
SPE = 1.00 SP
PIE = 7.25 PA+OA
OwEtot = 5.10 OA
SEhtot = 2.70 SP
EHS = 4.85 CU
OIE = 8.20 OA
LbE = 5.80 CU
LaE = 7.95 CU
evia = 4.25
4.55 SR
0.45 DM
SPD = 1.00 SP 0.45 DM
GapD = 0.70 SP
B-side
evia = 2.40
SDhtot = 2.70 SP
Solder resist
covered via
4.55 SR
DHS = 4.85 CU
0.30 PH
LbD = 5.80 CU
0.60 SR cover
LaD = 7.95 CU
0.60 CU
(A-side fully covered)

number of vias: 20
solder land
solder land plus solder paste
solder paste deposit

solder resist
Remark:
occupied area 001aao134 Dimensions in mm
Stencil thickness: 0.125 mm
Fig 40. Reflow soldering for the HVQFN33 (7x7) package

Footprint information for reflow soldering of LQFP48 package
SOT313-2
Hx
Gx
(0.125)
P1
P2
Hy Gy
AyBy
D2 (8⋅) D1
Bx
Ax
Generic footprint pattern

Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1
P2
Ax Ay Bx By D1 D2 Gx Gy Hx Hy
C
0.500 0.280
0.560 10.350 7.350 7.350
10.350
1.500 0.500 7.500 7.500 10.650 10.650 sot313-2_fr
Fig 41. Reflow soldering for the LQFP48 package

Footprint information for reflow soldering of TFBGA48 package
SOT1155-2
Hx
Hy
see detail X
solder land
solder paste deposit
solder land plus solder paste

SL
occupied area
SP
SR
solder resist
detail X
DIMENSIONS in mm
P SL SP SR Hx Hy
0.50 0.225 0.275 0.325 4.75 4.75 sot1155-2_frFig 42. Reflow soldering for the TFBGA48 package

Footprint information for reflow soldering of LQFP64 package
SOT314-2
Hx
Gx
(0.125)
P2 P1
Hy Gy
AyBy
D2 (8⋅) D1
Bx
Ax
Generic footprint pattern

Refer to the package outline drawing for actual layout
solder land
occupied area
DIMENSIONS in mm
P1
P2
Ax Ay Bx By D1 D2 Gx Gy Hx Hy
C
0.500
0.560 0.280
13.300 13.300 10.300 10.300
1.500 0.400 10.500 10.500 13.550 13.550 sot314-2_fr
Fig 43. Reflow soldering for the LQFP64 package
14. Abbreviations
Table 20. Abbreviations
Acronym Description
A/D Analog-to-Digital
ADC Analog-to-Digital Converter
AHB Advanced High-performance Bus
APB Advanced Peripheral Bus
BOD BrownOut Detection
GPIO General Purpose Input/Output
JTAG Joint Test Action Group
PLL Phase-Locked Loop
RC Resistor-Capacitor
SPI Serial Peripheral Interface
SSI Serial Synchronous Interface
SSP Synchronous Serial Port
TAP Test Access Port
USART Universal Synchronous Asynchronous Receiver/Transmitter
15. References
[1] LPC11U2x User manual UM10462:
http://www.nxp.com/documents/user_manual/UM10462.pdf
[2] LPC11U2x Errata sheet:
http://www.nxp.com/documents/errata_sheet/ES_LPC11U2X.pdf
16. Revision history
Table 21. Revision history

Document ID Release date Data sheet status Change notice Supersedes
LPC11U2x v.2.3 20140327 Product data sheet - LPC11U2X v.2.2
Part LPC11U22FBD48/301 added.
LPC11U2X v.2.2 20140311 Product data sheet - LPC11U2X v.2.1
Modifications: • Updated Section 11.1 “Suggested USB interface solutions” for clarity.
• Open-drain I2C-bus and RESET pin descriptions updated for clarity. See Table 3.
LPC11U2X v.2.1 20130917 Product data sheet - LPC11U2X v.2
Modifications: • Number of CAP and MAT functions for timers updated in Figure 1.
• Table 3: Added “5 V tolerant pad” to RESET/PIO0_0 table note.
• Table 7: Removed BOD interrupt level 0.
• Added Section 11.6 “ADC effective input impedance”.
• Programmable glitch filter is enabled by default. See Section 7.7.1.
• Table 5 “Static characteristics” added Pin capacitance section.
• Updated Section 11.1 “Suggested USB interface solutions”.
• Table 4 “Limiting values”:
– Updated VDD min and max.
– Updated VI conditions.
• Table 10 “EEPROM characteristics”:
– Removed fclk and ter; the user does not have control over these parameters. –
Changed the tprog from 1.1 ms to 2.9 ms; the EEPROM IAP always does an erase and
program, thus the total program time is ter + tprog.
• Changed title of Figure 29 from “USB interface on a self-powered device” to “USB
interface with soft-connect”.
• Section 10.7 “USB interface” added. Parameter tEOPR1 and tEOPR2 renamed to tEOPR.
LPC11U2X v.2 20120113 Product data sheet - LPC11U2X v.1
Modifications: • Use of USB with power profiles specified (Section 7.17.5.1).

• Power consumption data added in Section 9.2.
• SSP dynamic characteristics added (Table 16).
• IRC dynamic characteristics added (Table 12).
• Data sheet status changed to Product data sheet.
LPC11U2X v.1 20111129 Preliminary data sheet - -
17. Legal information
17.1 Data sheet status

[1][2] [3] Definition
Document status Product status
Objective [short] data sheet Development This document contains data from the objective specification for product development.
Preliminary [short] data sheet Qualification This document contains data from the preliminary specification.
Product [short] data sheet Production This document contains the product specification.
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
and replaces all information supplied prior to the publication hereof.

17.2 Definitions Suitability for use — NXP Semiconductors products are not designed, authorized or
warranted to be suitable for use in life support, life-critical or safety-critical systems or
equipment, nor in applications where failure or malfunction of an NXP Semiconductors
Draft — The document is a draft version only. The content is still under internal review product can reasonably be expected to result in personal injury, death or severe
and subject to formal approval, which may result in modifications or additions. NXP property or environmental damage. NXP Semiconductors and its suppliers accept no
Semiconductors does not give any representations or warranties as to the accuracy or liability for inclusion and/or use of NXP Semiconductors products in such equipment or
completeness of information included herein and shall have no liability for the applications and therefore such inclusion and/or use is at the customer’s own risk.
consequences of use of such information.
Applications — Applications that are described herein for any of these products
Short data sheet — A short data sheet is an extract from a full data sheet with the are for illustrative purposes only. NXP Semiconductors makes no representation or
same product type number(s) and title. A short data sheet is intended for quick warranty that such applications will be suitable for the specified use without further
reference only and should not be relied upon to contain detailed and full information. testing or modification.
For detailed and full information see the relevant full data sheet, which is available on
request via the local NXP Semiconductors sales office. In case of any inconsistency or Customers are responsible for the design and operation of their applications and
conflict with the short data sheet, the full data sheet shall prevail. products using NXP Semiconductors products, and NXP Semiconductors accepts no
liability for any assistance with applications or customer product design. It is
Product specification — The information and data provided in a Product data customer’s sole responsibility to determine whether the NXP Semiconductors product
sheet shall define the specification of the product as agreed between NXP is suitable and fit for the customer’s applications and products planned, as well as for
Semiconductors and its customer, unless NXP Semiconductors and customer have the planned application and use of customer’s third party customer(s). Customers
explicitly agreed otherwise in writing. In no event however, shall an agreement be should provide appropriate design and operating safeguards to minimize the risks
valid in which the NXP Semiconductors product is associated with their applications and products.
deemed to offer functions and qualities beyond those described in the Product
data sheet. NXP Semiconductors does not accept any liability related to any default, damage,
costs or problem which is based on any weakness or default in the customer’s
applications or products, or the application or use by customer’s third party
customer(s). Customer is responsible for doing all necessary testing for the
customer’s applications and products using NXP Semiconductors products in order to
17.3 Disclaimers avoid a default of the applications and the products or of the application or use by
customer’s third party customer(s). NXP does not accept any liability in this respect.
Limited warranty and liability — Information in this document is believed to be Limiting values — Stress above one or more limiting values (as defined in the
accurate and reliable. However, NXP Semiconductors does not give any Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to
representations or warranties, expressed or implied, as to the accuracy or the device. Limiting values are stress ratings only and (proper) operation of the device
completeness of such information and shall have no liability for the consequences of at these or any other conditions above those given in the Recommended operating
use of such information. NXP Semiconductors takes no responsibility for the content in conditions section (if present) or the Characteristics sections of this document is not
this document if provided by an information source outside of NXP Semiconductors. warranted. Constant or repeated exposure to limiting values will permanently and
In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, irreversibly affect the quality and reliability of the device.
special or consequential damages (including - without limitation - lost profits, lost Terms and conditions of commercial sale — NXP Semiconductors products are
savings, business interruption, costs related to the removal or replacement of any sold subject to the general terms and conditions of commercial sale, as published at
products or rework charges) whether or not such damages are based on tort (including http://www.nxp.com/profile/terms, unless otherwise agreed in a valid written individual
negligence), warranty, breach of contract or any other legal theory. agreement. In case an individual agreement is concluded only the terms and
Notwithstanding any damages that customer might incur for any reason whatsoever, conditions of the respective agreement shall apply. NXP Semiconductors hereby
NXP Semiconductors’ aggregate and cumulative liability towards customer for the expressly objects to applying the customer’s general terms and conditions with regard
products described herein shall be limited in accordance with the Terms and to the purchase of NXP Semiconductors products by customer.
conditions of commercial sale of NXP Semiconductors.
No offer to sell or license — Nothing in this document may be interpreted or
Right to make changes — NXP Semiconductors reserves the right to make changes construed as an offer to sell products that is open for acceptance or the grant,
to information published in this document, including without limitation specifications conveyance or implication of any license under any copyrights, patents or other
and product descriptions, at any time and without notice. This document supersedes industrial or intellectual property rights.

Export control — This document as well as the item(s) described herein may be
subject to export control regulations. Export might require a prior authorization For more information, please visit: http://www.nxp.com
from competent authorities. whenever customer uses the product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c)
Non-automotive qualified products — Unless this data sheet expressly states that customer fully indemnifies NXP Semiconductors for any liability, damages or failed
this specific NXP Semiconductors product is automotive qualified, the product is not product claims resulting from customer design and use of the product for automotive
suitable for automotive use. It is neither qualified nor tested in accordance with applications beyond NXP Semiconductors’ standard warranty and NXP
automotive testing or application requirements. NXP Semiconductors accepts no Semiconductors’ product specifications.
liability for inclusion and/or use of non-automotive qualified products in automotive
equipment or applications. In the event that customer uses the product for design-in
and use in automotive applications to automotive specifications and standards,
customer (a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
17.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the
property of their respective owners.
18. Contact information 2

I C-bus — logo is a trademark of NXP Semiconductors N.V.
For sales office addresses, please send an email to: salesaddresses@nxp.com

19. Contents
1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 7.17.5.1 Power profiles . . . . . . . . . . . . . . . . . . . . . . . . 25
Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 7.17.5.2 Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering 7.17.5.3 Deep-sleep mode. . . . . . . . . . . . . . . . . . . . . . 25
information. . . . . . . . . . . . . . . . . . . . . 3 4.1 Ordering options . 7.17.5.4 Power-down mode . . . . . . . . . . . . . . . . . . . . . 25
. . . . . . . . . . . . . . . . . . . . . . . 3 5 Block 7.17.5.5 Deep power-down mode . . . . . . . . . . . . . . . . 26
diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning 7.17.6 System control . . . . . . . . . . . . . . . . . . . . . . . . 26
information. . . . . . . . . . . . . . . . . . . . . . 5 6.1 7.17.6.1 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin 7.17.6.2 Brownout detection . . . . . . . . . . . . . . . . . . . . 26
description . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 Functional 7.17.6.3 Code security (Code Read Protection - CRP) 26
description . . . . . . . . . . . . . . . . . . 14 7.1 On-chip flash 7.17.6.4 APB interface . . . . . . . . . . . . . . . . . . . . . . . . . 27
programming memory . . . . . . . 14 7.2 7.17.6.5 AHBLite . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 7.3 SRAM . . . 7.17.6.6 External interrupt inputs . . . . . . . . . . . . . . . . . 27 7.18
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.4 On-chip Emulation and debugging . . . . . . . . . . . . . . . 28 8 Limiting
ROM . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.5 Memory values . . . . . . . . . . . . . . . . . . . . . . . . 29 9 Static
map. . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.6 Nested Vectored characteristics . . . . . . . . . . . . . . . . . . . 30 9.1 BOD static
Interrupt Controller (NVIC) . 16 7.6.1 Features . . . . . . . . . . . . . characteristics . . . . . . . . . . . . . . . 36 9.2 Power
. . . . . . . . . . . . . . . . 16 7.6.2 Interrupt sources. . . . . . . . . . . . . . consumption . . . . . . . . . . . . . . . . . . . 36 9.3 Peripheral power
. . . . . . . . . 17 7.7 IOCON block . . . . . . . . . . . . . . . . . . . . . . . . . consumption . . . . . . . . . . . 39 9.4 Electrical pin characteristics.
17 7.7.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.8 . . . . . . . . . . . . . 41 10 Dynamic
General-Purpose Input/Output GPIO . . . . . . . 17 7.8.1 characteristics. . . . . . . . . . . . . . . . . 44 10.1 Flash
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.9 USB memory . . . . . . . . . . . . . . . . . . . . . . . . 44 10.2 External
interface . . . . . . . . . . . . . . . . . . . . . . . . 18 7.9.1 Full-speed clock. . . . . . . . . . . . . . . . . . . . . . . . . 44 10.3 Internal oscillators
USB device controller . . . . . . . . . . 18 7.9.1.1 . . . . . . . . . . . . . . . . . . . . . 45 10.4 I/O pins . . . . . . . . . . . . . . . .
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.10 . . . . . . . . . . . . . 46 10.5 I 2C-bus. . . . . . . . . . . . . . . . . . . . . . . . .
USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 7.10.1 . . . . . 46 10.6 SSP interface . . . . . . . . . . . . . . . . . . . . . . . . . 48
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.11 SSP 10.7 USB interface . . . . . . . . . . . . . . . . . . . . . . . . 51 11
serial I/O controller . . . . . . . . . . . . . . . . . 19 7.11.1 Features . . Application information . . . . . . . . . . . . . . . . . 52 11.1
. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7.12 I 2C-bus serial I/O Suggested USB interface solutions . . . . . . . . 52 11.2 XTAL
controller . . . . . . . . . . . . . . 19 7.12.1 Features . . . . . . . . . . . . . input . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 11.3 XTAL Printed-
. . . . . . . . . . . . . . . . 20 7.13 10-bit Circuit Board (PCB) layout
ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.13.1 guidelines. . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.14 General 11.4 Standard I/O pad configuration . . . . . . . . . . . 56 11.5
purpose external event Reset pad configuration . . . . . . . . . . . . . . . . . 57 11.6 ADC
counter/timers. . . . . . . . . . . . . . . . . . . . . . . . . 20 effective input impedance . . . . . . . . . . . 57 11.7 ADC usage
7.14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 7.15 notes. . . . . . . . . . . . . . . . . . . . . . 58 12 Package outline. . . . .
System tick timer . . . . . . . . . . . . . . . . . . . . . . 21 7.16 . . . . . . . . . . . . . . . . . . . 59 13
Windowed WatchDog Timer (WWDT) . . . . . . 21 7.16.1 Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 14
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 7.17 Clocking Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 69 15
and power control . . . . . . . . . . . . . . 22 7.17.1 Integrated References. . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 16
oscillators . . . . . . . . . . . . . . . . . . . 22 7.17.1.1 Internal RC Revision history . . . . . . . . . . . . . . . . . . . . . . . 70 17 Legal
oscillator . . . . . . . . . . . . . . . . . . . 23 7.17.1.2 System oscillator
information . . . . . . . . . . . . . . . . . . . . . . 71 17.1 Data sheet
. . . . . . . . . . . . . . . . . . . . . . 24 7.17.1.3 Watchdog
status . . . . . . . . . . . . . . . . . . . . . . 71 17.2
oscillator . . . . . . . . . . . . . . . . . . . . 24 7.17.2 System PLL and
USB PLL . . . . . . . . . . . . . . . 24 7.17.3 Clock output . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 17.3
. . . . . . . . . . . . . . . . . 24 7.17.4 Wake-up process . . . . . . . . . . . Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 71
. . . . . . . . . . . 24
7.17.5 Power control . . . . . . . . . . . . . . . . . . . . . . . . . 24 continued >>

17.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 72
18 Contact information. . . . . . . . . . . . . . . . . . . . . 72
19 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2014. All rights reserved.

For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 27 March 2014
Document identifier: LPC11U2X
Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:

NXP:
LPC11U24FBD48/401, LPC11U23FBD48/301, LPC11U24FBD48/301, LPC11U24FBD64/401,
LPC11U24FET48/301, LPC11U24FHI33/301, LPC11U24FHN33/401, LPC11U22FBD48/30QL
LPC11U24FHI33/301Y LPC11U24FBD48/40EL OM13066UL

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LPC11U2x

32-bit ARM Cortex-M0 microcontroller; up to 32 kB flash; up

The LPC11U2x operate at CPU frequencies of up to 50 MHz.

The peripheral complement of the LPC11U2x includes up to 32 kB of flash memory, up to 10

For additional documentation related to the LPC11U2x parts, see Section 15

2. Features and benefits

◆ ARM Cortex-M0 processor, running at frequencies of up to 50 MHz.

◆ ARM Cortex-M0 built-in Nested Vectored Interrupt Controller (NVIC).

◆ Non-Maskable Interrupt (NMI) input selectable from several input sources.

◆ System tick timer.

◆ Up to 32 kB on-chip flash program memory.

◆ Up to 4 kB on-chip EEPROM data memory; byte erasable and byte programmable. ◆

◆ ROM-based 32-bit integer division routines.

NXP Semiconductors LPC11U2x 32-bit ARM Cortex-M0 microcontroller

◆ Up to 54 General-Purpose I/O (GPIO) pins with configurable pull-up/pull-down

◆ Two GPIO grouped interrupt modules enable an interrupt based on a

◆ High-current sink driver (20 mA) on true open-drain pins.

◆ Four general-purpose counter/timers with a total of up to 5 capture inputs and 13

◆ 10-bit ADC with input multiplexing among eight pins.

◆ USB 2.0 full-speed device controller.

◆ USART (Universal Synchronous Asynchronous Receiver/Transmitter) with

◆ Crystal Oscillator with an operating range of 1 MHz to 25 MHz (system oscillator).

◆ 12 MHz high-frequency Internal RC oscillator (IRC) that can optionally be used as a

◆ Integrated PMU (Power Management Unit) to minimize power consumption during

NXP Semiconductors LPC11U2x 32-bit ARM Cortex-M0 microcontroller

◆ Power-On Reset (POR).

■ Unique device serial number for identification.

■ Single 3.3 V power supply (1.8 V to 3.6 V).

■ Temperature range −40 °C to +85 °C.

■ Available as LQFP64, LQFP48, TFBGA48, and HVQFN33 packages.

■ Consumer peripherals ■ Handheld scanners

■ Medical ■ USB audio devices

Table 1. Ordering information

Name Description Version

plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm

plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm

plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm

plastic low profile quad flat package; 48 leads; body 7 × 7 × 1.4 mm

plastic low profile quad flat package; 64 leads; body 10 × 10 × 1.4

4.1 Ordering options

NXP Semiconductors LPC11U2x 32-bit ARM Cortex-M0 microcontroller

PLL0 USB PLL

GPIO pins GPIO GROUP1 INTERRUPTS

(1) Not available on HVQFN33 packages.

Fig 1. Block diagram

NXP Semiconductors LPC11U2x 32-bit ARM Cortex-M0 microcontroller

Transparent top view

Fig 2. Pin configuration (HVQFN33)

NXP Semiconductors LPC11U2x 32-bit ARM Cortex-M0 microcontroller

Fig 3. Pin configuration (TFBGA48)

NXP Semiconductors LPC11U2x 32-bit ARM Cortex-M0 microcontroller

Fig 4. Pin configuration (LQFP48)

NXP Semiconductors LPC11U2x 32-bit ARM Cortex-M0 microcontroller

Fig 5. Pin configuration (LQFP64)

NXP Semiconductors LPC11U2x 32-bit ARM Cortex-M0 microcontroller

6.2 Pin description

Table 3. Pin description

RESET/PIO0_0 2 3 4 [2] I; PU I RESET — External reset input with 20 ns glitch

- I/O PIO0_0 — General purpose digital input/output pin.