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26 Chapter 3 (X - 86 Family)

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CHAPTER - 3

INTRODUCTION
TO
X – 86 FAMILY
BLOCK DIAGRAM

OF

8086

MICROPROCESSOR
BUS INTERFACE UNIT ( BIU)
1. QUEUE

2. SEGMENT REGISTERS

3. INSTRUCTION POINTER
QUEUE

Stores them
Speeds up Fetches 6
in the FIFO
program bytes of
register to be
execution instruction
used by
ahead of time
Execution
Unit (E.U.)
SEGMENT REGISTERS
Four 16 – bit segment registers are used
to store the starting address of memory
segment.
The four segment registers are:
1.Extra Segment ( E.S. )
2.Code Segment ( C.S. )
3.Stack Segment ( S.S. )
4.Data Segment ( D.S. )
INSTRUCTION POINTER ( I.P. )
• Code segment contains starting
address of segment having code
bytes

• Instruction Pointer holds the


address of the next code byte within
the code segment.
EXECUTION UNIT ( E.U. )
1.Flag Register - 8086 has 16 – bit flag register with 9
active flags.

2.General Purpose Registers - 8086 has 8


general purpose registers.

3.Stack Pointer - 16 – bit starting address of stack is


stored in SP.
8086 allows 64 KB of RAM as stack.
FLAG REGISTER OF
16 – BIT VERSION
OF
X – 86 FAMILY
16 – BIT FLAG REGISTER OF X – 86 FAMILY

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0


FLAG REGISTER OF
32 – BIT VERSION
OF
X – 86 FAMILY
32 – BIT FLAG REGISTER OF X – 86 FAMILY
PROGRAMMING MODEL

OF 16 – BIT

VERSION OF

X – 86 FAMILY
Programming Model of 8085 Microprocessor
PROGRAMMING MODEL

OF 32 – BIT

VERSION OF

X – 86 FAMILY
SERIES

OF

MICROPROCESSORS IN

X – 86 FAMILY
SERIES INTRODUCED ADDRESS DATA MEMORY FEATURES
BY INTEL IN BUS BUS CAPACITY
THE YEAR
8086 1978 20 - BIT 16 - BIT 1 MB •Supports Multiplication
and Division operations.
80286 1982 24 - BIT 16 - BIT REAL : 1 MB •Works in Real and
PROTECTED : Protected modes.
16 MB • IBM made PC/AT using
80286.

80386 1985 32 – BIT 32 - BIT 4 GB • Operates in Paged & Non-


(NON – Paged modes.
MULTIPLEXED)
• It has a Non – Multiplexed
Address Bus.
80486 1989 32 - BIT 32 - BIT 4 GB • It has Built-in : Math Co-
processor ; M.M.U. ; 8 KB
Cache Memory.
• It has SX and DX versions.
• It has DX2 and DX4 version
80586 1993 32 - BIT 64 - BIT 4 GB • Dual Pipelining
• Branch Prediction
• On-Chip caches
• 64 – bit Data Bus
MAIN FEATURES OF PENTIUM PROCESSOR

1) DUAL PIPELINING – Use of super scalar architecture which allows


the Pentium processor to process more than one instruction per
clock cycle.

2) BRANCH PREDICTION – The Pentium processor makes an


educated guess as to where the next instruction will be following
a conditional instruction.

3) ON CHIP CACHES – The Data and Code On-Chip Caches increase


the processing speed of the Pentium processor.

4) 64 – BIT DATA BUS – The 64 –bit Data Bus will increase the
processing speed of the Pentium processor as it will have twice
the speed of a 32 – bit processor.
Important Board
Exam Questions for
Chapter 3
Q1. Draw the flag register of the 16-bit
version of X-86 microprocessor.
Q2. Draw the flag register of the 32-bit
version of X-86 microprocessor.
Q3. Explain the programming model
of 16-bit version of X-86 family.

Q4. Explain the programming model


of 32-bit version of X-86 family.
Q5. Explain the various series in the
X-86 family of microprocessors.

Q6. Explain the four important


features of the Pentium processor.

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