UNIT-V

Embedded Communications Protocols and

Internet of Things
COMMUNICATION:
Communication between electronic devices is like communication between humans. Both
sides need to speak the same language. In electronics, these languages are called communication
protocols. Luckily for us, there are only a few communication protocols we need to know when
building most electronics projects. In this series of articles, we will discuss the basics of the three
most common protocols: SPI, I2C and UART.
SPI, I2C, and UART are quite a bit slower than protocols like USB, Ethernet, Bluetooth,
and Wi-Fi, but they’re a lot simpler and use less hardware and system resources. SPI, I2C, and
UART are ideal for communication between microcontrollers and between microcontrollers and
sensors where large amounts of high speed data don’t need to be transferred.
DATA COMMUNICATION TYPES: (1) PARALLEL
(2) SERIAL: (I) ASYNCHRONOUS (II) SYNCHRONOUS
Parallel Communication:
• In parallel communication, all the bits of data are transmitted simultaneously on
separate communication lines.
• Used for shorter distance.
• In order to transmit n bit, n wires or lines are used.
• More costly.
• Faster than serial transmission.
• Data can be transmitted in less time.
Example: printers and hard disk

Serial Communication Basics:

• In serial communication the data bits are transmitted serially one by one i.e. bit by bit
on single communication line
• It requires only one communication line rather than n lines to transmit data from
sender to receiver.
• Thus all the bits of data are transmitted on single lines in serial fashion.
• Less costly.
• Long distance transmission.
Example: Telephone.
Serial communication uses two methods:
• Asynchronous.
• Synchronous.
Asynchronous:
🢡 Transfers single byte at a time.
🢡 No need of clock signal
❖ Example: UART (universal asynchronous receiver transmitter)
Synchronous:
🢡 Transfers a block of data (characters) at a time.
🢡 Requires clock signal
❖ Example: SPI (serial peripheral interface),
I2C (inter integrated circuit).

Data Transmission: In data transmission if the data can be transmitted and received,
it is a duplex transmission.
Simplex: Data is transmitted in only one direction i.e. from TX to RX only one TX
and one RX only
Half duplex: Data is transmitted in two directions but only one way at a time i.e. two
TX's, two RX’s and one line
Full duplex: Data is transmitted both ways at the same time i.e. two TX's, two RX’s
and two lines

A Protocol is a set of rules agreed by both the sender and receiver on

• How the data is packed
• How many bits constitute a character
• When the data begins and ends
Table: Various Serial Communication Protocols
Serial Synchronous Data transfer
Type Duplex
Protocol /Asynchronous rate (kbps)

UART Asynchronous peer-to-peer Full-duplex 20

I2C Synchronous multi-master Half-duplex 3400

SPI Synchronous multi-master Full-duplex >1,000

MICROWIRE Synchronous master/slave Full-duplex > 625

1-WIRE Asynchronous master/slave Half-duplex 16

Baud Rate Concepts:

Data transfer rate in serial communication is measured in terms of bits per second
(bps). This is also called as Baud Rate. Baud Rate and bps can be used inter changeably with
respect to UART.
Ex: The total number of bits gets transferred during 10 pages of text, each with 100 ×
25 characters with 8 bits per character and 1 start & stop bit is:
For each character a total number of bits are 10. The total number of bits is:
100 × 25 × 10 = 25,000 bits per page. For 10 pages of data it is required to transmit 2, 50,000
bits. Generally baud rates of SCI are 1200, 2400, 4800, 9600, 19,200 etc. To transfer 2,
50,000 bits at a baud rate of 9600, we need: 250000/9600 = 26.04 seconds (27 seconds).

Synchronous/Asynchronous Interfaces (like UART, SPI,

I2C, and USB):
Serial communication protocols can be categorized as Synchronous and
Asynchronous protocols. In synchronous communication, data is transmission and receiving
is a continuous stream at a constant rate. Synchronous communication requires the clock of
transmitting device and receiving device synchronized. In most of the systems, like ADC,
audio codes, potentiometers, transmission and reception of data occurs with same frequency.
Examples of synchronous communication are: I2C, SPI etc. In the case of asynchronous
communication, the transmission of data requires no clock signal and data transfer occurs
intermittently rather than steady stream. Handshake signals between the transmitter and
receiver are important in asynchronous communications. Examples of asynchronous
communication are Universal Asynchronous Receiver Transmitter (UART), CAN etc.
Synchronous and asynchronous communication protocols are well-defined standards
and can be implemented in either hardware or software. In the early days of embedded
systems, Software implementation of I2C and SPI was common as well as a tedious work and
used to take long programs. Gradually, most the microcontrollers started incorporating the
standard communication protocols as hardware cores. This development in early 90‟s made
job of the embedded software development easy for communication protocols.
 Microcontroller of our interest TM4C123 supports UART, CAN, SPI, I2C and USB
protocols. The five (UART, CAN, SPI, I2C and USB) above mentioned communication
protocols are available in most of the modern day microcontrollers. Before studying the
implementation and programming details of these protocols in TM4C123, it is required to
understand basic standards, features and applications. In the following sections, we discuss
fundamentals of the above mentioned communication protocols.

UART COMMUNICATION
In UART communication, two UARTs communicate directly with each other. The
transmitting UART converts parallel data from a controlling device like a CPU into serial form,
transmits it in serial to the receiving UART, which then converts the serial data back into parallel
data for the receiving device. Only two wires are needed to transmit data between two UARTs.
Data flows from the Tx pin of the transmitting UART to the Rx pin of the receiving UART:

UARTs transmit data asynchronously, which means there is no clock signal to synchronize
the output of bits from the transmitting UART to the sampling of bits by the receiving UART.
Instead of a clock signal, the transmitting UART adds start and stop bits to the data packet being
transferred. These bits define the beginning and end of the data packet so the receiving UART
knows when to start reading the bits.
When the receiving UART detects a start bit, it starts to read the incoming bits at a
specific frequency known as the baud rate. Baud rate is a measure of the speed of data
transfer, expressed in bits per second (bps). Both UARTs must operate at about the same baud
rate. The baud rate between the transmitting and receiving UARTs can only differ by about 10%
before the timing of bits gets too far off.
Both UARTs must be configured to transmit and receive the same data packet structure.
HOW UART WORKS
The UART that is going to transmit data receives the data from a data bus. The data bus
is used to send data to the UART by another device like a CPU, memory, or microcontroller.
Data is transferred from the data bus to the transmitting UART in parallel form. After the
transmitting UART gets the parallel data from the data bus, it adds a start bit, a parity bit, and a
stop bit, creating the data packet. Next, the data packet is output serially, bit by bit at the Tx pin.
The receiving UART reads the data packet bit by bit at its Rx pin. The receiving UART then
converts the data back into parallel form and removes the start bit, parity bit, and stop bits.
Finally, the receiving UART transfers the data packet in parallel to the data bus on the receiving
end:

UART transmitted data is organized into packets. Each packet contains 1 start bit, 5 to 9
data bits (depending on the UART), an optional parity bit, and 1 or 2 stop bits:

START BIT
The UART data transmission line is normally held at a high voltage level when it’s
not transmitting data. To start the transfer of data, the transmitting UART pulls the transmission
line from high to low for one clock cycle. When the receiving UART detects the high to low
voltage transition, it begins reading the bits in the data frame at the frequency of the baud rate.
DATA FRAME
The data frame contains the actual data being transferred. It can be 5 bits to 9 bits long if
a parity bit is used. If no parity bit is used, the data frame can be 8 bits long. In most cases, the
data is sent with the least significant bit first.

PARITY
Parity describes the evenness or oddness of a number. The parity bit is a way for the
receiving UART to tell if any data has changed during transmission. Bits can be changed
by electromagnetic radiation, mismatched baud rates, or long distance data transfers. After the
receiving UART reads the data frame, it counts the number of bits with a value of 1 and checks if
the total is an even or odd number. If the parity bit is a 0 (even parity), the 1 bits in the data frame
should total to an even number. If the parity bit is a 1 (odd parity), the 1 bits in the data frame
should total to an odd number. When the parity bit matches the data, the UART knows that the
transmission was free of errors. But if the parity bit is a 0, and the total is odd; or the parity bit is a
1, and the total is even, the UART knows that bits in the data frame have changed.

STOP BITS
The Stop Bit, as the name suggests, marks the end of the data packet. It is usually two
bits long but often only on bit is used. In order to end the transmission, the UART maintains the
data line at high voltage (1).

STEPS OF UART TRANSMISSION

1. The transmitting UART receives data in parallel from the data bus:

2. The transmitting UART adds the start bit, parity bit, and the stop bit(s) to the data frame:
3. The entire packet is sent serially from the transmitting UART to the receiving UART. The
receiving UART samples the data line at the pre-configured baud rate:

4. The receiving UART discards the start bit, parity bit, and stop bit from the data frame:

5. The receiving UART converts the serial data back into parallel and transfers it to the data bus
on the receiving end:
ADVANTAGES AND DISADVANTAGES OF UARTS
No communication protocol is perfect, but UARTs are pretty good at what they do. Here are
some pros and cons to help you decide whether or not they fit the needs of your project:

ADVANTAGES
• Only uses two wires
• No clock signal is necessary
• Has a parity bit to allow for error checking
• The structure of the data packet can be changed as long as both sides are set up for it
• Well documented and widely used method
DISADVANTAGES
• The size of the data frame is limited to a maximum of 9 bits
• Doesn’t support multiple slave or multiple master systems
• The baud rates of each UART must be within 10% of each other

UART or Universal Asynchronous Receiver Transmitter is a dedicated hardware

associated with serial communication. The hardware for UART can be a circuit integrated on the
microcontroller or a dedicated IC. This is contrast to SPI or I2C, which are just communication
protocols.

UART is one of the most simple and most commonly used Serial Communication
techniques. Today, UART is being used in many applications like GPS Receivers, Bluetooth
Modules, GSM and GPRS Modems, Wireless Communication Systems, RFID based applications
etc.

SPI COMMUNICATION PROTOCOL

SPI is a common communication protocol used by many different devices. For example,
SD card modules, RFID card reader modules, and 2.4 GHz wireless transmitter/receivers all use
SPI to communicate with microcontrollers.
One unique benefit of SPI is the fact that data can be transferred without interruption.
Any number of bits can be sent or received in a continuous stream. With I2C and UART, data is
sent in packets, limited to a specific number of bits. Start and stop conditions define the
beginning and end of each packet, so the data is interrupted during transmission.
Devices communicating via SPI are in a master-slave relationship. The master is the
controlling device (usually a microcontroller), while the slave (usually a sensor, display, or
memory chip) takes instruction from the master. The simplest configuration of SPI is a single
master, single slave system, but one master can control more than one slave (more on this
below).
MOSI (Master Output/Slave Input) – Line for the master to send data to the slave.
MISO (Master Input/Slave Output) – Line for the slave to send data to the master
SCLK (Clock) – Line for the clock signal.
SS/CS (Slave Select/Chip Select) – Line for the master to select which slave to send data to.

*In practice, the number of slaves is limited by the load capacitance of the system, which reduces the
ability of the master to accurately switch between voltage levels.

HOW SPI WORKS

THE CLOCK
The clock signal synchronizes the output of data bits from the master to the sampling of
bits by the slave. One bit of data is transferred in each clock cycle, so the speed of data transfer
is determined by the frequency of the clock signal. SPI communication is always initiated by the
master since the master configures and generates the clock signal.
Any communication protocol where devices share a clock signal is known
as synchronous. SPI is a synchronous communication protocol. There are
also asynchronous methods that don’t use a clock signal. For example, in UART communication,
both sides are set to a pre-configured baud rate that dictates the speed and timing of data
transmission.
The clock signal in SPI can be modified using the properties of clock polarity and clock
phase. These two properties work together to define when the bits are output and when they are
sampled. Clock polarity can be set by the master to allow for bits to be output and sampled on
either the rising or falling edge of the clock cycle. Clock phase can be set for output and sampling
to occur on either the first edge or second edge of the clock cycle, regardless of whether it is
rising or falling.

SLAVE SELECT
The master can choose which slave it wants to talk to by setting the slave’s CS/SS line to
a low voltage level. In the idle, non-transmitting state, the slave select line is kept at a high
voltage level. Multiple CS/SS pins may be available on the master, which allows for multiple
slaves to be wired in parallel. If only one CS/SS pin is present, multiple slaves can be wired to
the master by daisy-chaining.

MULTIPLE SLAVES
SPI can be set up to operate with a single master and a single slave, and it can be set up
with multiple slaves controlled by a single master. There are two ways to connect multiple slaves
to the master. If the master has multiple slave select pins, the slaves can be wired in parallel like
this:
If only one slave select pin is available, the slaves can be daisy-chained like this:

MOSI AND MISO

The master sends data to the slave bit by bit, in serial through the MOSI line. The slave
receives the data sent from the master at the MOSI pin. Data sent from the master to the slave is
usually sent with the most significant bit first.
The slave can also send data back to the master through the MISO line in serial. The
data sent from the slave back to the master is usually sent with the least significant bit first.
STEPS OF SPI DATA TRANSMISSION
1. The master outputs the clock signal:

2. The master switches the SS/CS pin to a low voltage state, which activates the slave:

3. The master sends the data one bit at a time to the slave along the MOSI line. The slave reads
the bits as they are received:

4. If a response is needed, the slave returns data one bit at a time to the master along the MISO
line. The master reads the bits as they are received:

ADVANTAGES AND DISADVANTAGES OF SPI

There are some advantages and disadvantages to using SPI, and if given the choice
between different communication protocols, you should know when to use SPI according to the
requirements of your project:
ADVANTAGES
• No start and stop bits, so the data can be streamed continuously without interruption
• No complicated slave addressing system like I2C
• Higher data transfer rate than I2C (almost twice as fast)
• Separate MISO and MOSI lines, so data can be sent and received at the same time

DISADVANTAGES
• Uses four wires (I2C and UARTs use two)
• No acknowledgement that the data has been successfully received (I2C has this)
• No form of error checking like the parity bit in UART
• Only allows for a single master

Fig: SPI Master connected to a single slave

Fig: SPI master connected to multiple slaves

I2C COMMUNICATION PROTOCOL
Inter IC (i2c) (IIC) is important serial communication protocol in modern electronic
systems. Philips invented this protocol in 1986. The objective of reducing the cost of production
of television remote control motivated Philips to invent this protocol. IIC is a serial bus interface,
can be implemented in software, but most of the microcontrollers support IIC by incorporating it
as hard IP (Intellectual Property). IIC can be used to interface microcontroller with RTC,
EEPROM and different variety of sensors. IIC is used to interface chips on motherboard,
generally between a processor chip and any peripheral which supports IIC. IIC is very reliable
wireline communication protocol for an on board or short distances. I2C is a serial protocol for
two-wire interface to connect low-speed devices like microcontrollers, EEPROMs, A/D and D/A
converters, I/O interfaces and other similar peripherals in embedded systems

I2C combines the best features of SPI and UARTs. With I2C, you can connect multiple
slaves to a single master (like SPI) and you can have multiple masters controlling single, or
multiple slaves. This is really useful when you want to have more than one microcontroller
logging data to a single memory card or displaying text to a single LCD.

IIC protocol uses two wires for data transfer between devices: Serial Data Line (SDA)
and Serial Clock Line (SCL). The reduction in number of pins in comparison with parallel data
transfer is evident. This reduces the cost of production, package size and power consumption.
IIC is also best suited protocol for battery operated devices. IIC is also referred as two wire serial
interface (TWI).

SDA (Serial Data) – The line for the master and slave to send and receive data.
SCL (Serial Clock) – The line that carries the clock signal.
I2C is a serial communication protocol, so data is transferred bit by bit along a single wire
(the SDA line).
 Like SPI, I2C is synchronous, so the output of bits is synchronized to the sampling of bits
by a clock signal shared between the master and the slave. The clock signal is always controlled
by the master.

GENERAL ELECTRICAL CHARACTERISTICS OF I2C

To implement I2C (For TIVA series microcontrollers or for most of the
microcontrollers) a 4.7kilo ohm pull-up resistor for each line is needed. This is required to
implement wired-AND logic in IIC.
More than 100 devices can be connected to I2C bus theoretically. It is better to restrict
to 15 devices for better performance of the network. Each device is called as node. Nodes
which generates clock are called Master nodes and devices which work based on the clock
generated by master node are called Slave nodes. Generally, master nodes initiate and
terminate the transmission. The four possible modes of operation are: master transmitter,
master receiver, slave transmitter and slave receiver.

HOW I2C WORKS

With I2C, data is transferred in messages. Messages are broken up into frames of data.
Each message has an address frame that contains the binary address of the slave, and one or
more data frames that contain the data being transmitted. The message also includes start and
stop conditions, read/write bits, and ACK/NACK bits between each data frame:
Start Condition: The SDA line switches from a high voltage level to a low voltage level before the
SCL line switches from high to low.
Stop Condition: The SDA line switches from a low voltage level to a high voltage level after the
SCL line switches from low to high.
Address Frame: A 7 or 10 bit sequence unique to each slave that identifies the slave when the
master wants to talk to it.
Read/Write Bit: A single bit specifying whether the master is sending data to the slave (low
voltage level) or requesting data from it (high voltage level).
ACK/NACK Bit: Each frame in a message is followed by an acknowledge/no-acknowledge bit. If
an address frame or data frame was successfully received, an ACK bit is returned to the sender
from the receiving device.

ADDRESSING
I2C doesn’t have slave select lines like SPI, so it needs another way to let the slave know
that data is being sent to it, and not another slave. It does this by addressing. The address frame
is always the first frame after the start bit in a new message.
The master sends the address of the slave it wants to communicate with to every slave
connected to it. Each slave then compares the address sent from the master to its own address.
If the address matches, it sends a low voltage ACK bit back to the master. If the address doesn’t
match, the slave does nothing and the SDA line remains high.

READ/WRITE BIT
The address frame includes a single bit at the end that informs the slave whether the
master wants to write data to it or receive data from it. If the master wants to send data to the
slave, the read/write bit is a low voltage level. If the master is requesting data from the slave, the
bit is a high voltage level.

THE DATA FRAME

After the master detects the ACK bit from the slave, the first data frame is ready to be
sent.
 The data frame is always 8 bits long, and sent with the most significant bit first. Each data
frame is immediately followed by an ACK/NACK bit to verify that the frame has been received
successfully. The ACK bit must be received by either the master or the slave (depending on who
is sending the data) before the next data frame can be sent.
After all of the data frames have been sent, the master can send a stop condition to the
slave to halt the transmission. The stop condition is a voltage transition from low to high on the
SDA line after a low to high transition on the SCL line, with the SCL line remaining high.

STEPS OF I2C DATA TRANSMISSION

1. The master sends the start condition to every connected slave by switching the SDA line from
a high voltage level to a low voltage level before switching the SCL line from high to low:

2. The master sends each slave the 7 or 10 bit address of the slave it wants to communicate
with, along with the read/write bit:
3. Each slave compares the address sent from the master to its own address. If the address
matches, the slave returns an ACK bit by pulling the SDA line low for one bit. If the address from
the master does not match the slave’s own address, the slave leaves the SDA line high.

4. The master sends or receives the data frame:

5. After each data frame has been transferred, the receiving device returns another ACK bit to
the sender to acknowledge successful receipt of the frame:

6. To stop the data transmission, the master sends a stop condition to the slave by
switching SCL high before switching SDA high:

SINGLE MASTER WITH MULTIPLE SLAVES

Because I2C uses addressing, multiple slaves can be controlled from a single master.
With a 7 bit address, 128 (27) unique address are available. Using 10 bit addresses is
uncommon, but provides 1,024 (210) unique addresses. To connect multiple slaves to a single
master, wire them like this, with 4.7K/10K Ohm pull-up resistors connecting the SDA and SCL
lines to Vcc:
MULTIPLE MASTERS WITH MULTIPLE SLAVES
Multiple masters can be connected to a single slave or multiple slaves. The problem with
multiple masters in the same system comes when two masters try to send or receive data at the
same time over the SDA line. To solve this problem, each master needs to detect if the SDA line
is low or high before transmitting a message. If the SDA line is low, this means that another
master has control of the bus, and the master should wait to send the message. If the SDA line is
high, then it’s safe to transmit the message. To connect multiple masters to multiple slaves, use
the following diagram, with 4.7K Ohm pull-up resistors connecting the SDA and SCL lines to Vcc:

ADVANTAGES AND DISADVANTAGES OF I2C

There is a lot to I2C that might make it sound complicated compared to other protocols,
but there are some good reasons why you may or may not want to use I2C to connect to a
particular device:

ADVANTAGES
• Only uses two wires
• Supports multiple masters and multiple slaves
• ACK/NACK bit gives confirmation that each frame is transferred successfully
• Hardware is less complicated than with UARTs
• Well known and widely used protocol
DISADVANTAGES
• Slower data transfer rate than SPI
• The size of the data frame is limited to 8 bits
• More complicated hardware needed to implement than SPI

UNIVERSAL SERIAL BUS (USB)

Universal Serial Bus (USB) is a set of interface specifications for high speed wired
communication between electronics systems peripherals and devices with or without
PC/computer. The USB was originally developed in 1995 by many of the industry leading
companies like Intel, Compaq, Microsoft, Digital, IBM, and Northern Telecom.

The major goal of USB was to define an external expansion bus to add peripherals to a
PC in easy and simple manner.

USB offers users simple connectivity. It eliminates the mix of different connectors for
different devices like printers, keyboards, mice, and other peripherals. That means USB-bus
allows many peripherals to be connected using a single standardized interface socket. It supports
all kinds of data, from slow mouse inputs to digitized audio and compressed video.

USB also allows hot swapping. The "hot-swapping" means that the devices can be
plugged and unplugged without rebooting the computer or turning off the device. That means,
when plugged in, everything configures automatically. Once the user is finished, they can simply
unplug the cable out; the host will detect its absence and automatically unload the driver. This
makes the USB a plug-and-play interface between a computer and add-on devices.

USB is now the most used interface to connect devices like mouse, keyboards, PDAs,
game-pads and joysticks, scanners, digital cameras, printers, personal media players, and flash
drives to personal computers.

USB sends data in serial mode i.e. the parallel data is serialized before sends and de-
serialized after receiving.

The benefits of USB are low cost, expandability, auto-configuration, hot-plugging and
outstanding performance. It also provides power to the bus, enabling many peripherals to
operate without the added need for an AC power adapter.

Various versions USB:

USB1.0: USB 1.0 is the original release of USB having the capability of transferring
12Mbps, supporting up to 127 devices. This USB 1.0 specification model was introduced in
January 1996.

USB1.1: USB 1.1 came out in September 1998. USB 1.1 is also known as full-speed
USB. This version is similar to the original release of USB; however, there are minor
modifications for the hardware and the specifications. USB version 1.1 supported two speeds, a
full speed mode of 12Mbits/s and a low speed mode of 1.5Mbits/s.
 USB2.0: Hewlett-Packard, Intel, LSI Corporation, Microsoft, NEC, and Philips jointly led
the initiative to develop a higher data transfer rate than the 1.1 specifications. The USB 2.0
specification was released in April 2000 and was standardized at the end of 2001.
Supporting three speed modes (1.5, 12 and 480 Mbps), USB 2.0 supports low-bandwidth
devices such as keyboards and mice, as well as high-bandwidth ones like high-resolution Web-
cams, scanners, printers and high-capacity storage systems.
USB 2.0, also known as hi-speed USB. This hi-speed USB is capable of supporting a
transfer rate of up to 480 Mbps, compared to 12 Mbps of USB 1.1. That's about 40 times as fast!
Wow!
USB3.0: USB 3.0 is the latest version of USB release. It is also called as Super-Speed
USB having a data transfer rate of 4.8Gbps (600 MB/s). That means it can deliver over 10x the
speed of today's Hi-Speed USB connections.
The USB 3.0 specification was released by Intel and its partners in August 2008.
Products using the 3.0 specifications are come out in 2010.
The USB "tiered star" topology:
The USB system is made up of a host, multiple numbers of USB ports, and multiple
peripheral devices connected in a tiered-star topology.
The host is the USB system's master, and as such, controls and schedules all
communications activities. Peripherals, the devices controlled by USB, are slaves responding to
commands from the host. USB devices are linked in series through hubs. There always exists
one hub known as the root hub, which is built in to the host controller.

Fig: The USB "tiered star" topology

USB connectors:

Connecting a USB device to a computer is very simple -- you find the USB connector on
the back of your machine and plug the USB connector into it. If it is a new device, the operating
system auto-detects it and asks for the driver disk. If the device has already been installed, the
computer activates it and starts talking to it.

The USB standard specifies two kinds of cables and connectors.

Fig: USB Type A & B Connectors

The USB standard uses "A" and "B" connectors mainly to avoid confusion:
1. "A" connectors head "upstream" toward the computer.
2. "B" connectors head "downstream" and connect to individual devices.
By using different connectors on the upstream and downstream end, it is impossible to
install a cable incorrectly, because the two types are physically different.

Pin No Signal Color of the cable

1 +5V power Red
2 - Data White / Yellow
3 +Data Green / Blue
4 Ground Black/Brown
Table: USB pin connections
USB can support 4 data transfer types or transfer modes.
1. Control
2. Isochronous
3. Bulk
4. Interrupt
Control transfers exchange configuration, setup and command information between the
device and host. The host can also send commands or query parameters with control packets.
Isochronous transfer is used by time critical, streaming device such as speakers and
video cameras. It is time sensitive information so, within limitations, it has guaranteed access to
the USB bus.
Bulk transfer is used by devices like printers & scanners, which receives data in one big
packet.
Interrupt transfer is used by peripherals exchanging small amounts of data that need
immediate attention.
 All USB data is sent serially. USB data transfer is essentially in the form of packets of
data, sent back and forth between the host and peripheral devices. Initially all packets are sent
from the host, via the root hub and possibly more hubs, to devices.
Each USB data transfer consists of a…
1. Token packet (Header defining what it expects to follow)
2. Optional Data Packet (Containing the payload)
3. Status Packet (Used to acknowledge transactions and to provide a means of error
correction).

Implementing and Programming UART:

TM4C123GH6PM microcontroller has got eight UART ports. They are named as
UART0-UART7. In the TI Launchpad, the UART0 port is connected to the ICDI (In-Circuit
Debug Interface). ICDI is further connected to USB port. Users can use UART0 for flash
programming, debugging using JTAG. The UART features of TI Tiva TM4C123GH6PM
microcontroller is: -
• UART‟s have programmable baud-rate generator allowing speeds up to 5 Mbps for
regular speed and 10 Mbps for high speed.
• Separate 16x8 transmit (TX) and receive (RX) FIFOs to reduce CPU interrupt service
loading with programmable FIFO length
• Standard asynchronous communication bits for start, stop, and parity, Line-break
generation and detection
• Fully programmable serial interface characteristics
o 5, 6, 7, or 8 data bits
o Even, odd, stick, or no-parity bit generation/detection
o 1 or 2 stop bit generation
• IrDA serial-IR (SIR) encoder/decoder providing
o Programmable use of IrDA Serial Infrared (SIR) or UART input/output
o Support of IrDA SIR encoder/decoder functions for data rates up to 115.2 Kbps
half duplex
o Support of normal 3/16 and low-power (1.41-2.23 μs) bit durations
o Programmable internal clock generator enabling division of reference clock by 1
to 256 for low-power mode bit duration
• Support for communication with ISO 7816 smart cards
• Modem flow control (on UART1)
• EIA-485 9-bit support
• Standard FIFO-level and End-of-Transmission interrupts
• Efficient transfers using Micro Direct Memory Access Controller (μDMA)
o Separate channels for transmit and receive
o Receive single request asserted when data is in the FIFO; burst request asserted at
programmed FIFO level Transmit single request asserted when there is space in
the FIFO; burst request asserted at programmed FIFO level.
UART Register Map
TI Tiva TM4C123GH6PM UART has got several Special Function Registers (SFR‟s)
which needs to program with appropriate values to achieve required UART functionality. In
this section, UART0 is taken as example in which virtual connection is possible on TI Tiva
launch pad.

Figure: Simplified block diagram of UART

Baud Rate Generators: The SFR‟s used in setting the baud rate are UART Integer
Baud-Rate Divisor (UARTIBRD) and UART Fractional Baud-Rate Divisor (UARTFBRD).
The block diagram of the registers is given below:

Figure: Baud Rate Registers

The physical addresses for these UART baud rate registers are: 0x4000:C000+0x024
(UARTIBRD) and 0x4000:C000+0x028 (UARTFBRD). Only lower 16 bit are used in
UARTIBRD and lower 6-bits are used in UARTFBRD. So it comes to total of 22 bits (16-bit
integer + 6 bit of fraction). To reduce the error rate and use the standard baud rate supported
by the terminal programs it is required to use both the registers when we program for the
baud rate. The standard baud rates are: 2400, 4800, 9600, 19200, 57600 and 115200.

Baud rate can be calculated using the below formula:

Desired Baud Rate = SysClk / (16 × ClkDiv)

 Where the SysClk is the working system clock connected to the UART and ClkDiv is
the value programmed into baud rate registers.

The baud-rate divisor (BRD) has the following relationship to the system clock,
where BRDI is the integer part of the BRD and BRDF is the fractional part, separated by a
decimal place.

BRD = BRDI + BRDF = UARTSysClk / (ClkDiv * Baud Rate)

UARTSysClk is the system clock connected to the UART, and ClkDiv is 16 (if HSE
in UARTCTL is clear) or 8 (if HSE is set).
Alternatively, the UART may be clocked from the internal precision oscillator
(PIOSC), independent of the system clock selection. This will allow the UART clock to be
programmed independently of the system clock PLL settings.

TI Tiva Launchpad system clock is 16 MHz so desired Baud Rate can be calculated as:

Baud Rate = 16MHz / (16 × ClkDiv) = 1MHz / ClkDiv

The ClkDiv value includes both integer and fractional values loaded into UARTIBRD
and UARTFBRD registers. The integer part is easy to calculate and fraction part requires
manipulations based on trial and error.

Example:
System clock of TI Tiva Launchpad is16 MHz 16MHz is divided by 16 and it is fed
into UART. So UART operates at 1MHz frequency. So ClkDiv = 1MHz.
To generate a baud rate of 4800: 1MHz/4800 = 208.33
(a) 1MHz/4800 = 208.33, UARTIBRD=208 & UARTFBRD = (0.33×64) + 0.5 = 21.83 =21
(b) 1MHz/9600 = 104.166666, UARTIBRD = 104 & UARTFBRD = (0.16666×64) +0.5=11
(c) 1MHz/57600 = 17.361, UARTIBRD = 17 and UARTFBRD = (0.361 × 64) + 0.5 =23
(d) 1MHz/115200 = 8.680, UARTIBRD = 8 and UARTFBRD = (0.680 × 64) +0.5=44
Serial IR (SIR):
UART includes an IrDA (Infrared) serial IR encoder-decoder block. SIR block
converts the data between UART and half-duplex serial SIR interface. The SIR block
provides a digitally encoded output and decoded input to UART. SIR block uses UnTx and
UnRx pins for SIR interface. These pins are connected to IrDA SIR physical layer link. SIR
block supports half-duplex communication. The IrDA SIR physical layer specifies a
minimum 10-ms delay between transmission and reception. The SIR block has two modes of
operation normal mode and low power mode.

ISO 7816 Support: UART support ISO 7816 smartcard communication. The UnTx signal is
used as a bit clock and the UnRx signal is used as the half-duplex communication line
connected to the smartcard. Any GPIO signal can be used to generate the reset signal to the
smartcard.
UART Control Register (UARTCTL):
This is a 32-bit register. The most important bits are RXE, TXE, HSE, and UARTEN.

Figure: UART Control Register (UARTCTL)

• RXE (Receive enable): This bit should be enabled to receive data.

• TXE (Transmit Enable): This bit should be enabled to transmit data.
• HSE (High Speed enable): This bit is used to set the baud rate. By default the system
clock is divided by 16 before it is fed to the UART. The user can program HSE =1, to
make system clock divide by 8.
• UARTEN (UART enable): This bit allows user to enable or disable the UART. During
the initialization of the UART registers, this is disabled. To disable UART under any
circumstances, this bit is used.
• SIREN (SIR Enable): IrDA SIR Block is enabled. UART will transmit and receive data
using SIR protocol.
• SIRLP (SIR Low Power Mode): This bit selects the IrDA encoding mode: Normal
mode or low power mode.
• SMART (ISO 7816 Smart Card support): The UART operates in Smart Card mode
when SMART = 1. UART does not support automatic retransmission on parity errors.
If a parity error is detected on transmission, all further transmit operations are aborted
and software must handle retransmission of the affected byte or message.
• LBE (Loop Back Enable): The UnTx path is fed through the UnRx path when LBE =1.
• RTSEN (Enable Request to send): RTS hardware flow control is enabled. Data is only
requested when receive FIFO has available entries.
• RTS (Request to send): When RTSEN is clear, the status of this bit is reflected on the
U1RTS signal. If RTSEN is set, this bit is ignored on a write and should be ignored on
read.

UART Line Control Register (UARTLCTH)

This register is used to set the length of data. The bits per character in a frame and
number of stop bits are also decided.
 • STP2 (Stop bit2): The stop bits can be 1 or 2. The default is 1 stop bit at the end of
each frame. If the receiving device is slow, we can use 2 stop bits by making the
STP2=1.
• FEN (FIFO Enable): UART has an internal 16-byte FIFO (first in first out) buffer to
store data for transmission to keep the CPU getting interrupted for the reception and
transmission of every byte. Enabling FEN bit, we can write up to16 bytes of data
block into its transmission FIFO buffer and let transfer happen one byte at a time.
There is also a separate 16 byte FIFO for the receiver to buffer the incoming data.
Upon Reset, the default for FIFO buffer size is 1 byte.
• WLEN (Word Length): The number of bits per character data in each frame can be 5,
6, 7, or 8. we use 8 bits for each character data frame. Default world length mode is 5.
• BRK (Send Break): A Low level is continually output on the UnTx signal, after
completing transmission of the current character. For the proper execution of the
break command, software must set this bit for at least two frames (character periods).
• PEN (Parity Enable): Parity is enabled and parity bit is added to the data frame by
making PEN = 1. Parity checking is also enabled.
• EPS (Even Parity Select): Odd parity is performed, which checks for an odd number
of 1s when EPS = 0. Even parity generation and checking is performed during
transmission and reception, which checks for an even number of 1s in data and parity
bits when EPS = 1.
UART Data Register (UARTDR):

Figure: UART Date Register (UARTDR)

Data should be placed in data register before transmission. Only lower 8 bits are used.
In a similar way, the received byte should be read and saved in memory before it gets
overwrite by next byte. During reception, we use other four bits (8, 9, 10 and 11) to detect
error, parity etc. Another set of registers are used to check the source of error.
(UARTRSR/UARTRCR)

• OE: Overrun error (OE = 0: No data is lost).

• BE: Break error
• PE: Parity error
• FE: Framing error.
UART Flag Register (UARTFR):
The UART Flag Register holds one byte of data when FIFO buffer is disabled.

Figure: UART Flag Register (UARTFR)

• TXFE (TX FIFO Empty): Transmitter loads one byte for transmission from the FIFO
buffer.
• When FIFO becomes empty, the TXFE is raised. The transmitter then frames the byte
and sends it out via TxD pin bit by bit serially.
• RXFF (RX FIFO Full): When a byte of data is received, byte is placed in Data
register and RXFF (RX FIFO full) flag bit is raised after receiving the complete byte.
• TXFF (TX FIFOI Full): When the transmitter is not busy, it loads one byte from the
FIFO buffer and the FIFO is not full anymore and the TXFF is lowered. We can
monitor TXFF flag and upon going LOW we can write another byte to the Data
register.

UART Transmission
Step to perform UART Transmission:

• Program the RCGCUART register to get clock on UART0.

• Program the RCGCGPIO register to get the clock for PORTA.
• Program UARTCTL to disable UART0.
• Program the integer part and fractional part into baud rate registers: UARTIBRD and
UARTFBRD for UART0.
• Program UARTCC to select the system clock as UART clock.
• Set the bits in UARTLCRH register for 1 stop bit, no interrupt, no FIFO use, and for 8-
bit date size (for UART 0).
• Program TxE and RxE in UARTCTL to enable transmitter and receiver.
• Make PA0 and PA1 pins to use as digital pins.
• Configure PA0 and PA1 pins for UART.
• Loop the program for wait on TxD output. Monitor the TXFF flag bit and when it goes
low, write a data into data register.
UART Reception
Step by Step Execution of UART Reception:
• Program the RCGCUART register to get clock on UART0.
• Program the RCGCGPIO register to get the clock for PORTA.
• Program UARTCTL to disable UART0.
 • Program the integer part and fractional part into baud rate registers: UARTIBRD and
UARTFBRD for UART0.
• Program UARTCC to select the system clock as UART clock.
• Set the bits in UARTLCRH register for 1 stop bit, no interrupt, no FIFO use, and for 8
-bit data size (for UART 0).
• Program TxE and RxE in UARTCTL to enable transmitter and receiver.
• Make PA0 and PA1 pins to use as digital pins.
• Configure PA0 and PA1 pins for UART.
• Loop the program for wait on TxD output. Monitor the TXFF flag bit and when it
goes low, write a data into data register.
• Monitor the RXFE flag bit in UART Flag register and when it goes LOW read the
received byte from Data register and save before it gets overwrite.

Implementing and Programming I2C:

The TM4C123GH6PM controller includes four I2C modules with the following features:
• Devices on the I2C bus can be designated as either a master or a slave
• Supports both transmitting and receiving data as either a master or a slave
• Supports simultaneous master and slave operation
• Four I2C modes
o Master transmit
o Master receive
o Slave transmit
o Slave receive
 • Four transmission speeds:
o Standard (100 Kbps)
o Fast-mode (400 Kbps)
o Fast-mode plus (1 Mbps)
o High-speed mode (3.33 Mbps)
• Clock low timeout interrupt
• Dual slave address capability
• Glitch suppression
• Master and slave interrupt generation
• Master generates interrupts when a transmit or receive operation completes (or aborts
due to an error)
• Slave generates interrupts when data has been transferred or requested by a master or
when a START or STOP condition is detected
• Master with arbitration and clock synchronization, multi-master support, and 7-bit
addressing mode.
I2C Network:
There are four on chip IIC modules in this Tiva microcontroller. The base address of
each IIC module is shown in below table:

Figure: I2C Networking using Tiva microcontroller

Clock should be enabled to IIC module and system control register (SYSCTL)
RCGCI2C needs to be programmed. To enable the clock SYSCTL ->RCGCI2C | = 0x0F will
enable clock to all four modules

Figure: RunMode Clock Gating Control Register (RCGCI2C)

Clock should be enabled to IIC module and system control register (SYSCTL) RCGCI2C
needs to be programmed.
To enable the clock SYSCTL ->RCGCI2C | = 0x0F will enable clock to all four modules.
Clock Speed: I2CMTPR (I2C Master Timer Period) register is programmed to set the clock
frequency for SCL.

Figure: I2C Master Time Period Register

Table: RCG12C Register Description

The formula used to set the clock speed is given below:

SCL_PERIOD = 2 x (1+TPR) x (SCL_LP+ SCL_HP) x CLK_PRD
Where
CLK_PRD: System Clock period
SCL_LP: SCL low period and it is fixed at 6.
SCL_HP: SCL High period and it is fixed at 4.
Finally, the above equation can be written as:
SCL_PERIOD = (20 x (1+TPR)/ System clock frequency
The TPR can be calculated as:
TPR = ((System clock frequency x SCL_PERIOD)/20) - 1)
TPR = (System Clock frequency)/ (20 x I2C clock) - 1
With System clock frequency of 20MHz and with I2C clock is 333 KHz, we get TPR (Timer
period) = 2.
TPR value to generate Standard, Fast and Fast mode plus SCL frequencies is given in below
table:
Table: TPR Values for I2C modes
The HS bit in the I2CMTPR register needs to be set for the TPR value to be used in High-
Speed mode.
Table: TPR Values for High-Speed Mode

I2CMCR (I2C Master Configuration register) is used to configure microcontroller as master

or slave. The description of I2CMCR is below:

Figure: I2C Master Configuration Register

Table: I2CMCR Register Description

Slave Address:
In a master device, the slave address is stored in I2CMSA. Addresses in I2C
communication is 7-bits. I2CMSA stores D7 to D1 bits and LSB of D0 indicate master is
receiver of transmitter.

Figure: I2C Master Slave Address Register

Data Register:
In transmit mode, a byte of data will be placed in I2CMDR (I2C Master Data
Register) for transmission.

Figure: I2C Master Data Register

Control and Status Flag Register:
The I2CMCS (I2C Master Control/Status) register is programmed for both control
and status. I2CMCS register configures the I2C controller operation. The status whether a
byte has been transmitted. That is, transmission buffer is empty and ready to transmit the next
byte. After writing a data into I2C Data register and the slave address into I2C Master Slave
address register, we can configure I2CMCS register for the I2C to start a data transmission
from Master to slave device. Writing 0x07 to I2CMCS register has all the three of STOP = 1,
RUN = 1, and START = 1 in it. To check the status of transmission, we poll the BUSBSY bit
of I2CMCS register. BUSBSY bit goes low after transmission complete. Program should also
check the ERROR bit to confirm that no error has occurred during transmission. For any error
in transmission, detected by transmitter or raised by slave, the ADRACK and DATACK will
be set. The bit ARBLST should be polled, to confirm transmitter has got access to bus and
not lost arbitration.

Figure: I2C Master Control/Status Register

Table: I2C MCS Register Description

Configuring GPIO for I2C Network:
GPIO pins are configured for I2C as follows:
• Enable the clock to GPIO pins by using system control register RCGCGPIO.
• Set the GPIO AFSEL (GPIO alternate function) for I2C pins.
• Enable digital pins in the GPIODEN register.
• I2C signals are assigned to specific pins using GPIOCTL register.

(a) (b)
Figure: Data transmission using (a) Master Single Transmit, (b) Single Master Receive
Implementing and Programming SPI:
Serial peripheral interface (SPI) is a serial communication interface originally
designed by Motorola in late eighties. SPI and I2C came into existence almost at the same
time. Most of the modern day microcontrollers will support SPI protocol. Both SPI and I2C
offer good support for communication with low-speed devices, but SPI is better suited to
applications in which devices transfer data streams. Some devices use the full-duplex mode to
implement an efficient, swift data stream for applications such as digital audio, digital signal
processing, or telecommunications channels, but most off-the-shelf chips stick to half-duplex
request/response protocols.
SPI is used to talk to a variety of peripherals, such a
• Sensors: temperature, pressure, ADC, touchscreens, video game controllers
• Control devices: audio codecs, digital potentiometers, DAC
• Camera lenses: Canon EF lens mount
• Memory: flash and EEPROM
• Real-time clocks
• LCD, sometimes even for managing image data
• Any MMC or SD card
Description: SPI is a synchronous serial communication protocol like I2C, where master
generates clock and data transfer between master and slave happens with respect to clock.
Both master and slave devices will have shift registers connected to input (MISO for master
and MOSI for slave) and output (MOSI for master and MISO for slave) as shown in figure.

Figure: Serial Peripheral Interface

Communication between the devices will start after CS (chip select) pin will go low.
(CS is an active low pin). In SPI, the 8-bit shift registers are used. After passing of 8 clock
pulses, the contents of two shift registers are interchanged. SPI is full duplex communication.
In SPI protocol both master and slaves use the same clock for communication When
CPOL= 0 the idle value of the clock is zero while at CPOL=1 the idle value of the clock is
one.
 CPHA=0 means sample data on the leading (first) clock edge, while CPHA=1 means
sample data on the trailing (second) clock edge. The idle value of the clock is zero the leading
clock edge is a positive edge but if the idle value of the clock is one, the leading clock edge is
a negative edge.
In SPI protocol both master and slaves use the same clock for communication When
CPOL= 0 the idle value of the clock is zero while at CPOL=1 the idle value of the clock is
one.
CPHA=0 means sample data on the leading (first) clock edge, while CPHA=1 means
sample data on the trailing (second) clock edge. The idle value of the clock is zero the leading
clock edge is a positive edge but if the idle value of the clock is one, the leading clock edge is
a negative edge.

Figure: SPI Timing Diagram

Table: SPI Modes

SPI in Tiva Microcontroller:

The TM4C123GH6PM microcontroller includes four Synchronous Serial Interface
(SSI) modules. Each SSI module is a master or slave interface for synchronous serial
communication with peripheral devices that have Freescale SPI, MICROWIRE, or Texas
Instruments synchronous serial interfaces.
The TM4C123GH6PM SSI modules have the following features:
• Programmable interface operation for Freescale SPI, MICROWIRE, or Texas
Instruments synchronous serial interfaces
• Master or slave operation
• Programmable clock bit rate and prescaler
 • Separate transmit and receive FIFOs, each 16 bits wide and 8 locations deep
• Programmable data frame size from 4 to 16 bits
• Internal loopback test mode for diagnostic/debug testing
• Standard FIFO-based interrupts and End-of-Transmission interrupt
• Efficient transfers using Micro Direct Memory Access Controller (μDMA)
• Separate channels for transmit and receive
• Receive single request asserted when data is in the FIFO; burst request asserted when
FIFO contains 4 entries
• Transmit single request asserted when there is space in the FIFO; burst request
asserted
• When four or more entries are available to be written in the FIFO.
Most SSI signals are alternate functions for some GPIO signals and default to be
GPIO signals at reset. The exceptions to this rule are the SSI0Clk, SSI0Fss, SSI0Rx, and
SSI0Tx pins, which default to the SSI function. The AFSEL bit in the GPIO Alternate
Function Select (GPIOAFSEL) register should be set to choose the SSI function.
Each data frame is between 4 and 16 bits long depending on the size of data
programmed and is transmitted starting with the MSB. There are three basic frame types that
can be selected by programming the FRF bit in the SSICR0 register:
• Texas Instruments synchronous serial
• Freescale SPI
• Microwire
For all three formats, the serial clock (SSInClk) is held inactive while the SSI is idle,
and SSInClk transitions at the programmed frequency only during active transmission or
reception of data. The idle state of SSInClk is utilized to provide a receive timeout indication
that occurs when the receive FIFO still contains data after a timeout period.
For Freescale SPI and MICROWIRE frame formats, the serial frame (SSInFss) pin is
active Low, and is asserted (pulled down) during the entire transmission of the frame.
We focus on the SPI features of SSI module. This microcontroller supports four SSI
modules. The SSI modules are located at the following base addresses:
Table: SPI Modules base address

Clock to SSI: RCGCSSI register is used to enable the clock to SSI modules. We need
to write RCGSSI = 0x0F to enable the clock to all SSI modules.

Figure: Synchronous Serial Interface Run Mode Clock Gating Control CRCG (SSI) Register
Configuring the SSI:
SSICR0 (SSI control register 0) is used to configure the SSI. The generic SPI is used
to transfer the byte size of data, the SSI in Tiva microcontroller allows transfer of data
between 4 bits to 16bits.

Figure: SSI Control O Register

Table: SSICRO Register Description

Bit Rate:
SSI module clock source can be either from System Clock or PIOSC (Precision
Internal Oscillator). The selected frequency is fed to pre-scaler before it is used by the Bit
Rate circuitry. The CPSDVSR (CPS Divisor) value comes from the pre-scaler divisor
register. The lower 8 bits of SSICPSR (SSI Clock Prescale) register are used to divide the
CPU clock before it is fed to the Bit Rate circuitry. Only even values can be used for the pre-
scaler since the D0 must be 0. For the pre-scaler register, the lowest value is 2 and the highest
is 254.
The SSICR0 (SSI Control register 0) allows the Bit Rate selection among other
things. The output of clock pre-scaler circuitry is divided by 1 + SCR and then used as the
SSI baud rate clock. The value of SCR can be from 0 to 255. The below formula is used to
calculate the bit rate.
Bit Rate (BR): BR=SysClk/(CPSDVSR × (1 + SCR))

Figure: SSI Clock Prescaler Register

Example:
For a Bit Rate=50 KHz and SCR=03 in SSICR0 register.
The pre-scaler register value for a given system clock frequency of 16MHz, the BR
can be calculated using above formula as:
BR = SysClk / (CPSDVSR × (1 + SCR))
50 KHz = 16 MHz / (X × (1 + 3).
The pre-scaler value is 0x50 in Hex.
SPI module can act like slave or a master. The value in a MS bit in SSI control
register 1 (SSICR1) decide the microcontroller as master or slave. SSE bit in the SSICR1
register is used to enable/ disable the SPI.

Figure: SSI Control 1 Register

Data Register:
The SSIDR is used for both as transmitter and receiver buffer. In SPI handling 8-bit
data, will be placed into the lower 8-bits of the register and the rest of the register are unused.
In the receive mode, the lower 8-bit holds the received data.

Figure: SSI Data Register

Status Flag Register: SSISR is used to monitor transmitter/receiver buffer is empty.

Figure: SSI Status Register

Table: SSI Status Register Description

SPI data Transmission:
To perform SPI data transmission, follow the steps given below:
• Enable the clock to SPI module in system control register RCGCSSI.
• Before initialization, disable the SSI via bit 1 of SSICR1 register.
• Set the Bit Rate with the SSICPSR prescaler and SSICR0 control registers.
• Select the SPI mode, phase, polarity, and data width in SSICR0 control register.
• Set the master mode in SSISCR1 register.
• Enable SSI using SSICR1 register.
• Assert slave select signal.
• Wait until the TNF flag in SSISR goes high, then load a byte of data into SSIDR.
• Wait until transmit is complete that is, transmit FIFO empty and SSI not busy.
• De-assert the slave signal
 What is ISA Bus?

The Industry Standard Architecture or ISA (Pronounced as separate letters or

as eye-sa) bus began as part of IBM's revolutionary PC/XT and PC/AT released in
1981. However, it was officially recognized as "ISA" in 1987 when the IEEE
(Institute of Electrical and Electronics Engineers) formally documented standards
governing its 16-bit implementation. AT version of the bus is called the AT bus
and became a de facto industry standard.

History
ISA stands for Industry standard architecture. It was the original IBM expansion
bus and initially no standard was assigned to it. Its first version was the 8 bit bus
and it ran at the speed of about 7 MHz.
In 1984, with the advent of PCAT (Intel 286), the bus width is increased to 16bits
and the frequency successively 6 to 8 MHz, 8.33 MHz and finally, providing
a theoretical maximum of 16MB /s (in practice only 8 MB/ s as a cycle of two was
used for addressing).
The second generation of PC's used 16 bit ISA expansion bus which also ran at the
same speed i.e. 7 MHz initially. The later cards allow speed of 8.33 MHz for the 16
bit ISA bus. Nowadays the I/O devices are much faster than their speed but still
the ISA connectors are usually included in PC's to make them backward
compatible with the slower ISA cards.
Current motherboards no longer include ISA bus, PCI bus replaced by the faster
and Plug & Play.
ISA bus architecture
ISA bus architecture is the basis of personal computer. 8-bit ISA bus is used in
single user systems with 80386 and 80486 processors. There are 24 address lines
and '16 data lines in it. It operates at 8 MHz and 2 to 8 clock cycles are needed to
transfer data. The data transfer rate of the system is less when 8-bit ISA bus is
used with 32 bit processor having 32 bit address and data bus. So, 16 bit ISA bus is
used to transfer data. Many peripherals such as disk controller, printer, and
scanner can be connected to ISA bus.
 Introduction to PCI protocol
Today’s computer systems, with their emphasis on high resolution graphics, full
motion video, high bandwidth networking, and so on, go far beyond the
capabilities of the architecture that ushered in the age of the personal computer
in 1982. Modern PC systems demand high performance interconnects that also
allow devices to be changed or upgraded with a minimum of effort by the end
user.
In response to this need, PCI (peripheral component interconnect) has emerged
as the dominant mechanism for interconnecting the elements of modern, high
performance computer systems. It is a well thought out standard with a number
of forward looking features that should keep it relevant well into the next
century. Originally conceived as a mechanism for interconnecting peripheral
components on a motherboard, PCI has evolved into at least a half dozen
different physical implementations directed at specific market segments yet all
using the same basic bus protocol. In the form known as Compact PCI, it is having
a major impact in the rapidly growing telecommunications market.
PCI offers a number of significant performance and architectural advantages over
previous busses:
Speed: The basic PCI protocol can transfer up to 132 Mbytes per second, well
over an order of magnitude faster than ISA. Even so, the demand for bandwidth is
insatiable. Extensions to the basic protocol yield bandwidths as high as 512
Mbytes per second and development currently under way will push it to a
gigabyte.
Configurability: PCI offers the ability to configure a system automatically,
relieving the user of the task of system configuration. It could be argued that PCI’s
success owes much to the very fact that users need not be aware of it.
Multiple Masters: Prior to PCI, most busses supported only one “master,” the
processor. High bandwidth devices could have direct access to memory through a
mechanism called DMA (direct memory access) but devices, in general, could not
talk to each other. In PCI, any device has the potential to take control of the bus
and initiate transactions with any other device.
Reliability: “Hot Plug” and “Hot Swap,” defined respectively for PCI and Compact
PCI, offer the ability to replace modules without disrupting a system’s operation.
This substantially reduces MTTR (mean time to repair) to yield the necessary
degree of up-time required of mission-critical systems such as the telephone
network.

PCI Slots and PCI card

PCI Protocol
PCI is a synchronous bus architecture with all data transfers being performed
relative to a system clock (CLK). The initial PCI specification permitted a
maximum clock rate of 33 MHz allowing one bus transfer to be performed every
30 nanoseconds. Later, PCI specification extended the bus definition to support
operation at 66 MHz, but the vast majority of today’s personal computers
continue to implement a PCI bus that runs at a maximum speed of 33 MHz.
PCI implements a 32-bit multiplexed Address and Data bus (AD[31:0]). It
architects a means of supporting a 64-bit data bus through a longer connector
slot, but most of today’s personal computers support only 32-bit data transfers
through the base 32-bit PCI connector. At 33 MHz, a 32-bit slot supports a
maximum data transfer rate of 132 MBytes/sec, and a 64-bit slot supports 264
MBytes/sec.
The multiplexed Address and Data bus allows a reduced pin count on the PCI
connector that enables lower cost and smaller package size for PCI components.
Typical 32-bit PCI add-in boards use only about 50 signals pins on the PCI
connector of which 32 are the multiplexed Address and Data bus. PCI bus cycles
are initiated by driving an address onto the AD[31:0] signals during the first clock
edge called the address phase. The address phase is signaled by the activation of
the FRAME# signal. The next clock edge begins the first of one or more data
phases in which data is transferred over the AD[31:0] signals.
In PCI terminology, data is transferred between an initiator which is the bus
master, and a target which is the bus slave. The initiator drives the C/BE[3:0]#
signals during the address phase to signal the type of transfer (memory read,
memory write, I/O read, I/O write, etc.). During data phases the C/BE[3:0]# signals
serve as byte enable to indicate which data bytes are valid. Both the initiator and
target may insert wait states into the data transfer by deasserting the IRDY# and
TRDY# signals. Valid data transfers occur on each clock edge in which both IRDY#
and TRDY# are asserted.
A PCI bus transfer consists of one address phase and any number of data
phases. I/O operations that access registers within PCI targets typically have only
a single data phase. Memory transfers that move blocks of data consist of
multiple data phases that read or write multiple consecutive memory locations.
Both the initiator and target may terminate a bus transfer sequence at any time.
The initiator signals completion of the bus transfer by deasserting the FRAME#
signal during the last data phase. A target may terminate a bus transfer by
asserting the STOP# signal. When the initiator detects an active STOP# signal, it
must terminate the current bus transfer and re-arbitrate for the bus before
continuing. If STOP# is asserted without any data phases completing, the target
has issued a retry. If STOP# is asserted after one or more data phases have
successfully completed, the target has issued a disconnect.
Initiators arbitrate for ownership of the bus by asserting a REQ# signal to a central
arbiter. The arbiter grants ownership of the bus by asserting the GNT# signal.
REQ# and GNT# are unique on a per slot basis allowing the arbiter to implement a
bus fairness algorithm. Arbitration in PCI is “hidden” in the sense that it does not
consume clock cycles. The current initiator’s bus transfers are overlapped with
the arbitration process that determines the next owner of the bus.
PCI supports a rigorous auto configuration mechanism. Each PCI device includes
a set of configuration registers that allow identification of the type of device (SCSI,
video, Ethernet, etc.) and the company that produced it. Other registers allow
configuration of the device’s I/O addresses, memory addresses, interrupt levels,
etc.
Although it is not widely implemented, PCI supports 64-bit addressing. Unlike the
64-bit data bus option which requires a longer connector with additional 32-bits
of data signals, 64-bit addressing can be supported through the base 32-bit
connector. Dual Address Cycles are issued in which the low order 32-bits of the
address are driven onto the AD[31:0] signals during the first address phase, and
the high order 32-bits of the address (if non-zero) are driven onto the AD[31:0]
signals during a second address phase. The remainder of the transfer continues
like a normal bus transfer.
PCI defines support for both 5 Volt and 3.3 Volt signaling levels. The PCI
connector defines pin locations for both the 5 Volt and 3.3 Volt levels. However,
most early PCI systems were 5 Volt only, and did not provide active power on the
3.3 Volt connector pins. Over time more use of the 3.3 Volt interface is expected,
but add-in boards which must work in older legacy systems are restricted to using
only the 5 Volt supply. A “keying” scheme is implemented in the PCI connectors to
prevent inserting an add-in board into a system with incompatible supply voltage.
Although used most extensively in PC compatible systems, the PCI bus
architecture is processor independent. PCI signal definitions are generic allowing
the bus to be used in systems based on other processor families. PCI includes
strict specifications to ensure the signal quality required for operation at 33 and
66 MHz. Components and add-in boards must include unique bus drivers that are
specifically designed for use in a PCI bus environment. Typical TTL devices used in
previous bus implementations such as ISA and EISA are not compliant with the
requirements of PCI. This restriction along with the high bus speed dictates that
most PCI devices are implemented as custom ASICs.
The higher speed of PCI limits the number of expansion slots on a single bus to no
more than 3 or 4, as compared to 6 or 7 for earlier bus architectures. To permit
expansion buses with more than 3 or 4 slots, the PCI SIG has defined a PCI-to-PCI
Bridge mechanism. PCI-to-PCI Bridges are ASICs that electrically isolate two PCI
buses while allowing bus transfers to be forwarded from one bus to another. Each
bridge device has a “primary” PCI bus and a “secondary” PCI bus. Multiple bridge
devices may be cascaded to create a system with many PCI buses.


 ISA vs. PCI

One of the most advantageous features of personal and business computers is

their flexibility and expandability. Expansion cards, input/output cards and other
hardware upgrades that use the ISA or PCI protocol allow users to customize their
computers to meet their specific needs without having to pay for features they
don’t want or need. This article provides a brief background on ISA and the latest
standard in I/O cards, PCI.

History of ISA

The ISA (Industry Standard Architecture) port has been nearly as long as the PC
itself. Created in 1981 and updated in 1983, the ISA standard served as an
interface between add-on cards and motherboards. ISA proved to be a harbinger
of an explosion in consumer add-on component demand. While other standards
were produced, e.g., AGP and VLB, ISA endured as the most supported and
utilized I/O standard. This was helped along due heavy investment by industry
and military institutions. Consequently, though practically extinct on PCs and
laptops, motherboards are still produced with ISA. Many specialized industry and
military situations still require the old standby, ISA. ISA has also proven to be a
reliable standard that has been leveraged by subsequent technologies. All
modern internal hard drives use some variant of the specifications.

History of PCI

PCI (Peripheral Component Interconnect) was created in 1990 by Intel researchers

as a replacement for VLB (VESA Local Bus). It first gained popularity for use in
server stacks and towers. However, even with its improvements over VLB, it did
not gain significant market share in the consumer sector until 1994, with the
introduction of Pentium PCs. In 1995, it replaced NuBus as Apple’s choice for
expansion. Since then, PCI has undergone a number of version upgrades, with PCI
1.0 giving way to PCI 2.0 and finally, in 2004, PCI-E was introduced. PCI-E
represents a significant step away beyond PCI 1.0—in fact, PCI-E is not backwards
compatibility with PCI 1.0 and PCI 2.0 ports. As such, PCI and PCI-E still co-exist on
many motherboards. Mini-PCI-E has made strides in replacing PCI, and is expected
to overtake PCI-E in the near future.

ISA and PCI Compared

For many years, ISA and PCI were equivalents. Because PCI was introduced as a
complement to, rather than a direct competitor to ISA, it is not uncommon for
motherboards to have both ISA and PCI ports. ISA, at least for a time, was
concurrent with the PCI standard. ISA would give better performance in some
areas, while PCI yielded better performance in other areas.

In physical appearance the ISA and PCI ports are vastly different. The ISA is longer
(by about two inches), and thus the I/O cards that connect via ISA tend to be
bulkier as well. Their differences do not stop there. PCI is a significantly faster (in
theory) bus. PCI has double (or in rare instances, quadruple) the bit-width,
resulting in faster data transfer.

When placed head-to-head, PCI is definitely the better and faster option. Which is
to be expected, considering PCI is a full ten years newer. While, in 2010, ISA is
practically obsolete and PCI is well on its way to extinction as PCI-E and Mini-PCI-E
gain steam, they are still in use by many consumers and industries. ISA and PCI
made a significant impact on the computer industry.

ISA: The 16-bit ISA interface is defined by the IBM PC/AT and it is also called the
AT Bus. Its data transfer rate is only 8.33MHz which is 16.66Mbytes/s (8.33MHz *
2 bytes). And the most significant feature of the ISA interface is that it cannot
support PnP (Plug and Play) function, so we have to configure the setting in the
software to make sure it is corresponding to the setting on the hardware. By the
way, since the performance and transfer quality of the ISA bus are worse than the
PCI bus, it is replaced by the PCI, AGP, and USB interface gradually.

PCI: The “Peripheral Component Interconnect” interface which means PCI is the
most common interface in modern computer. It had displaced the ISA bus as the
standard expansion bus. Compare to the ISA bus, there are several superiorities
for the PCI bus. For instance, the data transfer rate for the 32-bit PCI standard bus
can be as high as 133Mbytes/s (33MHz), and the PCI bus can support PnP function
so that the system will configure the device setting automatically. Besides, most
of the PCI bus can support either 5V or 3.3V power suppliers (lower than ISA bus)
which we usually call the “Universal Bus”.
 What is FireWire?

FireWire 400 sockets

FireWire is a method of transferring information between digital devices,

especially audio and video equipment. Also known as IEEE 1394, FireWire is fast --
the latest version achieves speeds up to 800 Mbps. At some time in the future,
that number is expected to jump to an unbelievable 3.2 Gbps when
manufacturers overhaul the current FireWire cables.

You can connect up to 63 devices to a FireWire bus. Windows operating systems

(98 and later) and Mac OS (8.6 and later) both support it.

Let's say you have your digital camcorder connected to your home computer.
When your computer powers up, it queries all of the devices connected to the bus
and assigns each one an address, a process called enumeration. FireWire is plug-
and-play, so if you connect a new FireWire device to your computer,
the operating system auto-detects it and asks for the driver disc. If you've already
installed the device, the computer activates it and starts talking to it. FireWire
devices are hot pluggable, which means they can be connected and disconnected
at any time, even with the power on.

FireWire Specifications
The original FireWire specification, FireWire 400 (1394a), was faster
than USB when it came out. FireWire 400 is still in use today and features:

 Transfer rates of up to 400 Mbps

 Maximum distance between devices of 4.5 meters (cable length)
The release of USB 2.0 -- featuring transfer speeds up to 480 Mbps and up to 5
meters between devices -- closed the gap between these competing standards.
But in 2002, FireWire 800 (1394b) started showing up in consumer devices, and
USB 2.0 was left in the dust. FireWire 800 is capable of:

 Transfer rates up to 800 Mbps

 Maximum distance between devices of 100 meters (cable length)
The faster 1394b standard is backward-compatible with 1394a.

In the next section, we'll get deeper into the FireWire vs. USB debate.

The key difference between FireWire and USB is that FireWire is intended for
devices working with a lot more data -- things like camcorders, DVD players and
digital audio equipment. FireWire and USB share a number of characteristics but
differ in some important ways.

Implementing FireWire costs a little more than USB, which led to the adoption of
USB as the standard for connecting most peripherals that do not require a high-
speed bus.

Speed aside, the big difference between FireWire and USB 2.0 is that USB 2.0
is host-based, meaning that devices must connect to a computer in order to
communicate. FireWire is peer-to-peer, meaning that two FireWire cameras can
talk to each other without going through a computer.

FireWire Cables and Connectors

FireWire devices can be powered or unpowered. FireWire allows devices to draw

their power from their connection. Two power conductors in the cable can supply
power (8 to 30 volts, 1.5 amps maximum) from the computer to an unpowered
device. Two twisted pair sets carry the data in a FireWire 400 cable using a 6-pin
configuration.
FireWire adapter cable (9-pin configuration on left)
PHOTO COURTESY HSW SHOPPER

Some smaller FireWire-enabled devices use 4-pin connectors to save space,

omitting the two pins used to supply power.

FireWire 800 cables use a 9-pin configuration. Six of those pins are the same as
the six pins in the 1394a connector (shown above). Two of the added pins provide
a "grounded shield" to protect the other wires from interference, and the third
added pin does nothing at this time [ref].

Because FireWire 800 is backward-compatible with FireWire 400, there are a

variety of adapters available to facilitate the combination of both standards on
the same bus. There are also two types of FireWire 800 ports available: a
"bilingual" port accommodates both FireWire standards, while a b-only port
accepts only a FireWire 800 connector.

Sending Data via FireWire

FireWire uses 64-bit fixed addressing, based on the IEEE 1212 standard. There are
three parts to each packet of information sent by a device over FireWire:
 A 10-bit bus ID that is used to determine which FireWire bus the data came
from
 A 6-bit physical ID that identifies which device on the bus sent the data
 A 48-bit storage area that is capable of addressing 256 terabytes of
information for each node
The bus ID and physical ID together comprise the 16-bit node ID, which allows for
64,000 nodes on a system. Data can be sent through up to 16 hops (device to
device). Hops occur when devices are daisy-chained together. Look at the
example below. The camcorder is connected to the external hard drive connected
to Computer A. Computer A is connected to Computer B, which in turn is
connected to Computer C. It takes four hops for Computer C to access the
camera.

Assuming all of the devices in this setup are equipped with FireWire 800, the
camcorder can be up to 400 meters from Computer C.

Now that we've seen how FireWire works, let's take a closer look at one of its
most popular applications: streaming digital video.

FireWire and Digital Video

FireWire really shines when it comes to digital video applications. Most digital
video cameras or camcorders now have a FireWire plug. When you attach a
camcorder to a computer using FireWire, the connection is amazing.
An important element of FireWire is the support of isochronous devices.

The ISOCHRONOUS (ISOC) format for data transmission is a procedure or protocol

in which each information CHARACTER or BYTE is individually synchronized or
FRAMED by the use of Start and Stop Elements, also referred to as START BITS and
STOP BITS.

In isochronous mode, data streams between the device and the host in real-time
with guaranteed bandwidth and no error correction. Essentially, this means that a
device like a digital camcorder can request that the host computer allocate
enough bandwidth for the camcorder to send uncompressed video in real-time to
the computer. When the computer-to-camera FireWire connection enters
isochronous mode, the camera can send the video in a steady flow to the
computer without anything disrupting the process.