A PROJECT REPORT ON

“Universal Asynchronous Receiver and Transmitter”

(UART)

A Project report submitted in partial fulfilment of the

requirementfor the award of the degree of

MASTER OF TECHNOLOGY
IN

VLSI DESIGN

Submitted by

CHINNAPULLAIAHGARI SUCHITHA 21MVD7005

Submitted to
Dr. Nalluri Purnachand
Associate Professor,
School of Electronics Engineering (SENSE).
VIT_AP.
 Universal Asynchronous Receiver and Transmitter
(UART)

ABSTRACT:

Now a days, all the computers and microcontrollers have several serial data ports used to
communicate with serial input/output devices such as keyboards and serial printers. By using
a modem connected to a serial port serial data can be transmitted to and received from a remote
location via telephone line. The serial communication interface, which receives and transmits
the serial data is called Universal Asynchronous Receiver-Transmitter (UART). RxD is the
receiver data signal and TxD is transmitted data signal. In this project UART is implemented
using vivado tool. The VHDL code for UART transmitter module and receiver module along
with their test bench codes are written and simulated using behavioural model.

INTRODUCTION:
An Universal Asynchronous Receiver and Transmitter (UART) is an integrated circuit which
is programmed to control a computer’s interface to its attached serial devices. Specially, it
provides the system with the RS-232C Data Terminal Equipment (DTE) interface, enabling it
to talk to and exchange data with modems and some other serial devices.

UART is the combination of hardware used for serial communication between computer and
any other peripheral devices. As we know, the processing of data in personal computers or any
other peripheral devices is in parallel form as it ensures speed. But the data communication in
these systems is in serial form, so first the data in parallel form is to be converted to serial form.
To do this process, UART is responsible for breaking parallel data into serial form and again
convert it to parallel form at the receiver end.

UART is called ‘Universal’ because the data frame and transmission speed can be configured
as per the requirement. And ‘Asynchronous’ as the transmitter and receiver are not
synchronized by a clock signal. UART needs two signals rx_data and tx_data. Tx_data is
output of the UART and Rx_data is input to UART. In UART, it consists of two extra bits start
and stop bit. When data is sent ‘start bit’ is inserted at the beginning of the data frame and stop
bit is inserted at the end of the data frame. The start bit sends a signal to the receiver telling
that the data bits are to be sent and force the clock to synchronize with the transmitter clock.
After adding the start bit, the data bits are sent one by one with first sending LSB and then
remaining bits. In receiver, the data bits are counted bit by bit using the counter. After every
data bit is received it is converted into parallel form and transmitted to other peripheral devices.

Fig. 1.1 Basic data frame of UART

The clock synchronization is absent between transmitter and receiver. To synchronize

transmitterand receiver start bit and stop bit is used. UART design for FPGA can act as an
interface for FPGA based embedded system which used soft core processors. This reduces
external routing problems and cost as FPGA contains huge number of logic gates unused.

UART provides the basic operations as:

• Converts the bytes it gets from the computer along parallel circuits to a single serial bit
stream for outbound transmission.
• For inbound transmission, converts the serial bit stream to the bytes that the system
handles.
• Adds a parity bit after selection in outbound and helps to strip them inbound
transmissions.
• Handles interrupts from keyboard and mouse (which are serial devices with special
ports.

LITERATURE SURVEY:
An electronic system requires a medium for communicating with the external world.
It can transfer data to another device, sending or receiving commands or just for debugging
purpose. The most common interface used is UART. As UART works on serial transmission
concept. In early days RS232 interface where used to connect serial port. But now many PC
you will come across has no serial port, so it is commonly implemented using USB, however
transmission concept is same. In UART main tasks are firstly to convert parallel data coming
from data bus in serial form. Then transmitting the serial data, finally after receiving data
converting it again into parallel form.

UART is used for serial communication. The UART has 3 main blocks transmitter
receiver and baud rate generator. The first UART was designed by Western Digital in 1971.
The first UART is designed by Gordon Bell for PDP series of computers. The main innovation
was this UART was using sampling to convert signal to digital domain, providing more steady
timingthan previous telegraphic circuits. To reduce cost of wiring and other components, DEC
shortened the line unit design into a single chip, this was first UART.

In 1980s National Semiconductor 8250 UART were used. 8250 UART has an on-chip
programmable bit rate generator which allowed to transmit data at any frequency. These UART
were used in IBM PC5150. To avoid problem such as interrupts and to increase efficiency,
Intel designed a UART 82510 which has two independent 4-byte FIFOs. Theyintroduced this
UART in 1993. It allowed operation up to 288 Kbit/s. After Intel’s UART many companies
designed various UART with different capacities of FIFO buffers, and different speed of
transmission. Further, NXP Semiconductor introduced dual UART (DUART), comprising of
two channels for communication, control registers and counter/timer. The channels are
independently programmable and supports independent transmission and reception. Some dual
UART models are SCC2692, SC26C92, SC28L92, etc. By mounting the dual UART in
common package NXP also designed Quad UART and Octal UART.

Concept of Project:
Before starting the project, one should look upon the pre-requirements needed for their
project. In this project, pre-requirements for UART Implementation using FPGA includes the
study of serial communication, how data is transferred from peripheral devices to computer
and vise-versa. UART transmitter starts the transmission by taking a data frame in parallel form
and advising the UART to transmit the data frame in a serial form. Similarly, the receiver must
detect transmission and receive the data in serial form, remove the start bit and stop bit, and
storethe data frame in parallel form. As the project states, UART is Universal Asynchronous
ReceiverTransmitter, we should know the difference between synchronous and asynchronous
system. There are some main terms that we should study before starting the project work and
the main terms includes UART, baud rate, data frame, etc. We should study the main block of
UART separately - transmitter, receiver and baud rate generator. As this will have registers,
flip flops, latches, counters and others one should know Area optimization technique so that
less amount of area must be used on the board. Now, we will study some concepts that we need
in this project.

What is UART?

UART stands for Universal Asynchronous Receiver Transmitter which is a serial

communication interface protocol. UART sends and receives data in the form of chunks or
packets which are known as “transmission characters”. There are two types of communications
in UART, half duplex and full duplex communications. In full duplex, both ends can
communicate with each other simultaneously. For example, Telephone; users at both ends can
speak and listen to each other simultaneously. With reference to UART, in full duplex
communication one end can transmit as well as receive the bits. In half duplex system, both
ends communicate each other but one user at a time. For example, walkie-talkie; in which one
user speaks and other only listen and vice-versa. Half duplex is used to conserve bandwidth.
In UART at a time one end can be active either transmitting or receiving end.

Synchronous and Asynchronous transmission:

In synchronous transmission, data is transmitted in form of packets or frames. Synchronous

transmission follows full duplex type of communication. There is synchronization between
transmitter and the receiver. In synchronous transmission, there is no gap between two data
frames. It is more efficient and trustworthy to send large data. The transmission is coordinated
with one or more clock signal in synchronous transmission.

In asynchronous transmission, data is transmitted in form of byte or characters. Asynchronous

transmission follows half duplex type of communication. Synchronization is not required. In
this transmission, start bit and stop is added to the data frame. Therefore, there is some gap
between two data frames. The transmission is coordinated with no clock signal, asynchronous
 transmission does not depend on any clock signal.
Synchronous transmission Asynchronous transmission

1. Data is transmitted in the form of 1. Data is transmitted in the form of byte

packets or frames or character.

2. Synchronous transmission is much 2. Asynchronous transmission is slower

faster than asynchronous than synchronous.
3. Synchronous transmission is not 3. Asynchronous transmission iseconomical.
economical.

4. There is constant time interval in 4. There is no constant time interval in

transmission. transmission.

5. There is no gap between two data frames 5. There is gap between data frames as
start bit and stop bit is added to the frame.

Table: synchronous and asynchronous transmission

Serial Communication:
In serial communication, the data is sent one bit at a time, sequential over the communication
channel. It is opposite to parallel communication, where all the data bits are sent all at a time.
In serial communication, data is in binary pulse form. Binary ‘1’ represents high logic and
binary ‘0’ represent low logic. Serial communication can be of many types depending on the
type of transmission mode. It has 3 transmission modes, simplex mode, half duplex, full duplex.

Simple Mode:

The simplex mode is one-way communication technique. Only one user (either the
transmitter or receiver is active at a time). If transmitter transmits, the receivercan
also accept. For example, Radio and Television.

Half Duplex:
Both transmitter and receiver in half duplex mode are active but one at a time that means if
transmitter transmits, the receiver can accept the data but cannot send and vice- versa. For
example, internet. If a user sends a request for any website, the web server processes the
 application and sends back the information.
Full Duplex:
Full duplex mode is widely used communication mode in the world. In this mode,
transmitter and receiver can transmit and receive simultaneously. For example,
smartphone.

Baud Rate and Bit Rate:

Baud rate is defined as the number of signal units per second. Whereas, Bit rate is the
number of bits transmitted per second. The formula which relates both the terms is given
below:

Bit rate = Baud rate x the number of bits per baud.

Bit rate Baud rate

Number of bits transmitted per second. Number of signal transmitted units per second.

Also called as number of bits travelled per Also called as number of characters travelled
second per second
Bit rate emphasize the computer efficiency Baud rate emphasize data transmission.

The formula for bit rate is: The formula for baud rate is:
= baud rate x number of bits = bit rate / number of bits per baud
persecond
UART Architecture:

Fig. Architecture of UART

UART architecture consists of three main blocks Transmitter, Receiver and Baud rate
generator. The data is taken from the computer or the peripheral devices. Below are
the block level micro-architecture and working of the modules.

Transmitter module:

All the operations in transmitter are with respect to clock which runs on multiple baud
rates. The transmitter converts the 8-bit parallel data into serial data and adds start bit at
start of the data frame and stop bit at the end of the data frame. In transmitter, the 8-bit
data from data bus is loaded to transmitter hold register (THR), it is an 8-bit register to
store the data parallelly through d_in pin. Then after all the data is loaded in THR then
data is loaded in Transmitter shift Register (TSR) parallelly. In TSR, start bit and stop
bit is added to the data bits, transmitter shift register is of 10-bit size. TSR convert
parallel data into serial form and then data is transmitted serially bit by bit through
tx_out. While transmitting data LSB of the data bit is transmitted first and then
remaining data is transmitted and last stop bit is transmitted to stop the transmission.
The clock given to transmitter block isthe baud clock (bclk) on which the baud rate is
set. Counter is used in TSR to count the data bits. Until and unless all the data is
transmitted no other data can be stored in hold register.

Fig. Micro-architecture of transmitter module

Table: Pin description of transmitter module

Pins Width I/O Description

d_in 8 bits Input Input to the transmitter form data bus.

tx_status 1 bit Outpu Shows the status of the transmitter module.

t
tx_data 1 bit Outpu Sends data to receiver bit by bit.
t
bclk 1 bit Input Input clock to transmitter module from
baud rategenerator.
Transmitter is designed based of FSM used as given below:

Fig. FSM for transmitter module.

Transmitter FSM have four states they are named as follows:

• Idle State.
• Start State.
• Data State.
• Stop State.

In transmitter FSM first state is idle state in which transmitter remains in idle condition
means nothing will going to happen in this state. But when desired input is given to this
state then there is change of state takes place. Here when valid start bit (logic ‘0’) is
given. as input then state changes from idle to start state means in idle state there is
a detection ofvalid start bit. When invalid input is given in idle state then transmitter
remains in same state i.e. idle state. Output of this state is logic ‘0’ for valid input (logic
‘0’).

When transmitter is in start state input is logic ‘0’ which is valid so there is change of
state from the start state to data state. If input is not logic ‘0’ then transmitter goes in
idle state. Start state will not change to data state until valid start bit is detected. In data
state transmitter sends frame sequence given to the input of transmitter and when
complete frame sequence is transmitted then state changes to stop state otherwise
transmitter will remain in same state until the complete transmission of frame sequence.

Stop state of transmitter will detect stop bit (logic ‘1’). If there will be any error in stop
bit, then transmitter remains in stop state only otherwise it will again go to idle state to
detect anotherstart bit. The above process continues till required number of bits will be
transmitted.

Receiver Module:
Block level micro-architecture of receiver module is given below,

Fig: Micro-architecture of receiver module.

The receiver module is complex than the transmitter module. It runs 4 X baud rate faster
than transmitter. The serial data is received from transmitter through rx_data pin 1-bit
at a time serially. Then, rx_data pin jumps into logic 0 from logic 1 indicating beginning
of the data frame. The start bit is identified by change in level from high to low level
and stop bit by change in the level from low to high. After identifying start bit, all the
data bits are sampled and counted using the bit counter generated in the receiver. The
counter counts the positive edge of the clock at every riding edge of the clock 1 bit is
counted. When count equals to 8 then it says all bits are received and stored in an 8 bit
Receiver Shift Register (RSR) and the data bits are converted into parallel data. Then it
sends the data bits to Receiver Hold Register (RHR) which is also an 8 bit register. RSR
send only data bits to RHR, start bit and stop bit is not sent. Then the parallel data is sent
to the data bus or peripheral device.

Table: Pin description for receiver module.

Pin Width I/O Description

rx_data 1 bit Input Input data from transmitter.

bclkx8 1 bit Input Input clock to receiver from baud rate generator.
Receiver clock is 8 times faster than transmitter
clock.
rx_status 1 bit Output Shows status of receiver block.

d_out 8 bit Output Sends output data to PC or peripheral devices.

Receiver is designed based on FSM used as given below

Receiver FSM also have same four states like transmitter they are named as follows:

• Idle State.
• Start State.
• Data State.
• Stop State.

In receiver FSM first state is idle state in which receiver remains in idle condition means
nothing will going to happen in this state. But when desired input is given to this state
then there is change of state takes place. Here when valid start bit (logic ‘0’) detected
idle state changes from idle to start state. When wrong bit is received in idle state
then receiver remains in idlestate. Output of this state is logic ‘0’ for valid input (logic
‘0’).

When receiver is in start state then it will not detect any bit because valid bit is already
detected in idle state, so receiver simply changes it’s states from start to data state. In
data state,if valid frame sequence received then there will be change in state from data
to stop state otherwise receiver will remain in same state until the arrival of valid data.

Stop state of receiver will detect stop bit (logic ‘1’). If there will be any error in stop bit,
then receiver remains in stop state only otherwise it will again go to idle state to detect
another start bit. The above process continues till required number of bits will be
received. Both transmitter and receiver works on mealy machine means output depends
on state as well asinput. There is change in output when any one of them changes (state
or input).

Baud Rate Generator Module:

Block level micro-architecture of baud rate generator is given below:

Fig: Micro-architecture of baud rate generator

 Table: Pin description for baud rate generator.

Pin Width I/O Description

sys_clk 1 bit Input Input clock to baud rate generator from FPGA
board.
sel_baud 2 bits Input Select lines to select different baud rates.

bclk 1 bit Output Output clock given to transmitter module.

bclk x 8 1 bit Output Output clock given to receiver module.

Baud rate generator is also used to divide frequency. By using given clock frequency
and requested baud rate we can calculate the frequency factor. In baud rate generator,
the input to the generator is system clock which is available on FPGA board in our
project we used 50 MHz. The clock is first divided by 8 by using the clock divider to
get the data bits on the positive edge of the clock. Then a parameterized counter is used
to count the data bits and the counter runs on the divided clock. The output of the
parameterized counter is divided into different divisors of different baud rates to run the
process on these baud rates. The divisor is found by the formula proposed as,

Divisor = sys. Clock / (8 x baud rate)

A specific baud rate is selected from a 4x1 multiplexer according to the select lines.
Then the output of this multiplexer is given to transmitter and receiver on which they
run. The receiver baud clock is 8 times faster than transmitter baud clock. To get this
difference in clock speeds the output of the multiplexer is first given to divide by 8 block
and then given to transmitter block and the output of the multiplexer is directly given to
receiver.
Fig: Micro-architecture UART
PROPOSED WORK:
VHDL CODE:
UART Transmitter:

module uart_tx(
input clk,
input rst_n,
input en_i,
input [7:0] data_i,
output reg tx_o,
output reg tx_done_o
);

localparam s_idle = 5'b00001,

s_start = 5'b00010,
s_wr = 5'b00100,
s_stop = 5'b01000,
s_done = 5'b10000;

//This is for simulation

localparam t_1_bit = 9;

reg en_cnt;
reg [15:0] cnt;
reg [4:0] state;
reg [7:0] data_r;
reg [7:0] tx_bits;

always @(posedge clk or negedge rst_n)

if(!rst_n)
cnt <= 16'd0;
else if ((en_cnt == 0) || (cnt == t_1_bit))
cnt <= 16'd0;
else
cnt <= cnt + 16'd1;

always @(posedge clk or negedge rst_n)

if (!rst_n) begin
state <= s_idle;
tx_o <= 1'b1;
data_r <= 8'd0;
en_cnt <= 1'b0;
tx_bits <= 8'd0;
tx_done_o <= 1'b0;
end else begin
case(state)
s_idle:
begin
data_r <= data_i;
tx_bit <= 8'b0;
 tx_done_o <= 1'b0;

if(en_i == 1) begin
en_cnt <= 1'b1;
state <= s_start;
end else begin
en_cnt <= 1'b0;
state <= s_idle;
end
end
s_start:
if (cnt == t_1_bit) begin
state <= s_wr;
end else begin
tx_o <= 0;
state <= s_start;
end

s_wr:
if (cnt == t_1_bit) begin
if (tx_bits == 8'd7)
state <= s_stop;
else begin
tx_bits <= tx_bits + 8'd1;
state <= s_wr;
end
end else begin
tx_o <= data_r[tx_bits];
state <= s_wr;
end

s_stop:
if (cnt == t_1_bit) begin
state <= s_done;
end else begin
tx_o <= 1'b1;
state <= s_stop;
end

s_done:
begin
en_cnt <= 1'b0;
tx_done_o <= 1'b1;
state <= s_idle;
end

default: state <= s_idle;

endcase
end
endmodule
Test bench for transmitter:
`define clk_period 20

module tb_uart_tx();

reg clk, rst_n, en_i;

reg [7:0] data_i;
wire tx_done_o;
wire tx_o;

uart_tx UART_TX(
clk,
rst_n,
en_i,
data_i,
tx_o,
tx_done_o
);

initial clk = 1;
always #(`clk_period/2) clk = ~clk;

initial begin
rst_n = 1;
en_i = 0;
data_i = 0;

#(`clk_period);

rst_n = 0; //begin to reset;

#(`clk_period);

rst_n = 1; //finish reset;

#(`clk_period);

data_i = 8'h55;
en_i = 1;
#(`clk_period);

en_i = 0;
#(`clk_period * 200);

$stop;
end
endmodule
UART RECEIVER:
`timescale 1ns / 1ps

module uart_rx(
input clk,
input rst_n,
input rx_i,
output reg [7:0] data_o,
output reg rx_done_o
);

localparam s_idle = 5'b00001,

s_start = 5'b00010,
s_rd = 5'b00100,
s_stop = 5'b01000,
s_done = 5'b10000;

localparam t_1_bit = 9;
localparam t_half_1_bit = 4;

reg en_cnt;
reg [15:0] cnt;
reg [4:0] state;
reg [7:0] rx_bits;

always @(posedge clk or negedge rst_n)

if(!rst_n)
cnt <= 16'd0;
else if ((en_cnt == 0) || (cnt == t_1_bit))
cnt <= 16'd0;
else
cnt <= cnt + 16'd1;

reg rx_0, rx_1, rx_2, rx_3;

always @(posedge clk or negedge rst_n)

if (!rst_n) begin
rx_0 <= 1'b0;
rx_1 <= 1'b0;
rx_2 <= 1'b0;
rx_3 <= 1'b0;
end else begin
rx_3 <= rx_i;
rx_2 <= rx_3;
rx_1 <= rx_2;
rx_0 <= rx_1;
end

wire start_flag;
assign start_flag = rx_0 & rx_1 & (~rx_2) & (~rx_3);

always @(posedge clk or negedge rst_n)

if (!rst_n) begin
state <= s_idle;
en_cnt <= 1'b0;
data_o <= 8'd0;
rx_bits <= 8'd0;
rx_done_o <= 1'b0;
end else begin
case(state)
s_idle:
begin
rx_bits <= 8'd0;
rx_done_o <= 1'b0;

if (start_flag) begin
en_cnt <= 1'b1;
state <= s_start;
end else begin
en_cnt <= 1'b0;
state <= s_idle;
end
end

s_start:
if (cnt == t_half_1_bit)
if (rx_i == 1'b0)
state <= s_rd;
else
state <= s_idle;

s_rd:
if (cnt == t_half_1_bit)
if (rx_bits == 8'd7)
state <= s_stop;
else begin
data_o[rx_bits] <= rx_i;
rx_bits <= rx_bits + 8'd1;
state <= s_rd;
end

s_stop:
if (cnt == t_half_1_bit)
begin
if (rx_i == 1)
state <= s_done;
else
state <= s_idle;
end
 s_done:
begin
en_cnt <= 1'b0;
rx_done_o <= 1'b1;
state <= s_idle;
end
default: state <= s_idle;
endcase
end
endmodule

Test bench for receiver:

`timescale 1ns / 1ps

`define clk_period 20

module tb_uart_rx();

reg clk, rst_n, rx_i;

wire [7:0] data_o;
wire rx_done_o;

uart_rx UART_RX(
clk,
rst_n,
rx_i,
data_o,
rx_done_o
);

initial clk = 1;
always #(`clk_period/2) clk = ~clk;

initial
begin
rst_n = 1;
rx_i = 1;
#`clk_period;

rst_n = 0;
#`clk_period;

rst_n = 1;
#(`clk_period * 10);

rx_i = 0; //start bit

#(`clk_period * 10);
 rx_i = 1; //bit 0
#(`clk_period * 10);

rx_i = 1; //bit 1
#(`clk_period * 10);

rx_i = 0; //bit 2
#(`clk_period * 10);

rx_i = 0; //bit 3
#(`clk_period * 10);

rx_i = 1; //bit 4
#(`clk_period * 10);

rx_i = 1; //bit 5
#(`clk_period * 10);

rx_i = 0; //bit 6
#(`clk_period * 10);

rx_i = 0; //bit 7
#(`clk_period * 10);

rx_i = 1; //stop bit;

#(`clk_period * 10);

#(`clk_period * 20);

$stop;
end
endmodule
VHDL SIMULATION:

A. UART TRANSMITTER

Fig: Simulation result of UART Transmitter

B. UART RECEIVER

Fig: Simulation result of UART Receiver

CONCLUSION:

In this project, UART is designed. The language used in thisproject is Verilog descriptive
language to achieve reliable serial data communication. The Transmitter and Receiver module
of the UART are designed and simulated using Vivado tool and the results of UART transmitter
and receiver are verified.