TPS65270

www.ti.com.cn ZHCS270C – AUGUST 2011 – REVISED APRIL 2012

带有集成金属氧化物半导体场效应晶体管 (MOSFET)， ，输入电压范围为

4.5V 至 18V，
，输出电流为 2A/3A 的双路同步降压稳压器
查询样品: TPS65270

1特性
2• 宽输入电源电压范围 • 采用 24 引线耐热增强型超薄小外形尺寸封装
(4.5V-18V) (HSSTOP) (PWP) 和 4mm x 4mm 四方扁平无引
• 0.8V，，±1% 精度基准 线 (RGE) 封装
• 高达 2A（ （降压 1）
）和 3A（
（降压 2）
）最大持续输出
负载电流 应用范围
• 低功耗脉冲跳跃模式可在轻负载时实现高效率 • 数字电视
• 可调开关频率 • DSL 调制解调器
由外部电阻器设定的 300kHz-1.4MHz • 线缆调制解调器
• 针对每个降压的专用启用和软启动 • 机顶盒
• 具有简单补偿电路的峰值电流模式控制 • 车载 DVD 播放器
• 逐周期过流保护 • 家庭网关和访问点网络
• 180° 相移运行可减少输入电容量和电源感应噪声 • 无线路由器

说明/订
订购信息
TPS65270 是一款单片双路同步降压稳压器，此稳压器具有可运行在 5，9，12，或者 15V 总线电压和多种化学类
型电池上的宽输入电压。 这个转换器设计用于在为设计人员提供选项来按照目标应用来优化转换器用法的同时简化
它的应用。

TPS65270 特有一个精准 0.8V 基准并且能够生成高达 15V 的输出电压。每个转换器特有使能引脚，此引脚可实现

对每个通道的专用控制，从而提供电源排序的灵活性。 每个通道的软启动时间可通过选择不同的外部电阻器来调
节。

恒定频率模式峰值电流简化了补偿并提供快速瞬态响应。 逐周期过流保护和断续模式操作在短路或者负载故障条件
下限制 MOSFET 功率耗散。 低侧反向电流保护还能够防止过多吸收电流损坏转换器。

可使用一个外部电阻器将此转换器的开关频率设定在 300kHz 至 1.4MHz 之间。 为了大大降低对输入滤波器的要

求，减轻电磁干扰 (EMI) 以及对输入电容器的需求，两个转换器具有相移为 180° 的时钟信号。

TPS65270 还特有一个轻负载脉冲跳跃模式 (PSM)。 为了实现轻负载下的高效率，PSM 模式可在轻负载时减少系

统输入电源上的功率损失。

TPS65270 采用一个 24 引线耐热增强型 HTSSOP (PWP) 封装和 24 引脚 QFN

4mm x 4mm (RGE) 封装。

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2 PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date. Copyright © 2011–2012, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not English Data Sheet: SLVSAX7
necessarily include testing of all parameters.
TPS65270
ZHCS270C – AUGUST 2011 – REVISED APRIL 2012 www.ti.com.cn

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

TYPICAL APPLICATION

C8
47nF
1 24 C9
ENABLE Buck 1 EN1 BST1
10uF
25V
2 23
FB1 FB1 VIN1 R4b
FB1
32.4K

3 22 VIN
C3 R1 SS1 LX1
2.2nF 10K C10 R4a C11
C2 22uF 40.2K 82pF
10nF 4 21
COMP1 LX1 1.8V/2A

C17 5 20 L1
100pF LOW_P GND 4.7uH
(optional) C4
10uF
6 19
VCC GND

TPS65270
7 18
AGND GND
R3
C16 383K 8 17
100pF ROSC GND L2
(optional) 4.7uH

9 16
COMP2 LX2 1.2V/3A
C6
R5a C15
10nF C14
C5 R2 10 15 40.2K 82pF
22uF
2.2nF 10K SS2 LX2
VIN
11 14 R5b
FB2

FB2 VIN2 80.6K FB2

C13
10uF
12 13
25V
ENABLE Buck 2 EN2 BST2
C12
47nF

C5 R3 C3
2.2nF 383K C4 2.2nF
C16 10uF C16
100pF 100pF
(optional) R2 R1 (optional)
10K 10K
24

23

22

21

20

19
COMP2

COMP1
ROSC

AGND

VCC

LOW_P

C6 C2
10nF 10nF
1 18
SS2 SS1

2 17
FB2 FB1

3 16
ENABLE Buck 1 EN2 EN1 ENABLE Buck 2
C12 C8
C13 47nF TPS65270 47nF C9
4 15
10uF VIN BST2 BST1 VIN 10uF
25V 25V
5 14
VIN2 VIN1

6 13
L2 LX2 LX1 L1
4.7uH 4.7uH
GND

GND

GND

GND
LX2

LX1

1.2V/3A 1.8V/2A
7

10

11

12

R5a C15 C11 R4a

C14 C10
40.2K 82pF 82pF 40.2K
22uF 22uF

R5b R4b
80.6K 32.4K

2 Copyright © 2011–2012, Texas Instruments Incorporated

 TPS65270
www.ti.com.cn ZHCS270C – AUGUST 2011 – REVISED APRIL 2012

FUNCTIONAL BLOCK DIAGRAM

LOW_P 5 Pre-Regulator, Voltage Reference,

Logic
Current Bias
VCC 6 Internal 23 VIN1
VIN1
LDO

ROSC 8
OSC
o
180

ILIM
24 BST1

SLP CS

S Q
21,22 LX1
Latch VOUT BUCK1
SS1 3
COMP R Q
0.8V EN
EA
FB1 2
FB1
FB1
COMP1 4
19, 20 GND

EN1 1
EN 1 Logic
BUCK 1

12
EN2 Logic
EN2
17,18
9 GND
COMP2 FB2
11
FB2
FB2
10 same as Buck 1 15,16
SS2 VOUT BUCK2
LX2

13
14 BST2
BUCK 2 VIN2
VIN2

AGND 6

Note: Pin numbers in block diagram are for HTSSOP (PWP) 24-pin package.

ORDERING INFORMATION (1)

(2)
TA PACKAGE ORDERABLE PART NUMBER TOP-SIDE MARKING
PWP (R-PDSO-G) TPS65270PWPR TPS65270
–40°C to 85°C
RGE (S-PVQFN-N24) TPS65270RGER or TPS65270RGET TPS65270

(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
web site at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.

Copyright © 2011–2012, Texas Instruments Incorporated 3

TPS65270
ZHCS270C – AUGUST 2011 – REVISED APRIL 2012 www.ti.com.cn

PIN OUT
PWP PACKAGE
(TOP VIEW)

EN1 1 24 BST1

FB1 2 23 VIN1

SS1 3 22 LX1

COMP1 4 21 LX1

LOW_P 5 20 GND

VCC 6 19 GND
Thermal Pad
AGND 7 18 GND

ROSC 8 17 GND

COMP2 9 16 LX2

SS2 10 15 LX2

FB2 11 14 VIN2

EN2 12 13 BST2

Exposed pad must be soldered to PCB for optimal thermal performance.

RGE PACKAGE
(TOP VIEW)
COMP2

LOW_P

COMP1
AGND
ROSC

VCC

24 23 22 21 20 19

SS2 1 18 SS1

FB2 2 17 FB1

EN2 3 16 EN1
Thermal Pad
BST2 4 15 BST1

VIN2 5 14 VIN1

LX2 6 13 LX1

7 8 9 10 11 12
LX1
GND

GND

GND

GND
LX2

Exposed pad must be soldered to PCB for optimal thermal performance.

4 Copyright © 2011–2012, Texas Instruments Incorporated

 TPS65270
www.ti.com.cn ZHCS270C – AUGUST 2011 – REVISED APRIL 2012

TERMINAL FUNCTIONS
NO. NO.
NAME DESCRIPTION
(HTSSOP) (QFN)
Enable for Buck 1. Logic high enables the Buck 1; Logic low disables
Buck 1. If pin is left open a weak internal pull-up to V5V will allow for
EN1 1 16
automatic enable; For a delayed start-up add a small ceramic capacitor
from this pin to ground.
Feedback voltage for Buck 1. Connect a resistor divider to set 0.8 V from
FB1 2 17
the output of the converter to ground.
Soft start input for Buck 1. An internal 5-µA charging current is sourcing to
SS1 3 18 this pin. Connect a small ceramic capacitor to this pin to set the Buck 1
soft start time.
Loop compensation pin for Buck 1. Connect a series RC circuit to this pin
COMP1 4 19
to compensate the control loop of this converter.
Low power operation mode. With active high, Buck 1 and Buck 2 operate
LOW_P 5 20 at pulse skipping mode at light load; active low forces both Buck 1 and
Buck 2 to PWM mode; this pin can’t be left open.
Internal 6.5-V power supply bias. Connect a 10-µF ceramic capacitor from
VCC 6 21
this pin to ground.
AGND 7 22 Analog ground. Connect all GND pins and power pad together.
Oscillator frequency setup. Connect a resistor to ground to set the
ROSC 8 23
frequency of internal oscillator clock.
Loop compensation pin for Buck 2. Connect a series RC circuit to this pin
COMP2 9 24
to compensate the control loop of this converter.
Soft start input for Buck 2. An internal 5-µA charging current is sourcing to
SS2 10 1 this pin. Connect a small ceramic capacitor to this pin to set the Buck 1
soft start time.
Feedback voltage for Buck 2. Connect a resistor divider to set 0.8 V from
FB2 11 2
the output of the converter to ground.
Enable for Buck 2. Logic high enables the Buck 2. Logic low disables
Buck 2. If pin is left open a weak internal pull-up to V5V will allow for
EN2 12 3
automatic enable; For a delayed start-up add a small ceramic capacitor
from this pin to ground.
Bootstrapped power supply to high side floating gate driver in Buck 2.
BST2 13 4 Connect a 47-nF ceramic capacitor from this pin to the switching node pin
LX2.
Input supply for Buck 2. Connect a 10-µF ceramic capacitor close to this
VIN2 14 5
pin.
LX2 15, 16 6, 7 Switching node connecting to inductor for Buck 2.
GND 17, 18, 19, 20 8, 9, 10, 11 Power ground for Buck 1 and Buck 2.
LX1 21, 22 12, 13 Switching node connecting to inductor for Buck 1.
Input supply for Buck 1. Conne ct a 10-µF ceramic capacitor close to this
VIN1 23 14
pin.
Bootstrapped power supply to high side floating gate driver in Buck 1.
BST1 24 15 Connect a 47-nF ceramic capacitor from this pin to the switching node pin
LX1.
Must be soldered to PCB for optimal thermal performance. Have thermal
Thermal Pad
vias on the PCB to enhance power dissipation.

Copyright © 2011–2012, Texas Instruments Incorporated 5

TPS65270
ZHCS270C – AUGUST 2011 – REVISED APRIL 2012 www.ti.com.cn

(1)
ABSOLUTE MAXIMUM RATINGS
over operating free-air temperature range (unless otherwise noted)
Voltage range at VIN1, VIN2, LX1, LX2 –0.3 to 18 V
Voltage range at LX1, LX2 (maximum withstand voltage transient < 10 ns) –1 to 18 V
Voltage at BST1, BST2, referenced to LX1, LX2 pin –0.3 to 7 V
Voltage at VCC, EN1, EN2, COMP1, COMP2, LOW_P –0.3 to 7 V
Voltage at SS1, SS2, FB1, FB2, ROSC –0.3 to 3.6 V
Voltage at AGND, GND –0.3 to 0.3 V
TJ Operating virtual junction temperature range –40 to 125 °C
TSTG Storage temperature range –55 to 150 °C

(1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating
conditions" is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VIN Input operating voltage 4.5 18 V
TA Ambient temperature –40 85 °C

ELECTROSTATIC DISCHARGE (ESD) PROTECTION

MIN MAX UNIT
Human body model (HBM) 2000 V
Charge device model (CDM) 500 V

PACKAGE DISSIPATION RATINGS (1) (2) (3)

TA = 25°C TA = 55°C TA = 85°C
PACKAGE θJA (°C/W) θJC (°C/W)
POWER RATING (W) POWER RATING (W) POWER RATING (W)
PWP 32.6 10 3.07 2.15 1.23
RGE 32.6 10 3.07 2.15 1.23

(1) This assumes a JEDEC JESD 51-5 standard board with thermal vias with High K profile - See Texas Instruments application report
(SLMA002) regarding thermal characteristics of the PowerPAD™ package.
(2) This assumes junction to exposed PAD.
(3) Based on JEDEC 51.5 HIGH K environment measured on a 76.2 x 114 x .6-mm board with the following layer arrangement:
(a) Top layer: 2 Oz Cu, 6.7% coverage
(b) Layer 2: 1 Oz Cu, 90% coverage
(c) Layer 3: 1 Oz Cu, 90% coverage
(d) Bottom layer: 2 Oz Cu, 20% coverage

6 Copyright © 2011–2012, Texas Instruments Incorporated

 TPS65270
www.ti.com.cn ZHCS270C – AUGUST 2011 – REVISED APRIL 2012

ELECTRICAL CHARACTERISTICS
TA = -40°C to 125°C, VIN = 12 V, fSW = 625 kHz (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT SUPPLY
VIN Input Voltage range VIN1 and VIN2 4.5 18 V
IDDSDN Shutdown EN1 = EN2 = 0 V 10 µA
Non switching quiescent power supply VFB1 = VFB2 = 900 mV,
IDDQ_nsw 1 mA
current LOW_P = high
Rising VIN 4 4.20 4.45
UVLO VIN under voltage lockout Falling VIN 3.65 3.85 4.10 V
Hysteresis 0.35
VCC load current = 0 A,
VCC Internal biasing supply 6.25 V
VIN = 12 V
VIN = 5 V,
VCC_drop VCC LDO Drop-Out Voltage 180 mV
VCC load current = 20 mA
IVCC VCC current limit 4.5 V < VIN < 18 V 200 mA
FEEDBACK AND ERROR AMPLIFIER
VIN = 12 V , VCOMP = 1.2 V,
-1% 0.8 1%
TJ = 25°C
VFB Regulated feedback voltage V
VIN = 12 V, VCOMP = 1.2 V,
-2% 0.8 2%
TJ = -40°C to 125°C
VIN = 4.5 V to 18 V,
VLINEREG Line regulation - DC 0.5 %/V
IOUT = 1 A
IOUT = 10 % - 90%
VLOADREG Load regulation - DC 0.4 %/A
IOUT,MAX
Gm_EA Error amplifier trans-conductance -2 µA < ICOMP < 2 µA 130 µs
Gm_SRC COMP voltage to inductor current Gm ILX = 0.5 A 10 A/V
ENABLE, PFM MODE AND SOFT-START
Rising 1.55
VEN EN1 and EN2 pin threshold V
Falling 0.4
Rising 1.55
VPSM PSM low power mode threshold V
Falling 0.4
ISS SS1 and SS2 soft-start charging current 5 µA
OSCILLATOR
FSW_BK Switching frequency range Set by external resistor ROSC 0.3 1.4 MHz
ROSC = 250 kΩ 0.85 1 1.15 MHz
FSW Programmable frequency
ROSC = 500 kΩ 425 500 575 kHz
PROTECTION
ILIMIT1 Buck 1 peak inductor current limit 4.5 V < VIN < 18 V 3.2 A
ILIMIT1_LS1 Buck 1 low side MOSFET current limit 4.5 V < VIN < 18 V 2 A
ILIMIT2 Buck 2 peak inductor current limit 4.5 V < VIN < 18V 4.1 A
ILIMIT1_LS2 Buck 2 low side MOSFET current limit 4.5 V < VIN < 18 V 2 A
MOSFET ON-RESISTANCES
Rdson_HS1 On resistance of high side FET on CH1 BST1 to LX1 = 6.25 V 120 mΩ
Rdson_LS1 On resistance of low side FET on CH1 VIN = 12 V 80 mΩ
Rdson_HS2 On resistance of high side FET on CH2 BST2 to LX2 = 6.25 V 95 mΩ
Rdson_LS2 On resistance of low side FET on CH2 VIN = 12 V 50 mΩ
Ton_min Minimum in time 80 120 ns
THERMAL SHUTDOWN
TTRIP Thermal protection trip point Rising temperature 160 °C
THYST Thermal protection hysteresis 20 °C

Copyright © 2011–2012, Texas Instruments Incorporated 7

TPS65270
ZHCS270C – AUGUST 2011 – REVISED APRIL 2012 www.ti.com.cn

TYPICAL CHARACTERISTICS
TA = 25°C, VIN = 12 V, fSW = 625 kHz (unless otherwise noted)
1.85 1.25

1.24

1.83 PWM, Vout1, Vin = 12 V 1.23

PWM, Vout2, Vin = 12 V
1.22

1.81 1.21

1.2
PSM, Vout2, Vin = 12 V
PSM, Vout2, Vin = 12 V
1.79 1.19

1.18
`

1.77 1.17

1.16

1.75 1.15
0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3 3.5 4

Figure 1. Load Regulation Figure 2. Load Regulation

Buck 1 at 1.8 V, 1% Resistors Buck 1 at 1.2 V, 1% Resistor s

100 95
VI = 4.5 V
90 90

80 VI = 15 V 85
VI = 12 V
70
VI = 4.5 V 80
VI = 15 V
60 VI = 12 V
75
50
70
40
65
30
60
20
55
10
50
0
0 0.5 1 1.5 2 2.5 3 0 0.5 1 1.5 2 2.5 3 3.5

Figure 3. Efficiency Figure 4. Efficiency

Buck 1 at 3.3 V Buck 2 at 1 V

1 1
Vin = 12 V Vout2 = 5 V auto PSM-PWM
0.9 Vin = 12 V Vout1 = 3.3 V auto PSM-PWM 0.9

0.8 0.8

0.7 0.7

0.6 0.6

0.5 0.5 Forced PWM

Forced PWM
0.4 0.4

0.3 0.3

0.2 0.2

0.1 0.1

0 0
0 0.05 0.1 0.15 0.2 0 0.05 0.1 0.15 0.2

Figure 5. Efficiency Figure 6. Efficiency

Buck 1 at 3.3 V Buck 2 at 5 V

8 Copyright © 2011–2012, Texas Instruments Incorporated

 TPS65270
www.ti.com.cn ZHCS270C – AUGUST 2011 – REVISED APRIL 2012

TYPICAL CHARACTERISTICS (continued)

TA = 25°C, VIN = 12 V, fSW = 625 kHz (unless otherwise noted)

Figure 7. Buck 1 and Buck 2 in Steady State Figure 8. Buck 1 and Buck 2 in Steady State
IO1 = 0 A, IO2 = 0 A IO1 = 2 A, IO2 = 3 A

Figure 9. Startup With EN Figure 10. Buck 1 Load Transient

VO1 = 1.8 V, VO2 = 1.2 V VO1 = 3.3 V, IO1 = 1 A - 2 A

Figure 11. Buck 2 Load Transient Figure 12. Buck 1 and Buck 2 in PSM Mode
VO2 = 1 V, IO1 = 1 A - 2 A

Copyright © 2011–2012, Texas Instruments Incorporated 9

TPS65270
ZHCS270C – AUGUST 2011 – REVISED APRIL 2012 www.ti.com.cn

TYPICAL CHARACTERISTICS (continued)

TA = 25°C, VIN = 12 V, fSW = 625 kHz (unless otherwise noted)

Figure 13. Buck 2 Hard Short and Recover

10 Copyright © 2011–2012, Texas Instruments Incorporated

 TPS65270
www.ti.com.cn ZHCS270C – AUGUST 2011 – REVISED APRIL 2012

OVERVIEW

TPS65270 is a power management IC with two step-down buck converters. Both high-side and low-side
MOSFETs are integrated to provide fully synchronous conversion with higher efficiency. TPS65270 can support
4.5-V to 18-V input supply, 2-A continuous current for Buck 1 and 3 A for Buck 2. The buck converters have an
automatic PSM mode, which can improve power dissipation during light loads. Alternatively, the device
implements a constant frequency mode by connecting the LOW_P pin to ground. The wide switching frequency
of 300 kHz to 1.4 MHz allows for efficiency and size optimization. The switching frequency is adjustable by
selecting a resistor to ground on the ROSC pin. Input ripple is reduced by 180° out-of-phase operation between
Buck 1 and Buck 2.
Both buck converters have peak current mode control which simplifies the loop compensation. A traditional type
II compensation network can stabilize the system and achieve fast transient response. Moreover, an optional
capacitor in parallel with the upper resistor of the feedback divider provides one more zero and makes the
crossover frequency over 100 kHz. Each buck converter has an individual cycle-by-cycle current limit and low
side reverse current limit.
The device has a built-in LDO regulator. During a standby mode, the 6.5-V LDO can be used to drive MCU and
other active loads. with this LDO, system is able to turn off the two buck converters so as to reduce the power
consumption and improve the standby efficiency. Each converter has its own programmable soft start that can
reduce the input inrush current. The individual Enable pins for each independent control of each output voltage
and power sequence.

DETAILED DESCRIPTION

Adjustable Switching Frequency

To select the internal switching frequency connect a resistor from ROSC to ground. Figure 14 shows the required
resistance for a given switching frequency.
900

800

700

600
Resistance - W

500

400

300

200

100

0
0 0.5 1 1.5 2 2.5 3
fsw - Switching Frequency - MHz

Figure 14. ROSC vs Switching Frequency

ROSC(kW) = 239.13 · fSW -1.149 (1)

For operation at 800 kHz, a 300-kΩ resistor is required.

Out-of-Phase Operation
In order to reduce input ripple current, Buck 1 and Buck 2 operate 180° out-of-phase. This enables the system
having less input ripple, then to lower component cost, save board space and reduce EMI.

Delayed Start-Up
If a delayed start-up is required on any of the buck converters fit a ceramic capacitor to the ENx pins. The delay
added is ~0.75 ms per nF connected to the pin. Note that the EN pins have a weak 1-MΩ pull-up to the 5-V rail.

Copyright © 2011–2012, Texas Instruments Incorporated 11

TPS65270
ZHCS270C – AUGUST 2011 – REVISED APRIL 2012 www.ti.com.cn

Soft Start Time

The device has an internal pull-up current source of 5 µA that charges an external slow start capacitor to
implement a slow start time. Equation 2 shows how to select a slow start capacitor based on an expected slow
start time. The voltage reference (VREF) is 0.8 V and the slow start charge current (Iss) is 5 µA. The soft start
circuit requires 1 nF per 160 µs to be connected at the SS pin. An 800-µs soft-start time is implemented for all
converters fitting 4.7 nF to the relevant pins.

Tss(ms) = VREF(V) · -
( )
Css(nF)
Iss(µA)
(2)

Adjusting the Output Voltage

The output voltage is set with a resistor divider from the output node to the FB pin. It is recommended to use 1%
tolerance or better divider resistors. In order to improve efficiency at light load, start with 40.2 kΩ for the R1
resistor and use the Equation 3 to calculate R2.
æ 0.8V ö
R 2 = R1 × ç ÷
è VO - 0.8V ø (3)

Vo TPS65270
R1
FB
-
R2 +
0.8V

Figure 15. Voltage Divider Circuit

Input Capacitor
Use 10-μF X7R/X5R ceramic capacitors at the input of the converter inputs. These capacitors should be
connected as close as physically possible to the input pins of the converters.

Bootstrap Capacitor
The device has two integrated boot regulators and requires a small ceramic capacitor between the BST and LX
pin to provide the gate drive voltage for the high side MOSFET. The value of the ceramic capacitor is
recommended to be 0.047 μF. A ceramic capacitor with an X7R or X5R grade dielectric is desired because of
the stable characteristics over temperature and voltage.

Error Amplifier
The device has a transconductance error amplifier. The transconductance of the error amplifier is 130 µA/V
during normal operation. The frequency compensation network is connected between the COMP pin and ground.

Loop Compensation
TPS65270 is a current mode control dc/dc converter. The error amplifier has 130-µA/V transconductance.

12 Copyright © 2011–2012, Texas Instruments Incorporated

 TPS65270
www.ti.com.cn ZHCS270C – AUGUST 2011 – REVISED APRIL 2012

Vo

iL
Co RL

Resr
gmps=10A/V

R1 Cff
Current Sense
I/V Gain

FBx
Rc
Vref=0.8V

CRoll R2
Cc gm=130µA/V

Figure 16. Loop Compensation

A typical compensation circuit could be type II (Rc and Cc) to have a phase margin between 60 and 90 degrees,
or type III (Rc, Cc and Cff) to improve the converter transient response. CRoll adds a high frequency pole to
attenuate high-frequency noise when needed. It may also prevent noise coupling from other rails if there is
possibility of cross coupling in between rails when layout is very compact.

Copyright © 2011–2012, Texas Instruments Incorporated 13

TPS65270
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To calculate the external compensation components follow the following steps:

TYPE II CIRCUIT TYPE III CIRCUIT

Select switching frequency that is appropriate for
application depending on L, C sizes, output ripple, EMI
concerns and etc. Switching frequencies between 500 kHz
Use type III circuit for switching
and 1 MHz give best trade off between performance and
frequencies higher than 500 kHz.
cost. When using smaller L and Cs, switching frequency
can be increased. To optimize efficiency, switching
frequency can be lowered.
Select cross over frequency (fc) to be less than 1/5 to 1/10 Suggested Suggested
of switching frequency. fc = fs/10 fc = fs/10

2p × fc × Vo × Co 2p × fc × Co
Set and calculate Rc. RC = RC =
g M × Vref × gm ps g M × gm ps
Calculate Cc by placing a compensation zero at or before
the converter dominant pole
RL × Co RL × Co
1 Cc = Cc =
fp = Rc Rc
CO × RL × 2p
Add CRoll if needed to remove large signal coupling to high
impedance COMP node. Make sure that
1 Re sr × Co Re sr × Co
fpRoll = CRoll = CRoll =
2 × p × RC × CRoll RC RC
is at least twice the cross over frequency.
Calculate Cff compensation zero at low frequency to boost
the phase margin at the crossover frequency. Make sure
1
NA C ff =
that the zero frequency (fzff is smaller than soft start 2 × p × fz ff × R1
equivalent frequency (1/Tss).

Slope Compensation
The device has a built-in slope compensation ramp. The slope compensation can prevent sub harmonic
oscillations in peak current mode control when duty cycle becomes too large.

Over Current Protection

The current through the internal high side MOSFET is sampled and scaled through an internal pilot device during
the hig time. The sampled current is compared to over current limit. If the peak inductor current exceeds the over
current limit reference level, an internal over current fault counter is set to 1 and an internal flag is set. The
internal power MOSFET is immediately turned off and will not be turned on again until the next switching cycle.
The protection circuitry continues to monitor the current and turns off the internal MOSFET as described. If the
overcurrent condition persists for four sequential clock cycles, the over-current fault counter overflows indicating
an overcurrent fault condition exists. The regulator is shut down and power good goes low. If the overcurrent
condition clears prior to the counter reaching four consecutive cycles, the internal flag and counter are reset. The
protection circuitry attempts to recover from the overcurrent condition after waiting four soft-start cycles. The
internal overcurrent flag and counter are reset. A normal soft-start cycle is attempted and normal operation
continues if the fault condition has cleared. If the overcurrent fault counter overflows during soft-start, the
converter shuts down and this hiccup mode operation repeats.

Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds thermal trip
threshold. Once the die temperature decreases below 140°C, the device reinitiates the power up sequence. The
thermal shutdown hysteresis is 20°C.

14 Copyright © 2011–2012, Texas Instruments Incorporated

 TPS65270
www.ti.com.cn ZHCS270C – AUGUST 2011 – REVISED APRIL 2012

Power Dissipation
The total power dissipation inside TPS65270 should not to exceed the maximum allowable junction temperature
of 125°C to maintain reliable operation. The maximum allowable power dissipation is a function of the thermal
resistance of the package (RJA) and ambient temperature.
To calculate the temperature inside the device under continuous loading use the following procedure.
1. Define the set voltage for each converter.
2. Define the continuous loading on each converter. Make sure do not exceed the converter maximum loading.
3. Determine from the graphs below the expected losses in watts per converter inside the device. The losses
depend on the input supply, the selected switching frequency, the output voltage and the converter chosen.
4. To calculate the maximum temperature inside the IC use the following formula:
THOT_SPOT = TA + PDIS · qJA (4)
Where:
TA is the ambient temperature
PDIS is the sum of losses in all converters
θJA is the junction to ambient thermal impedance of the device and it is heavily dependant on board layout
xxx
1.7 1.7
1.6 1.6
1.5 1.5
1.4 1.4
1.3 1.3
1.2 1.2
1.1 1.1
1.0 1.0
0.9 0.9
0.8 0.8
0.7 0.7
0.6 0.6
0.5 0.5
0.4 0.4
0.3 0.3
0.2 0.2
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3

I (A) I (A)

Figure 17. Buck 1 Figure 18. Buck 1

VIN = 12 V, fSW = 500 kHz VIN = 12 V, fSW = 1.1 MHz
VO (from top to bottom) = 5 V, 3.3 V, VO (from top to bottom) = 5 V, 3.3 V,
2.5 V, 1.8 V, 1.2 V 2.5 V, 1.8 V, 1.2 V
1.6 1.6

1.4 1.4

1.2 1.2

1.0 1.0

0.8 0.8

0.6 0.6

0.4 0.4

0.2 0.2
1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6 1 1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3 3.2 3.4 3.6

I (A) I (A)

Figure 19. Buck 2 Figure 20. Buck 2

VIN = 12 V, fSW = 500 kHz VIN = 12 V, fSW = 1.1 MHz
VO (from top to bottom) = 5 V, 3.3 V, VO (from top to bottom) = 5 V, 3.3 V,
2.5 V, 1.8 V, 1.2 V 2.5 V, 1.8 V, 1.2 V

Copyright © 2011–2012, Texas Instruments Incorporated 15

TPS65270
ZHCS270C – AUGUST 2011 – REVISED APRIL 2012 www.ti.com.cn

Low Power Mode Operation

By pulling the Low_P pin high all converters will operate in pulse-skipping mode, greatly reducing the overall
power consumption at light and no load conditions. When LOW_P is tied to low, all converters run in forced PWM
mode.

Thermal Shutdown
The device implements an internal thermal shutdown to protect itself if the junction temperature exceeds 160°C.
The thermal shutdown forces the device to stop switching when the junction temperature exceeds thermal trip
threshold. Once the die temperature decreases below 140°C, the device reinitiates the power up sequence. The
thermal shutdown hysteresis is 20°C.

Layout Recommendations
Layout is a critical portion of PMIC designs.
• Place VOUT, and LX on the top layer and an inner power plane for VIN.
• Fit also on the top layer connections for the remaining pins of the PMIC and a large top side area filled with
ground.
• The top layer ground area sould be connected to the bottom ground layer(s) using vias at the input bypass
capacitor, the output filter cpacitor and directly under the TPS65270 device to provide a thermal path from the
Powerpad land to ground.
• The AGND pin should be tied directly to the power pad under the IC and the power pad.
• For operation at full rated load, the top side ground area together with the bottom ground plane, must provide
adequate heat dissipating area.
• There are several signals paths that conduct fast changing currents or voltages that can interact with stray
inductance or parasitic capacitance to generate noise or degrade the power supplies performance. To help
eliminate these problems, the VIN pin should be bypassed to ground with a low ESR ceramic bypass
capacitor with X5R or X7R dielectric. Care should be taken to minimize the loop area formed by the bypass
capacitor connections, the VIN pins, and the ground connections. Since the LX connection is the switching
node, the output inductor should be located close to the LX pins, and the area of the PCB conductor
minimized to prevent excessive capacitive coupling.
• The output filter capacitor ground should use the same power ground trace as the VIN input bypass capacitor.
Try to minimize this conductor length while maintaining adequate width.
• The compensation should be as close as possible to the COMP pins. The COMP and OSC pins are sensitive
to noise so the components associated to these pins should be located as close as possible to the IC and
routed with minimal lengths of trace.

16 Copyright © 2011–2012, Texas Instruments Incorporated

 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TPS65270PWPR ACTIVE HTSSOP PWP 24 2000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS65270

TPS65270RGER ACTIVE VQFN RGE 24 3000 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS
65270
TPS65270RGET ACTIVE VQFN RGE 24 250 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 TPS
65270

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Dec-2020

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPS65270PWPR HTSSOP PWP 24 2000 330.0 16.4 6.95 8.3 1.6 8.0 16.0 Q1
TPS65270RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
TPS65270RGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 30-Dec-2020

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TPS65270PWPR HTSSOP PWP 24 2000 853.0 449.0 35.0
TPS65270RGER VQFN RGE 24 3000 367.0 367.0 35.0
TPS65270RGET VQFN RGE 24 250 210.0 185.0 35.0

Pack Materials-Page 2
 GENERIC PACKAGE VIEW
TM
PWP 24 PowerPAD TSSOP - 1.2 mm max height
4.4 x 7.6, 0.65 mm pitch PLASTIC SMALL OUTLINE

This image is a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4224742/B

www.ti.com
 PACKAGE OUTLINE
PWP0024P SCALE 2.000
TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

6.6 C
TYP
A 6.2
PIN 1 INDEX 0.1 C SEATING
AREA 22X 0.65 PLANE
24
1

2X
7.9
7.15
7.7
NOTE 3

12
13
0.30
4.5 24X
B 0.19
4.3
0.1 C A B

SEE DETAIL A
(0.15) TYP

2X 1.00 MAX
NOTE 5

12 13
2X 0.35 MAX
NOTE 5
0.25
GAGE PLANE 1.2 MAX
2.98 25
2.08
THERMAL
PAD
0.75 0.15
0 -8 0.50 0.05
DETAIL A
A 20

1 24 TYPICAL

2.4
1.5

4224478/A 10/2018
PowerPAD is a trademark of Texas Instruments.
NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. Reference JEDEC registration MO-153.
5. Features may differ or may not be present.

www.ti.com
 EXAMPLE BOARD LAYOUT
PWP0024P TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

(3.4)
NOTE 9
(2.4)
SYMM METAL COVERED
24X (1.5) BY SOLDER MASK
1
24X (0.45) 24
SEE
DETAILS
(R0.05) TYP

22X (0.65) (2.98)

SYMM 25
(7.8)
(1) TYP NOTE 9

SOLDER MASK
DEFINED PAD
( 0.2) TYP
VIA

12 13

(1) TYP

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 8X

SOLDER MASK METAL UNDER SOLDER MASK

METAL
OPENING SOLDER MASK OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
SOLDER MASK DETAILS
15.000

4224478/A 10/2018
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
8. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
numbers SLMA002 (www.ti.com/lit/slma002) and SLMA004 (www.ti.com/lit/slma004).
9. Size of metal pad may vary due to creepage requirement.
10. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged
or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
PWP0024P TM
PowerPAD TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

(2.4)
BASED ON METAL COVERED
0.125 THICK BY SOLDER MASK
24X (1.5)
STENCIL
1
24X (0.45) 24

(R0.05) TYP

22X (0.65)
SYMM 25 (2.98)
BASED ON
0.125 THICK
STENCIL

12 13

SYMM SEE TABLE FOR

DIFFERENT OPENINGS
FOR OTHER STENCIL
(5.8) THICKNESSES

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 8X

STENCIL SOLDER STENCIL

THICKNESS OPENING
0.1 2.68 X 3.33
0.125 2.40 X 2.98 (SHOWN)
0.15 2.19 X 2.72
0.175 2.03 X 2.52

4224478/A 10/2018
NOTES: (continued)

11. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
12. Board assembly site may have different recommendations for stencil design.

www.ti.com
 GENERIC PACKAGE VIEW
RGE 24 VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

Images above are just a representation of the package family, actual package may vary.
Refer to the product data sheet for package details.

4204104/H
 PACKAGE OUTLINE
RGE0024B SCALE 3.000
VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

4.1 B
A
3.9

0.5
0.3

PIN 1 INDEX AREA

4.1
3.9
0.3
0.2

DETAIL
OPTIONAL TERMINAL
TYPICAL

C
1 MAX

SEATING PLANE
0.05
0.00 0.08 C

2X 2.5
2.45 0.1 (0.2) TYP
7 12
EXPOSED
SEE TERMINAL
THERMAL PAD
DETAIL
6 13

2X 25 SYMM
2.5

1 18
0.3
20X 0.5 24X
0.2
24 19 0.1 C A B
SYMM
PIN 1 ID
(OPTIONAL) 0.05
0.5
24X
0.3

4219013/A 05/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

www.ti.com
 EXAMPLE BOARD LAYOUT
RGE0024B VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

( 2.45)
SYMM

24 19
24X (0.6)

1
18

24X (0.25)

(R0.05)
TYP 25 SYMM

(3.8)

20X (0.5)
13
6

( 0.2) TYP
VIA
7 12
(0.975) TYP

(3.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:15X

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

SOLDER MASK
METAL OPENING

EXPOSED EXPOSED
METAL SOLDER MASK METAL UNDER
OPENING METAL SOLDER MASK

NON SOLDER MASK

SOLDER MASK
DEFINED
DEFINED
(PREFERRED)

SOLDER MASK DETAILS

4219013/A 05/2017
NOTES: (continued)

4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.

www.ti.com
 EXAMPLE STENCIL DESIGN
RGE0024B VQFN - 1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD

4X ( 1.08)
(0.64) TYP
24 19

24X (0.6)

1
25
18

24X (0.25)

(R0.05) TYP (0.64)

TYP
SYMM

(3.8)

20X (0.5)
13
6

METAL
TYP

7 12
SYMM

(3.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL

EXPOSED PAD 25
78% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
SCALE:20X

4219013/A 05/2017

NOTES: (continued)

6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.

www.ti.com
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