Progress Report

1st Mohammad Asif Ikbal

Departement of Electronics Engineering, Z.H.C.E.T.
Aligarh Muslim University
Aligarh, India
asifiqbal068@gmail.com

Abstract—In this report, the author provides a brief summary

of one week of learning at the new research lab under the
guidance of Dr. Mohammad Wajid. During this period, the
author developed a foundational understanding of digital design
implementation on hardware using the Vivado 2023 software
suite by Xilinx and successfully implemented various designs
on the Xilinx XC7S50-CS324A Spartan-7 FPGA. This FPGA
board offers a versatile and programmable hardware platform
for developing and testing digital designs across various applica-
tions. Additionally, the author gained an understanding of scan
chain techniques, which are employed for testing and debugging
integrated circuits (ICs), including FPGAs and ASICs.
Index Terms—component, formatting, style, styling, insert

I. OBJECTIVE -1
The first objective was to develop a sound understanding of
the steps to be followed for using Vivado and implementing
the design of a Boolean board. The author’s understanding
is summarized in the flow diagram shown in the fig 1. That
illustrates the key steps involved in FPGA design using the
Vivado Design Suite. The process is divided into six intercon-
nected stages: 1. Define Requirements: Establish the functional
and performance specifications for the FPGA design. 2. De-
sign Logic Circuit: Create the logic circuit using Hardware
Description Languages (HDLs) like Verilog or VHDL. 3.
Verify Functionality: Check the correctness of the design logic Fig. 1. Vivado Project implementation process
through simulation or formal verification. 4. Simulate Design:
Run test cases to simulate the behavior of the logic design
before implementation. 5. Synthesize Design: Convert the
high-level HDL code into a gate-level netlist optimized for
the target FPGA device. 6. Implement Design: Map, place,
and route the design onto the physical FPGA fabric, making it
ready for programming. This diagram emphasizes the iterative
and systematic approach to FPGA design in Vivado, ensuring
correctness and optimization at every stage. The author be-
gins with basic logic gates, progresses to combinational and
sequential logic, and concludes by implementing FSM.

A. Implementation of D Flip-flop
A D flip-flop is a sequential element that follows the input
pin D at the given edge of a clock. In the implemented design,
shown in Fig-3 we have used an enable input as well as a reset
input. The waveform in Fig. 2(a) represents the behavior of
Fig. 2. Implementation result of (a) D flip-flip, (b) counter, (c) FSM-Parity
generator
 Fig. 3. D Flip-Flop Fig. 5. Schematic of the FSM-Parity generator

Fig. 4. Schematic of the implemented Counter

the D flip-flop for the test condition defined in the testbench

file.

B. Implementation of the Counter

In this section the author has implemented a counter shown Fig. 6. Understanding Scan Chain
in fig 4. This schematic represents a 4-bit counter circuit
designed and simulated using FPGA design tools like Vivado.
The primary components in the schematic include: If the number of ones received by the circuit is odd, its output
1. Inputs: - ‘clock‘: The clock signal driving the counter. - will be one; otherwise, it will be zero. The desired operation
‘reset‘: Resets the counter to its initial state. 2. Components: can be observed in the waveform represented in Fig. 2(c).
-IBUF/IBUFG: Input buffers that condition the clock and reset
signals for use in the circuit. - FDCE: Flip-flops used as the II. OBJECTIVE -2
core of the counter, storing and updating the count values at
each clock cycle. - LUTs (Look-Up Tables): Combinational The second task was to learn the basics of Scain Chain tech-
logic used to implement counter logic and control the next nique. This is used in digital design and testing, particularly for
state of the flip-flops. - OBUF: Output buffers that drive verifying integrated circuits (ICs) like FPGAs and ASICs. It is
the counter outputs (‘count[3:0]‘) and an additional signal a form of Design for Testability (DFT) that facilitates testing
(‘maxtick‘). 3. Functionality: - The counter increments its and debugging by making internal registers and flip-flops in a
value on each rising edge of the clock. - If the ‘reset‘ signal is circuit more accessible for testing purposes. For understanding
active, the counter resets to ‘0‘. - The ‘maxtick‘ signal might the concept of scan chain, consider a complicated digital
indicate a specific event (e.g., when the counter reaches its circuit consisting both sequential blcok and combinatioanl
maximum value). This schematic reflects ongoing learning block. Testing this kind of circuit poses significant challenges
and understanding of FPGA-based design and simulation due to the controllability and observability issues caused by
tools.It demonstrates the use of key Vivado features such as flip-flops, as they obscure access to internal nodes. To address
HDL synthesis, simulation, and schematic visualization for this, the circuit can be partitioned into two components: the
implementing digital circuits. The output waveform of the combinational circuit and the flip-flops, as shown in fig-6. The
implemented desgin is shown in fig 2(b). As it is a 4-bit combinational circuit, which includes next-state and output
counter it upcounts from 0 to 15. At the count 15 the maximum logic, is separated from the flip-flops to simplify testing. The
count signal become high, and reset the counter to start the outputs from flip-flops to the combinational circuit are termed
count from 0. pseudo-primary inputs, while the inputs from the combina-
tional circuit to the flip-flops are pseudo-primary outputs. By
C. Implementation of Parity generator isolating the flip-flops and focusing on testing the combina-
In this section, the author has implemented a basic Moore tional portion using automated test pattern generation (ATPG)
Machine, known as a Parity Generator, as shown in Fig. 5. methods like D-algorithm or PODEM, the complexities of flip-
The circuit receives a random sequence of zeros and ones, flop control are mitigated. However, this requires replacing
and depending on the number of ones, it generates the output. standard flip-flops with special scan flip-flops, enabling their
initialization, control, and observation from outside the chip.
The Key steps for this process includes:
1) Reading the Verilog Design: The Verilog code describ-
ing the sequential circuit is read.
2) Setting Design Constraints: Timing constraints, such as
clock period, input/output delays, and setup/hold times,
are defined.
3) Creating Scan Chain Configuration: The number of scan
chains and the assignment of flip-flops to chains are
specified.
4) Inserting Scan Flip-Flops: The synthesis tool replaces
regular flip-flops with scan flip-flops and adds the nec-
essary scan control signals.
5) Generating Test Patterns: Test patterns are generated to
exercise all possible states of the circuit.
6) Performing Timing Analysis: Timing analysis is per-
formed to ensure that the design meets timing require-
ments, even after scan insertion.
The Key Commands to Learn for using Synopsys Design
Compiler, includes, but is not limited to, the following, is
mentioned.
1) setd f ts ignal: Defines DFT signals like scan input, scan
output, and scan enable.
2) createt estp rotocol: Creates a test protocol based on the
specified scan chain configuration.
3) df td rc: Checks for design rule violations related to scan
design.
4) sets canc onf iguration: Configures the scan chain pa-
rameters, such as the number of scan chains and the
assignment of flip-flops.
5) insertd f t: Inserts scan flip-flops and connects them to
form the scan chain.
6) df tc overagee stimate: Estimates the fault coverage
achieved by the scan test.
By following these steps and using the appropriate Synopsys
Design Compiler commands, designers can effectively imple-
ment scan design and improve the testability of their sequential
circuits.