Department of Collegiate and Technical Education

Department of
Electronics & Communication Engineering

HDL LABORATORY (18ECL77)

( VII Semester)
Experiment No - 01
INTRODUCTION TO CMOS VLSI

Session # 01
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 VLSI LABORATORY
Subject Code: 18ECL77 IA Marks: 40
No. of Practical Hrs/Week : 03 Exam Hours: 03
Total no. of Practical Hrs. : 42 Exam Marks: 60
Experiments can be conducted using any of the following or equivalent design tools: Cadence/Synopsis/Mentor
Graphics/Microwind
Laboratory Experiments
Part-A
Analog Design
Use any VLSI design tools to carry out the experiments, use library files and technology files below 180 nm.

l.a) Capture the schematic of CMOS inverter with load capacitance of 0.1pF and set the widths of inverter with Wn = Wp, Wn =
2Wp, Wn = Wp/2 and length at selected technology. Carry out the following:
i Set the input signal to a pulse with rise time, fall time of 1ns and pulse width of 10ns and time period of 20ns and plot the
input voltage and output voltage of designed inverter?
ii. From the simulation results compute tpHL, tpLH and td for all three geometrical settings of width?
iii Tabulate the results of delay and find the best geometry for minimum delay for CMOS inverter?
1.b) Draw layout of inverter with Wp/Wn =40/20, use optimum layout methods. Verify for DRC and LVS, extract parasitic and
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perform post layout simulations,
Department of Electronics with
compare the results pre-layout simulations.
and Communication Record
Engineering the observations.
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2. a) Capture the schematic of 2-input CMOS NAND gate having similar delay as that of CMOS inverter computed in experiment Verify the
functionality of NAND gate and also find out the delay td for all four possible combinations of input vectors. Table the results. Increase the
drive strength to 2X and 4X and tabulate the results.
2. b) Draw layout of NAND with Wp/Wn =40/20, use optimum layout methods. Verify for DRC and LVS, extract parasitic and perform post
layout simulations, compare the results with pre-layout simulations. Record the observations.
3. a) Capture schematic of Common Source Amplifier with PMOS Current Mirror Load and find its transient response and AC response?
Measures the Unity Gain Bandwidth (UGB), amplification factor by varying transistor geometries, study the impact of variation in width to
UGB.
3. b) Draw layout of common source amplifier, use optimum layout methods. Verify for DRC and LVS, extract parasitic and perform post layout
simulations, compare the results with pre-layout simulations. Record the observations.
4.a) Capture schematic of two-stage operational amplifier and measure the following:
i UGB ii. dB bandwidth iii. Gain margin and phase margin with and without coupling capacitance
iv. Use the op-amp in the inverting and non-inverting configuration and verity its functionality
v. Studythe UGB, 3dB bandwidth, gain and power requirement in op-amp by varying the stage wise transistor geometries and record the
observations.
4.b) Draw layout of two-stage operational amplifier with minimum transistor width set to 300 (in 180/90/45 nm technology), choose
appropriate transistor geometries as per the results obtained in 4.a. Use optimum layout methods. Verity for DRC and LVS, extract parasitic and
perform post layout simulations, compare the results with pre-layout simulations. Record the observations.
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 Part -B
Digital Design
Carry out the experiments using semicustom design flow or ASIC design flow, use technology library 180/90/45nm and below
Note: The experiments can also be carried out using FPGA design flow, it is required to set appropriate constraints in FPGA
advanced synthesis options
1. Write verilog code for 4-bit up/down asynchronous reset counter and carry out the following:
a Verity the functionality using test bench
b. Synthesize the design bysetting area and timing constraint. Obtain the gate level netlist, find the critical path and maximum
frequency of operation. Record the area requirement in terms of number of cells required and properties of each cell in term
of driving strength, power and area requirement.
c. Perform the above for 32-bit up/down counter and identity the critical path, delay of critical path, and maximum frequency
of operation, total number of cells required and total area.
2. Write verilog code for 4-bit adder and verity its functionality using test bench. Synthesize the design by setting prope
constraints and obtain the net list. From the report generated identity critical path, maximum delay, total number of cells
power requirement and total area required. Change the constraints and obtain optimum synthesis results .

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3. Write verilog code for UART and carry out the following:
a Perform functional verification using test bench
b. Synthesize the design targeting suitable library and by setting area and timing constraints
c. For various constrains set, tabulate the area, power and delay for the synthesized netlist
d Identity the critical path and set the constraints to obtain optimum gate level netlist with suitable constraints
4.Write verilog code for 32-bit ALU supporting four logical and four arithmetic operations, use case statement and if statement for ALU
behavioral modeling.
a Perform functional verification using test bench
b. Synthesize the design targeting suitable library by setting area and timing constraints
c. For various constrains set, tabulate the area, power and delay for the synthesized netlist
d Identity the critical path and set the constraints to obtain optimum gate level netlist with suitable constraints Compare the synthesis results
of ALU modeled using IF and CASE statements.
5.Write verilog code for Latch and Flip-flop, Synthesize the design and compare the synthesis report (D, SR, JK).
6. For the synthesized netlist carry out the following for any two above experiments:
a Floor planning (automatic), identity the placement of pads
b. Placement and Routing, record the parameters such as no. of layers used for routing, flip method for placement of standard cells, placement
of standard cells, routes of power and ground, and routing of standard cells
c. Physical verification and record the LVS and DRC reportsElectronics & communication ,18ECL77
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 Course Outcomes:

CO1: Be able to design analog circuits at CMOS transistor level and verify its functionality by DC, AC and transient
analysis.
CO2: Be able to draw layout & apply CMOS technology-specific layout rules for placement and routing of transistors and
interconnect.
CO3: Able to write Verilog code for combinational and sequential circuits, with their test bench to verify initial timing
and gate level simulation.
CO4: Be able to complete a VLSI design projects having a set of objectives and design constraints.

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 Introduction

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 PART-A
ANALOG DESIGN
General notes
Lab getting started:

Login to your system using the username and password.

Right click on the desktop, select tools option to access the terminal window
In a terminal window, type csh at the command prompt to invoke C shell.
>csh
>source cshrc //cshrc file contains paths to the cadence installation.
>cd Database
>cd analog
>cd adelab
>virtuoso &

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 The virtuoso or Command Interface Window (CIW) appears at the bottom of the screen.

 If the “What’s New…” window appears, close it with the File-Close command.
 Keep opened CIW window for the labs.

 General Procedures
 1. Creating a new Library:

Click File-New-Library. New library window will open

Create your own library by typing some name in the library name field
Add the created library to the existing library by selecting option “Attach an existing technology library” and click ok.
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  In the “Attach Design Library to
technology file” form, select
gpdk180 from the cyclic field and
click ok

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2. Creating a Schematic Cellview:

 In the CIW or Library manager, execute File-

New-Cellview.
 Setup the new file form by selecting the
library name in the Library tab,
provide a cell name in the Cell tab and
select the type as Schematic and open
with Schematics XL option and click
ok.

Click ok. A blank schematic editor window appears

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 1. Adding Components to Schematics:

 In the schematic editor window click create-instance-browse. This opens up a library browser from which you can select
the components. The browser window has 4 different fields – Library, Category, Cell & View
o In order to select pmos , select the 4 fields as
gpdk180 – mos – pmos – symbol
o In order to select nmos , select the 4 fields as
gpdk180 – mos – nmos – symbol

• After you complete the add instance form,

move your cursor to the schematic window
and click left to place a component. If you
place a component with wrong parameter
values, use the Edit-Properties-Objects
command to change the parameter. Use Edit-
Move command if you place components in
the wrong location. You can rotate components
using Edit-Rotate command.

• After entering components, click cancel in the Add

instance form or press Esc.

• Similarly place the required components in the

schematic editor window

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Set pmos/nmos properties like length=180nm,width=2um as shown above.

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  Similarly select gnd from the library browser
and place it in the schematic editor window.
After placing the sources, click cancel in the
Add instance form or press Esc.

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1. Adding Pins to Schematic: • Name the pins in Pin Names tab and select the direction of
In the schematic editor window click create-pins, corresponding pin in the
this opens up a Add Pin form Direction tab and place it in the schematic editor window.
For example :Pin Names – X, Direction – input for input pin
Pin Names – Y, Direction – output for output
pin

After placing the pins Press ESC to exit Add Pins form
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6. Adding Wires to a Schematic:
 Click the wire (narrow) icon in the schematic window.
 In the schematic window, click on a pin of one of
your components as the first point for your
wiring. A diamond shape appears over the
starting point of this wire.Follow the prompts at
the bottom of the design window and click left
on the destination point for your wire. A wire is
routed between the source and destination points.
 Complete the wiring as shown in figure and
when done wiring press ESC key in the
schematic window to cancel wiring.
7. Click the Check and Save icon in the Schematic editor
window.
8. Observe the CIW output area for any errors

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 Symbol Creation:
 In the schematic window, run Create -Cellview -From Cellview.
The Cellview form appears.as shown below and press ok

 Verify library name, cell name, and check the To View Name
field is set to
symbol, Click ok.
 Modify the pin specification.( if necessary for
top and bottom pins) And Click ok.

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 Editing a Symbol:
 Select delete option and delete all the rectangles present in the window except pins and pin names

 Set the input and output pins to the required position as shown in the figure

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 Draw the symbol for the respective circuit by selecting Create-Shape- line/circle etc .After creating the shape press ESC key.

 After creating symbol, click on the save

icon in the symbol editor window to save
the symbol. In the symbol editor,go to
File select Close option to close the
symbol view window and schematic
window.

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 To circuit:
In the CIW again go to File-New Cellview and give different name in the cell field and click ok and check/select your
library name in the library fieldcreate the test

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 Again a new schematic editor window will gets open

 In this window click Create instance browse select your library name and select inverter and
symbol in the corresponding field and press close

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Then place the symbol into the schematic editor window

 Provide the input voltage to the test circuit by selecting Vpulse in library window using the following steps

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Create-instance–browse–Select analoglib-independent-Vpulse-symbol - close.

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Then set the specifications for Vpulse as
Voltage1=0 Period=20n
Voltage2=5 Pulsewidth=10n

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 Click hide and place the symbol near the input terminal in the test circuit. Select wire option and connect one terminal of
Vpulse to the schematic symbol input terminal and the other terminal to gnd. Then create one output pin as create-pin-
enter pin name-set pin direction as output-click ok-place near the output terminal and connect pin to the output terminal
using wire.

Select Gnd and VDD symbol from analoglib library by following the steps Create -instance-browse-analoglib-sources-Global-
select-gnd-symbol-close. Create -instance-browse-analoglib-sources-Global-select-V dd-symbol-close
 After selecting place them in the appropriate position as shown in the figure. To create biasing circuit select biasing
voltage VDC by following the steps
 Create-instance-browse-analoglib-sources-Global-select-VDC-symbol-close.Then set the properties of Vdc as dc
voltage=5v, shown below

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  Click the save icon and finally the test
circuit and biasing circuit is ready for
simulation as shown below

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 Simulation with Spectre:

 In the schematic window, run Launch-ADE L, the following window will appears

In the simulation window click on setup-

Model Libraries tab and press ok

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 Click the Analysis icon tab in the ADE-L window and select the Choose

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 To setup for transient analysis select tran icon, set the Stop Time for 100ns click at the moderate or
enabled button at the bottom, click Apply.

 To setup for DC analysis select dc, turn on Save Dc Operating Point. Turn on the Component
Parameter. Double Click on the select Component, which takes you to the schematic window.
Select input signal, Vpulse and select component parameter as DC. Set start time=0 and stop time
=5 voltages. Click Apply and ok.

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Selecting outputs for plotting
 Execute Outputs- To be plotted- Select on Schematic in the simulation window.

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Follow the prompt at the bottom of the schematic window, click on the output net, input net of the design. Press ESC with
the cursor in the schematic after selecting it

Execute Simulation-Netlist and Run to start the simulation.

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 LMS-KARNATAKA

E-CONTENT MODERATOR: R. PREMANANDA

Assistant Professor
Department of Electronics & Communication
Government Engineering College, Haveri

E-CONTENT DEVELOPER: R. PREMANANDA

Assistant Professor
Department of Electronics & Communication
Government Engineering College, Haveri

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 THANK YOU

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