The IAS Machine (Institute for Advanced Study Machine), developed under

the guidance of John von Neumann, was one of the first computers to use
the Von Neumann Architecture. The core idea of the IAS machine was to
use stored programs, where both data and instructions are stored in
memory.

Key Components of the IAS Machine

1. Control Unit (CU):

o The Control Unit manages the operations of the computer by

directing the flow of data between components (like memory,
registers, and the ALU).

o It generates control signals that orchestrate the fetch-execute

cycle of the computer.

2. Arithmetic Logic Unit (ALU):

o The ALU performs all arithmetic operations (addition,

subtraction, etc.) and logical operations (AND, OR, NOT, etc.).

o The ALU uses the accumulator register to store intermediate

results.

3. Memory:

o The IAS machine had primary memory to store both data and
instructions.

o Memory was accessed via addresses, and both data and

instructions were stored as binary values (in the form of 40-bit
words).

o The memory had a word size of 40 bits and was divided into
multiple locations.

4. Registers:

o The IAS machine had several types of registers:

 Program Counter (PC): Holds the address of the next

instruction to be executed.

 Accumulator (AC): Holds intermediate results of

arithmetic and logical operations.
  Memory Buffer Register (MBR): Holds data fetched
from memory.

 Memory Address Register (MAR): Holds the address of

the memory location to be accessed.

 Instruction Register (IR): Holds the current instruction

being decoded and executed.

5. Input/Output Devices:

o The IAS machine could interact with external devices to input

data or output results.

6. Bus:

o The machine had data, address, and control buses that carried
the data, addresses, and control signals between various
components (like the ALU, memory, and registers).

Working of the IAS Machine (Fetch-Decode-Execute Cycle)

The IAS machine followed a fetch-decode-execute cycle that repeats

continuously to process instructions. Here’s how it worked:

1. Fetch

 The Control Unit fetches the next instruction from memory using the
address stored in the Program Counter (PC).

 The Memory Address Register (MAR) is loaded with the address of

the instruction, and the instruction is placed in the Instruction
Register (IR).

2. Decode

 The instruction in the IR is decoded by the Control Unit to determine

what operation is needed.

 The Control Unit sends appropriate signals to the ALU (for arithmetic
or logical operations) or to memory (for read/write operations).

3. Execute

 The decoded instruction is executed:

 o If it's an arithmetic or logical operation, the ALU performs it, and
the result is stored in the Accumulator (AC).

o If it's a memory operation, data is read from or written to

memory.

o The Program Counter (PC) is updated to point to the next

instruction (i.e., incremented).

4. Repeat

 The process repeats for every new instruction, which is fetched,

decoded, and executed.
1. Fetch Phase
  Step 1: Instruction Fetch

o The Program Counter (PC) contains the address of the next

instruction in Main Memory (M) to be executed.

o This address is sent to the Memory Address Register (MAR).

o The instruction at that memory address is fetched and placed

into the Memory Buffer Register (MBR).

 Step 2: Instruction Decode

o The instruction fetched is split into two parts: the operation

code (opcode) and the operand(s).

o The opcode specifies what operation to perform (e.g., addition,

subtraction), and the operand specifies the data or address
involved.

o These parts are temporarily held in the Instruction Register

(IR) and, if needed, in the Instruction Buffer Register (IBR)
for further processing.

2. Decode Phase

 The Control Circuits decode the instruction stored in the IR.

 Based on the opcode, the control unit sends the necessary control
signals to the relevant components:

o For arithmetic or logic operations, control signals direct the

Arithmetic Logic Unit (ALU).

o For memory-related instructions, signals coordinate the memory

read/write process.

3. Execute Phase

 Arithmetic and Logic Operations:

o Data required for computation is fetched from Main Memory

(M) and placed in registers like the Accumulator (AC) or
Multiplier Quotient (MQ).
 o The ALU performs the desired operation (e.g., addition,
subtraction, logical comparisons).

 Memory Operations:

o For a Read operation: Data is fetched from Main Memory to the

MBR and then transferred to a register (e.g., AC or MQ).

o For a Write operation: Data from the AC is sent via the MBR to a
specific memory address specified in the MAR.

 Program Control:

o If the instruction is a branch or jump, the PC is updated to point

to the new instruction address.

4. Store Phase

 After computation or processing, the result can be:

o Stored in Main Memory: Data is written back to a specific

memory location via the MAR and MBR.

o Sent to Input/Output Equipment: The result is sent to

external devices for user interaction or further processing.

Key Example: Addition of Two Numbers

1. Fetch:

o The instruction "ADD A, B" is fetched from memory.

2. Decode:

o The control unit decodes it as: Fetch data from memory locations
A and B, add them, and store the result in the Accumulator
(AC).

3. Execute:

o The control unit signals the ALU to retrieve the values from
memory, perform the addition, and store the result in AC.

4. Store:
 o The result in AC is stored back into memory or sent to the output
device.

Cycle Continuation

 After executing an instruction, the PC is incremented to point to the

next instruction in memory, and the cycle begins again with the next
fetch phase.

 This process repeats continuously until the program completes.

Key Takeaways:

1. Sequential Execution: Instructions are fetched, decoded, and

executed one at a time.

2. Shared Memory: Both instructions and data reside in the same

memory space, leading to potential bottlenecks.

3. Registers: Temporary storage (e.g., AC, MQ, MBR) ensures smooth

data flow during execution.

This working principle highlights the simplicity and modular design of the Von
Neumann architecture, which remains foundational to modern computer
systems.

Example :

Data/Instruction

Memory
Location

00A H LOAD M(00C H), ADD

M(00D H)

00B H STOR M(00C H)

00C H 5

00D H 7
This shows how a sequence of instructions is fetched, decoded, and
executed, with the final result stored in memory.

PC= 00A H

MAR=00A H

MBR=LOAD M(00C H), ADD M(00D H)

IBR=ADD M(00D H)

IR=00000001

MAR=00C H

MBR=5

AC=5

IR=00000101

MAR=00D H

MBR=7

AC=12

PC= 00B H

IR=00100001

MAR=00B

MBR=STOR M(00C H)

00C H->12

mage 1: Memory and Instructions

This table represents the memory layout:

Memory
Data/Instruction
Location

LOAD M(00C H), ADD

00A H
M(00D H)

00B H STOR M(00C H)

00C H 5
Memory
Data/Instruction
Location

00D H 7

 00A H contains two instructions:

o LOAD M(00C H): Load the value at address 00C H (which is 5)

into the accumulator (AC).

o ADD M(00D H): Add the value at address 00D H (which is 7) to

the accumulator (AC).

 00B H contains STOR M(00C H):

o Store the result in the accumulator back into memory address

00C H.

 00C H contains 5, and 00D H contains 7, which are data values.

Image 2: Execution Process

This image traces how the instructions execute step by step within the CPU:

1. Instruction Fetch at 00A H:

 Program Counter (PC) = 00A H: This points to the first instruction.

 Memory Address Register (MAR) = 00A H: Fetches the content of

memory at 00A H.

 Memory Buffer Register (MBR) = LOAD M(00C H), ADD M(00D

H):

o The fetched instruction contains two operations.

o Instruction Register (IR) = 00000001: Decodes LOAD M(00C

H).

2. Execute LOAD M(00C H):

 MAR = 00C H: Fetch the value at 00C H.

 MBR = 5: Data at 00C H is 5.

 Accumulator (AC) = 5: The accumulator now holds 5.

3. Execute ADD M(00D H):

 IR = 00000101: Decodes ADD M(00D H).

 MAR = 00D H: Fetch the value at 00D H.

 MBR = 7: Data at 00D H is 7.

 AC = 12: Adds 7 to the accumulator (5 + 7 = 12).

4. Instruction Fetch at 00B H:

 PC = 00B H: Move to the next instruction.

 IR = 00100001: Decodes STOR M(00C H).

 MAR = 00C H: Specifies the address to store the accumulator's value.

 MBR = 12: Updates memory location 00C H to 12.

Final State

 Memory Updates:

o 00C H = 12 (previously 5, now updated after execution).

 Accumulator (AC): Holds the result 12.

Summary

1. LOAD M(00C H): Loads 5 into the accumulator.

2. ADD M(00D H): Adds 7 to the accumulator, resulting in 12.

3. STOR M(00C H): Stores 12 back into memory location 00C H.

The final memory state is:

Memory
Value
Location

Instruction
00A H
s

00B H Instruction

00C H 12
Memory
Value
Location

00D H 7

2.

Memory Data/Instruction
Location

1 LOAD 300, ADD 301

2 STOR 300

300 5

301 7

• The data 5 and 7 are loaded at the memory location

300 and 301 respectively
• LOAD M(X) 300: will load the data of the address
300 (5) to the AC
• ADD M(X) 301: will add the data of the location
301 (7) to the data of the AC (5) and overwrite the
data of AC (5) by the result of addition (12)
• STOR M(X) 300: will store the data of AC (12) to
the memory location 300 (in this case overwriting)